JPH0515405U - Stacked Chip Thermistor - Google Patents

Stacked Chip Thermistor

Info

Publication number
JPH0515405U
JPH0515405U JP6050491U JP6050491U JPH0515405U JP H0515405 U JPH0515405 U JP H0515405U JP 6050491 U JP6050491 U JP 6050491U JP 6050491 U JP6050491 U JP 6050491U JP H0515405 U JPH0515405 U JP H0515405U
Authority
JP
Japan
Prior art keywords
chip thermistor
electrodes
resistance value
initial resistance
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6050491U
Other languages
Japanese (ja)
Inventor
昭一 岩谷
信之 三木
吾郎 武内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP6050491U priority Critical patent/JPH0515405U/en
Publication of JPH0515405U publication Critical patent/JPH0515405U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】 (修正有) 【目的】 チップサーミスタ素子の素材組成、形状を変
えることなく、チップサーミスタとしての初期抵抗値が
制御でき、高精度、かつ均一な積層型チップサーミスタ
を提供することを目的とする。 【構成】 チップサーミスタ素子のセラミック積層体5
a,5bの両端に外部電極7a,7bが形成され、該セ
ラミック積層体の一積層面に、一方の外部電極7aに接
続するように形成された内部電極6aと、他方の外部電
極7bに接続する一積層面に形成された内部電極6bが
重畳することなく対向するようにする。上記構成におい
て、内部電極6a,6b間距離Lあるいは積層数を変え
ることにより、チップサーミスタとしての初期抵抗値の
制御が可能となり、また電極が内部電極6a,6bで構
成されるため、外部電極7a,7b形成時における電極
溶解や素体の脱落現象を起こすことなく、安定した電極
間距離Lを保つことができ、チップサーミスタの初期抵
抗値の高精度化,均一化を図ることができる。
(57) [Summary] (Modified) [Purpose] To provide a highly accurate and uniform multilayer chip thermistor that can control the initial resistance value of the chip thermistor without changing the material composition and shape of the chip thermistor element. The purpose is to [Structure] Ceramic laminated body 5 of chip thermistor element
External electrodes 7a and 7b are formed on both ends of a and 5b, and an internal electrode 6a formed to be connected to one external electrode 7a and an external electrode 7b on the other side are connected to one laminated surface of the ceramic laminated body. The internal electrodes 6b formed on one stacked surface are opposed to each other without overlapping. In the above structure, the initial resistance value of the chip thermistor can be controlled by changing the distance L between the internal electrodes 6a and 6b or the number of stacked layers. Further, since the electrodes are composed of the internal electrodes 6a and 6b, the external electrode 7a , 7b can be maintained without causing electrode melting or dropping of the element body, and the initial resistance value of the chip thermistor can be made highly accurate and uniform.

Description

【考案の詳細な説明】[Detailed description of the device]

【0001】[0001]

【産業上の利用分野】[Industrial applications]

本考案は、温度センサとして各種民生機器等に利用される積層型チップサーミ スタに関する。 The present invention relates to a laminated chip thermistor used as a temperature sensor in various consumer devices and the like.

【0002】[0002]

【従来の技術】[Prior Art]

これまでのチップサーミスタは、図6に示すように、直方体状に形成されたセ ラミック素体1の両端外周をAg−Pd合金等で覆うように端部電極2a,2b を設け形成されている。 In the conventional chip thermistor, as shown in FIG. 6, end electrodes 2a and 2b are formed so as to cover the outer peripheries at both ends of a rectangular parallelepiped ceramic element body 1 with Ag-Pd alloy or the like. ..

【0003】 そして、上記チップサーミスタの初期抵抗値は、セラミック素体1の組成,形 状寸法(体積),あるいは電極間距離で決定される。しかしながら、図6に示す ように、端部電極にAg−Pd系の合金を用いると、セラミック素体全面に均一 に電極塗布形成する際、形状効果の影響を受け、電極間距離L1の精度が低下し 、チップサーミスタとしての初期抵抗値の精度も低下する。The initial resistance value of the chip thermistor is determined by the composition, shape dimension (volume), or inter-electrode distance of the ceramic body 1. However, as shown in FIG. 6, when an Ag-Pd alloy is used for the end electrodes, when the electrodes are uniformly applied and formed on the entire surface of the ceramic body, the shape effect affects the accuracy of the inter-electrode distance L1. As a result, the accuracy of the initial resistance value of the chip thermistor also decreases.

【0004】 また、図7は、端部電極4a,4bをセラミック素体3の両端外周にCu,N i,Sn−Pb等のメッキ電極で形成した場合であるが、図に示すようにメッキ 反応時に素地が溶け、素体の脱落現象を生じる場合があり、実質的な電極間距離 L2が変化し、初期抵抗値の非均一化につながる。Further, FIG. 7 shows a case where the end electrodes 4a and 4b are formed by plating electrodes of Cu, Ni, Sn-Pb or the like on the outer peripheries of both ends of the ceramic body 3, but as shown in FIG. The base material may melt during the reaction to cause a dropout phenomenon of the base body, and the substantial inter-electrode distance L2 changes, leading to non-uniform initial resistance.

【0005】[0005]

【考案が解決しようとする課題】[Problems to be solved by the device]

このように従来のチップサーミスタは、その電極形成段階において、電極間距 離を一定に保つことが困難で、そのため、チップサーミスタ素子の初期抵抗値の 精度が低下し、かつ非均一になるという問題がある。 As described above, in the conventional chip thermistor, it is difficult to keep the distance between the electrodes constant at the stage of forming the electrodes, and therefore, there is a problem that the accuracy of the initial resistance value of the chip thermistor element deteriorates and becomes nonuniform. is there.

【0006】 そこで本考案は上記事情に鑑みてなされたものであり、精度が高く、また均一 な初期抵抗値を有する積層型チップサーミスタを提供することを目的とするもの である。Therefore, the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multilayer chip thermistor having high accuracy and a uniform initial resistance value.

【0007】[0007]

【課題を解決するための手段】[Means for Solving the Problems]

上記目的を達成するために本考案は、セラミック積層体の両端に外部電極が形 成され、該セラミック積層体の一積層面に、一方の外部電極に接続するように形 成された内部電極と、他方の外部電極に接続する一積層面に形成された内部電極 の各先端部が、間隔を保って、重畳することなく、対向するようにしたものであ る。 In order to achieve the above object, the present invention provides an external electrode formed at both ends of a ceramic laminate, and an internal electrode formed to be connected to one external electrode on one laminated surface of the ceramic laminate. The respective tip portions of the internal electrodes formed on one laminated surface connected to the other external electrode are opposed to each other with a gap maintained therebetween without overlapping.

【0008】[0008]

【作用】[Action]

上記構成のチップサーミスタによれば、セラミック素体を積層状に形成し、1 乃至2の積層面に電極を、前記セラミック素体の両端に設けられた端部電極にそ れぞれ接続されるように形成することで、電極形成時における形状効果の影響や 素体の脱落現象を起こすことなく、安定した電極間距離を保つことができ、チッ プサーミスタの初期抵抗値の高精度化,均一化を図ることができる。 According to the chip thermistor having the above-mentioned configuration, the ceramic element bodies are formed in a laminated shape, and the electrodes are connected to the laminated surfaces 1 and 2 respectively to the end electrodes provided at both ends of the ceramic element body. By doing so, it is possible to maintain a stable distance between the electrodes without the influence of the shape effect during electrode formation and the phenomenon of the element falling off, and to improve the accuracy and uniformity of the initial resistance of the chip thermistor. Can be promoted.

【0009】[0009]

【実施例】【Example】

以下に本考案の実施例を図面を参照して詳述する。 Embodiments of the present invention will be described below in detail with reference to the drawings.

【0010】 図1は本考案の第1の実施例におけるチップサーミスタの断面を示すものであ り、2つの薄板状セラミック素体5a,5bを重ね合わせて積層状に形成してい る。そして図2に示すように、上記2つのセラミック素体5a,5bは、2つの セラミック層として上層の裏面及び下層の表面にそれぞれ内部電極6a,6bが 蒸着,スパッタリング,厚膜印刷等で形成され、上記内部電極が同一平面上に相 互に間隔を保って対向するように配置されるように熱圧着され、セラミック素体 5の両端外周に外部電極7a,7bが形成されている。ここで、内部電極間距離 Lと外部電極の最短距離L0とはL<L0,外部電極の最短距離L0とセラミッ ク素体の長手方向の寸法Wとは、ほぼ等しい関係を有するように形成する。FIG. 1 shows a cross section of a chip thermistor according to a first embodiment of the present invention, in which two thin plate-shaped ceramic bodies 5a and 5b are superposed and formed in a laminated shape. As shown in FIG. 2, the two ceramic elements 5a and 5b have two ceramic layers on which the internal electrodes 6a and 6b are respectively formed on the back surface of the upper layer and the surface of the lower layer by vapor deposition, sputtering, thick film printing or the like. The internal electrodes are thermocompression-bonded on the same plane so as to be opposed to each other with a space therebetween, and external electrodes 7a and 7b are formed on the outer circumferences of both ends of the ceramic body 5. Here, the distance L between the internal electrodes and the shortest distance L0 of the external electrodes are formed so that L <L0, and the shortest distance L0 of the external electrodes and the longitudinal dimension W of the ceramic element body are substantially equal to each other. ..

【0011】 また図4及び図5は本考案の第2の実施例におけるチップサーミスタの断面及 びその製法を示すものである。3つの薄板状セラミック素体8a,8b,8cの うち、セラミック素体8a,8bの上面には内部電極9a,9bが相互に間隔を 保って対向するように形成されている。そして上記セラミック素体8a,8b, 8cが熱圧着されたのち、その両端外周に外部電極10a,10bが形成される 。4 and 5 show a cross section of a chip thermistor and a manufacturing method thereof in the second embodiment of the present invention. Of the three thin plate-shaped ceramic bodies 8a, 8b, 8c, internal electrodes 9a, 9b are formed on the upper surfaces of the ceramic bodies 8a, 8b so as to face each other with a space therebetween. Then, after the ceramic bodies 8a, 8b, 8c are thermocompression bonded, external electrodes 10a, 10b are formed on the outer circumferences of both ends thereof.

【0012】 第1の実施例の如く構成された積層型チップサーミスタの場合、図3に示すよ うに、その初期抵抗値は、電極間距離Lに比例して増減する。したがって、内部 電極形成時に、積層チップサーミスタの長手方向の内部電極寸法L3,L4を制 御することにより、電極間距離Lを可変設定することができ、そのため、チップ サーミスタ素子としての初期抵抗値を素材組成,形状を変えることなく、制御す ることが可能となる。In the case of the multilayer chip thermistor configured as in the first embodiment, as shown in FIG. 3, its initial resistance value increases or decreases in proportion to the interelectrode distance L. Therefore, when the internal electrodes are formed, the interelectrode distance L can be variably set by controlling the internal electrode dimensions L3 and L4 in the longitudinal direction of the multilayer chip thermistor. Therefore, the initial resistance value as the chip thermistor element can be set. It is possible to control without changing the material composition and shape.

【0013】 また、第2の実施例の如く構成すると、段差をもって内部電極が形成されるた め、電極間距離Lが、第1の実施例におけるチップサーミスタに比べ、若干長く なり、それにともない、初期抵抗値もわずかながら大きくなる。すなわち、チッ プサーミスタの積層数を変え、電極間に段差が設けられるように形成することに より、微妙に初期抵抗値を制御することができる。Further, in the case of the configuration of the second embodiment, since the internal electrodes are formed with steps, the inter-electrode distance L becomes slightly longer than that of the chip thermistor of the first embodiment, and accordingly, The initial resistance value also increases slightly. That is, the initial resistance value can be delicately controlled by changing the number of stacked chip thermistors so that the steps are formed between the electrodes.

【0014】 さらに積層構造に伴い、電極が内部電極で構成されるため、外部電極形成時の 素地溶解あるいは素体の脱落等を受けてもチップサーミスタ素子としての初期抵 抗値は何等、影響を受けることはない。Furthermore, since the electrodes are composed of internal electrodes due to the laminated structure, the initial resistance value of the chip thermistor element is unaffected even if the substrate is melted or the element body is dropped when the external electrodes are formed. I will not receive it.

【0015】 このように、チップサーミスタを積層構造とし、内部電極の寸法あるいは積層 数を変えることにより、チップサーミスタ素子としての初期抵抗値を制御するこ とが可能となる。As described above, the chip thermistor has a laminated structure, and the initial resistance value of the chip thermistor element can be controlled by changing the size or the number of laminated internal electrodes.

【0016】 尚、本考案は上記実施例に限定されず、その要旨を変更しない範囲内で種々に 変形実施できる。The present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention.

【0017】[0017]

【考案の効果】[Effect of the device]

以上詳述した本考案によれば、積層構造としたチップサーミスタの内部電極の 寸法あるいは積層数を変えることにより、チップサーミスタ素子としての初期抵 抗値を制御することが可能となり、さらに外部電極形成時の素地溶解あるいは脱 落等を受けてもチップサーミスタ素子としての初期抵抗値が何等、影響を受ける ことがないため、精度が高く、均一な初期抵抗値を有する積層型チップサーミス タを提供することができる。 According to the present invention described in detail above, it is possible to control the initial resistance value as a chip thermistor element by changing the size or the number of stacked internal electrodes of the chip thermistor having a laminated structure, and further forming the external electrode. The initial resistance value of the chip thermistor element is not affected by the dissolution or dropping of the base material at any given time.Therefore, a multilayer chip thermistor with high accuracy and uniform initial resistance value is provided. be able to.

【図面の簡単な説明】[Brief description of drawings]

【図1】本考案の積層型チップサーミスタの第1の実施
例を示す断面図
FIG. 1 is a sectional view showing a first embodiment of a multilayer chip thermistor of the present invention.

【図2】本考案の積層型チップサーミスタの第1の実施
例の製造方法を説明するための図
FIG. 2 is a view for explaining the manufacturing method of the first embodiment of the multilayer chip thermistor of the present invention.

【図3】本考案の積層型チップサーミスタの第1の実施
例の電極間距離と初期抵抗値の関係を示すグラフ
FIG. 3 is a graph showing the relationship between the interelectrode distance and the initial resistance value of the first embodiment of the multilayer chip thermistor of the present invention.

【図4】本考案の積層型チップサーミスタの第2の実施
例を示す断面図
FIG. 4 is a sectional view showing a second embodiment of the multilayer chip thermistor of the present invention.

【図5】本考案の積層型チップサーミスタの第2の実施
例の製造方法を説明するための図
FIG. 5 is a view for explaining the manufacturing method of the second embodiment of the multilayer chip thermistor of the present invention.

【図6】第1の従来例を説明するための断面図FIG. 6 is a sectional view for explaining a first conventional example.

【図7】第2の従来例を説明するための断面図FIG. 7 is a sectional view for explaining a second conventional example.

【符号の説明】[Explanation of symbols]

5a,5b セラミック素体 6a,6b 内部電極 7a,7b 外部電極 5a, 5b Ceramic body 6a, 6b Internal electrode 7a, 7b External electrode

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】 セラミック積層体の両端に外部電極が形
成され、該セラミック積層体の一積層面に、一方の外部
電極に接続するように形成された内部電極と、他方の外
部電極に接続する一積層面に形成された内部電極の各先
端部が、間隔を保って、重畳することなく、対向するこ
とを特徴とする積層型チップサーミスタ。
1. External electrodes are formed on both ends of a ceramic laminate, and an internal electrode formed so as to be connected to one external electrode and one external electrode are formed on one laminated surface of the ceramic laminate. A multilayer chip thermistor, characterized in that the respective tip portions of the internal electrodes formed on one laminated surface are opposed to each other with a space therebetween, without overlapping.
JP6050491U 1991-07-31 1991-07-31 Stacked Chip Thermistor Pending JPH0515405U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6050491U JPH0515405U (en) 1991-07-31 1991-07-31 Stacked Chip Thermistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6050491U JPH0515405U (en) 1991-07-31 1991-07-31 Stacked Chip Thermistor

Publications (1)

Publication Number Publication Date
JPH0515405U true JPH0515405U (en) 1993-02-26

Family

ID=13144209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6050491U Pending JPH0515405U (en) 1991-07-31 1991-07-31 Stacked Chip Thermistor

Country Status (1)

Country Link
JP (1) JPH0515405U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6466903A (en) * 1987-09-07 1989-03-13 Murata Manufacturing Co Semiconductor ceramic having positive resistance temperature characteristic
JPH04283902A (en) * 1991-03-12 1992-10-08 Murata Mfg Co Ltd Ntc thermistor element

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6466903A (en) * 1987-09-07 1989-03-13 Murata Manufacturing Co Semiconductor ceramic having positive resistance temperature characteristic
JPH04283902A (en) * 1991-03-12 1992-10-08 Murata Mfg Co Ltd Ntc thermistor element

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