JPH05153102A - Clock disconnection detecting circuit - Google Patents

Abstract

PURPOSE:To simplify an integration, to attain a miniaturization, and to decrease a secular change by forming a delay circuit, logic circuit, and three state buffer by a digital circuit. CONSTITUTION:A clock 101 is delayed by a delay circuit 102, and the output of an exclusive logical sum circuit 104 is turned to '1' when the logical level of the clock 101 is different from that of a delay clock 103. When the clock 101 is erased, the output of the circuit 104 is turned to '0'. When '1' is inputted to a three state buffer 108, and a control terminal 106 is '0', an output terminal 109 is turned into a high impedance state. As for the output state of the buffer 108, '1' and the high impedance state are alternately repeated when the clock is normal, and it is turned into the high impedance state when the clock is erased. Therefore, the disconnected state of the clock 101 can be detected by monitoring the voltage of the output terminal 109.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock loss detection circuit used in a digital communication device or the like for detecting loss of a clock.

[0002]

2. Description of the Related Art In a digital communication device or the like, each part of the device is constantly monitored in order to identify a failure location when a failure occurs and switch to a standby system. In particular, the clock is essential in digital devices,
Detection of the clock loss condition is important. FIG. 3 is a diagram showing a conventionally known clock loss detection circuit.

In FIG. 3, reference numeral 302 is a DC blocking circuit to which the clock 301 is input. Reference numeral 303 is a peak detection circuit, 304 is a reference power generation circuit, and 305 is a comparator to which the outputs of the peak detection circuit 303 and the reference power generation circuit 304 are input.

If the clock disappears for some reason,
It is uncertain whether the level will be "0" or "1". Therefore, the DC blocking circuit 302 passes only the AC component of the clock, the peak detection circuit 303 detects the amplitude of the clock, and outputs a voltage proportional to the amplitude. The comparator 305 compares the output of the peak detector 303 and the output of the reference voltage generation circuit 304, and when the amplitude of the clock is below the reference, outputs a clock loss detection signal to the output terminal 306.
The clock is judged to be "disconnected".

However, in the above-mentioned conventional example, since the peak detection circuit 303 is an analog circuit, it is difficult to integrate it with other digital circuits, and there is a drawback that the device becomes large. Further, since the characteristics of the respective elements forming the peak detection circuit 303 and the reference voltage generation circuit 304 have variations, it is necessary to adjust them.
In addition, there is a problem that it is not stable against aging.

[0006]

The conventional clock loss detection circuit is not suitable for integration because it uses an analog circuit. In addition, since the characteristics of the elements forming each circuit vary, adjustment is necessary. In addition, there is a problem that it is not stable against aging.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a stable clock loss detection circuit which can be easily miniaturized, does not require an adjustment process, and has little secular change.

[0008]

In order to solve the above-mentioned problems, the present invention provides a delay circuit for delaying a clock and a logic for performing an exclusive OR operation of the clock and the delay clock output from the delay circuit. It is composed of an arithmetic circuit and a three-state buffer whose output is controlled by a signal output from the logical operation circuit, to which a signal of a constant logical level is input.

[0009]

The clock loss detection circuit having the above structure is a digital circuit including the delay circuit, the logic circuit and the three-state buffer. Since the circuits can be easily integrated, the circuit can be miniaturized and the elements can be integrated. No adjustment process is required, and the change over time will be extremely small.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of the clock loss detection circuit of the present invention. In FIG. 1, 101 is a clock, which is input to the delay circuit 102 from the outside. Delay circuit 10
2 delays the input clock by a predetermined time and outputs it. 1
Reference numeral 04 is an exclusive OR circuit, which is a clock 101 and a delay circuit 1.
The clock 103 delayed by 02 is input, and the exclusive OR operation of both is performed. Reference numeral 108 is a three-state buffer. The three-state buffer 108 has an input terminal 107, an output terminal 109, and a control terminal 106 to which a control signal for controlling the output state of the signal input from the input terminal 107 and output from the output terminal 109 is input.

Regarding the clock loss detection circuit having the above configuration,
The operation will be described with reference to FIG. FIG. 2 is a diagram showing signal waveforms at various parts of the circuit of FIG. 201 is clock 10
The waveform is 1. It is assumed that the clock 101 disappears from the middle (clock disconnection state) and becomes the “0” level. 202 is the waveform of the clock 103 delayed by the delay circuit 102.

Reference numeral 203 denotes an output waveform of the exclusive OR circuit 104, which is a clock 20 which is an input to the exclusive OR circuit 104.
"1" and the delayed clock 202 have different logic levels
1 ”level. As you can see the waveform of 203,
In the normal portion of the clock 201, "1" and "0" are alternately repeated, but when the clock 201 disappears, the output 105 of the exclusive OR circuit 104 becomes the "0" level. This is the same even when the disappearance of the clock 101 is at the "1" level.

The "1" level is input to the input terminal 107 of the three-state buffer 108, and the control terminal 106 becomes "1".
When the output terminal 109 is in a high impedance state when it is 0 ″, the output state of the three-state buffer 108 controlled by the output waveform of the exclusive-OR circuit 104 like 203 becomes like 204. That is, the three-state buffer As for the output state of 108, when the clock is normal, the "1" level and the high impedance state shown by Z in Fig. 2 are repeated alternately, but when the clock disappears, it becomes the high impedance state. This is the actual waveform.

Ideally, the logic level before that is maintained in the high impedance state portion, but since there is actually a leakage current, the voltage gradually decreases in the high impedance state portion. There is little voltage drop in the high impedance state where the clock 201 is normal "
It does not reach 0 "level, but if the clock disappears,"
Therefore, the disconnection state of the clock 101 can be detected by monitoring the voltage of the output terminal 109.

Since the clock loss detection circuit described above is composed of a digital circuit, it can be easily integrated. Therefore, if the gate array is integrated with other digital circuits, the size of the circuit can be greatly reduced. As a result, it is possible to obtain a stable operation that does not change over time without the need for an element adjustment process.

In the above embodiment, the time constant of the voltage drop at the output terminal 109 was not controlled, but it goes without saying that the time constant can be controlled by connecting an appropriate integrator. .

[0017]

As described above, according to the present invention, each circuit is composed of a digital circuit, and since it is easy to integrate with other digital circuits, downsizing can be realized and an adjustment process is unnecessary. It is possible to provide an extremely stable clock loss detection circuit that does not change over time.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a clock loss detection circuit according to the present invention.

FIG. 2 is a diagram showing waveforms for explaining the principle of the present invention.

FIG. 3 is a diagram showing a conventional clock loss detection circuit.

[Explanation of symbols]

Reference numeral 101 ... Clock 102 ... Delay circuit 103 ... Delay clock 104 ... Exclusive OR circuit 105 ... Exclusive OR circuit output 106 ... Control terminal 107 ... Input terminal 108 ... Three-state buffer 109 ... Output terminal 201 ... Clock 202 ... Delay clock 203 ... Exclusive-OR output 204 ... Three-state buffer output state 205 ... Three-state buffer output waveform 301 ... Clock 302 ... DC element circuit 303 ... Peak detection circuit 304 ... Reference voltage generation circuit 305 ... Comparator 306 ... Output terminal

Claims (1)

[Claims] 1. A delay circuit for delaying a clock, a logical operation circuit for performing an exclusive OR operation of the clock and the delayed clock delayed by the delay circuit, and a signal of a constant logical level is inputted to the logical circuit. A clock loss detection circuit comprising a three-state buffer whose output state is controlled by a signal output from an arithmetic circuit.