JPH05153077A - Circuit for transmitting digital signal - Google Patents

Abstract

PURPOSE:To simplify a transmitting circuit by unnecessitating a circuit for individually transmitting a synchronizing signal in a digital signal transmitting circuit where the transmission of the synchronizing signal is needed. CONSTITUTION:The digital signal transmitting circuit is provided with delay means (a shift register 3 and a data selector 4) for executing the bit delay of a digital signal, a means (a frame multiplex circuit 6) for taking the frame synchronization of the digital signal and a timing control means (a timing comparator 7) for comparing the timing of the frame synchronization in a transmission line with the synchronization timing of the digital signal so as to decide the delay amount of the delay means and permits the synchronization timing of the digital signal to coincide with the frame synchronization of the transmission line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transmission circuit for imparting frame synchronization to a digital signal, and more particularly to a transmission circuit for a digital signal which does not include a synchronization signal in the digital signal.

[0002]

2. Description of the Related Art In a conventional transmission circuit, a digital signal and its synchronizing signal are individually transmitted. As shown in FIG. 3, the digital signal input to the digital signal input terminal 11 and the sync signal input to the sync signal input terminal 12 are transmitted through the transmission lines in the buffer memories 13 and 14 and the frame multiplexing circuits 15 and 16, respectively. The frame was synchronized and output to the digital signal output terminal 17 and the synchronization signal output terminal 18 and sent to the transmission path.

[0003]

Such a conventional transmission circuit requires a buffer memory 14 and a frame multiplexing circuit 16 for transmitting a synchronizing signal in addition to the original transmission of a digital signal, and a transmission line. However, there is a problem in that it becomes double or the band is widened. An object of the present invention is to provide a digital signal transmission circuit capable of frame synchronization with one circuit configuration and one transmission path.

[0004]

A transmission circuit according to the present invention comprises a delay means for delaying a bit of a digital signal, a means for synchronizing a frame of a digital signal, a timing of frame synchronization in a transmission path and a synchronization timing of a digital signal. And timing control means for determining the delay amount of the delay means so that

[0005]

The timing control means controls the delay amount of the delay means so that the multiplexed digital signal is located at a specific bit in the frame according to the synchronizing signal.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.
In the figure, a shift register 3 and a data selector 4 are connected to a digital signal input terminal 1, and these constitute a bit delay circuit. The data selector 4 is controlled by a timing comparator 7 which compares the timing with the sync signal input to the sync signal input terminal 2. The output of the data selector 4 is output to the digital signal output terminal 8 through the buffer memory 5 and the frame multiplexing circuit 6.

In this transmission circuit, a digital signal input terminal 1 receives a signal train of digital signals as shown in FIG. 2 (a), and a synchronization signal input terminal 2 as shown in FIG. 2 (b). A synchronization signal shall be input. Here, in the signal sequence of the digital signal, A is the first bit and the following B,
C, D, E, F, G, H and 8 bits are transmitted in a cycle. Then, this digital signal is transferred to the shift register 3
Then, the bit delay amount is changed by the selector 4, and the frame delay circuit 5 outputs the output signal from the output terminal 8 through the buffer memory 5 in the frame multiplexing circuit 6 for frame synchronization.

With respect to the delay amount, the timing comparator 7 compares and calculates the timing of the input synchronizing signal, the delay amount of the digital signal input to the buffer memory 5, and the frame timing of the frame multiplexing circuit 6, It is determined so that the timing of the synchronization signal and the timing of the frame match. As a result, the digital signal becomes
As shown in (c), it is always inserted in a fixed position in the frame according to the sync signal. In this example, A, which is the first bit of the 8-bit period, is always inserted after the frame bit (FRM). On the receiving end side, if the signal sequence is received and the frame is synchronized, the synchronizing signal of the digital signal is naturally extracted. Therefore, a buffer memory, a frame multiplexing circuit, and a transmission line for individually transmitting the synchronization signal are unnecessary.

[0009]

As described above, according to the present invention, the delay means for delaying the bit of the digital signal and the timing control means for controlling the delay amount are provided, so that the frame bit originally possessed is used for the digital signal. The information of the synchronizing signal can be transmitted, and it is not necessary to individually transmit the synchronizing signal, and the circuit and the transmission path can be simplified.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an embodiment of a transmission circuit of the present invention.

2 is a signal diagram of a digital signal and a synchronization signal in the transmission circuit of FIG.

FIG. 3 is a block diagram of a conventional transmission circuit.

[Explanation of symbols]

 1 Digital signal input terminal 2 Sync signal input terminal 3 Shift register 4 Data selector 5 Buffer memory 6 Frame multiplexing circuit 7 Timing comparator

Claims (1)

[Claims] 1. A digital signal transmission circuit for transmitting a digital signal and its synchronization timing, delay means for bit-delaying the digital signal, means for establishing frame synchronization of the digital signal, and timing of frame synchronization in a transmission path. And a timing control unit that determines the delay amount of the delay unit so that the synchronization timing of the digital signal matches.