JPH05152440A - Automatic layout device for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To consider a delay value of a feedthrough terminal previously formed in a cell at the time of a back annotation in an automatic layout device for a semiconductor integrated circuit. CONSTITUTION:An automatic layout device for a semiconductor integrated circuit comprises a designing data base 1A, a library forming function 1B for converting individual cell information into a library for an automatic layout, an automatic layout.wiring function 1C for automatically laying out based on circuit connecting information written in the base 1A and the library, and a wiring length calculating function 1D for outputting the lengths of the wirings from the base 1A in which automatic layout.wiring results are written and delivering them to a delay simulator. The wiring length of a feedthrough terminal previously formed in a cell is calculated by the function 1B, added at the time of calculating the length, and the result is output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic layout apparatus for semiconductor integrated circuits, and more particularly to improvement of a wiring length calculation method in back annotation for feeding back automatic layout / wiring results to a delay simulator.

[0002]

2. Description of the Related Art In a conventional automatic layout device for a semiconductor integrated circuit, as shown in FIG. 2, there are three methods (hereinafter referred to as feedthroughs) in which wiring passes over cells. As shown in FIG. 2 (a), a method of using the input / output pins inside the cell, a method of automatically recognizing a wiring passage area on the ceni as shown in FIG. 2 (b) and wiring, Two
As shown in (c), a wiring to be passed (hereinafter referred to as a feedthrough terminal) is prepared in advance on the cell. Although the methods of FIGS. 2B and 2C are similar,
The wiring in FIG. 2B is a straight line, whereas the wiring in FIG. 2C can be formed in a free shape, so that the cell area can be reduced and the feedthrough can be used efficiently. ..

The conventional automatic layout device for a semiconductor integrated circuit has a function of feeding back the automatic placement / wiring results to the delay simulator (hereinafter referred to as back annotation). At that time, the wiring shown in FIG. The length is incorporated as delay information inside the cell, and the feedthrough according to the method of FIG. 2B is an automatic wiring. Therefore, the wiring length can be calculated similarly to the wiring outside the cell. However, since the feedthrough terminal formed on the cell by the method of FIG. 2C has nothing to do with the logical information of the cell,
It is not incorporated into the delay information inside the cell as in (a),
Further, since the wiring is not automatically performed, the wiring length cannot be calculated as shown in FIG. 2B.

FIG. 3 is a flowchart showing an example of a conventional automatic layout apparatus and a wiring length calculation method for back annotation. In the conventional automatic layout apparatus, first, cell information is input to convert the input / output pin information and cell outline necessary for automatic layout into a library (step 31). At this point, the wire length of the feedthrough terminal is not converted to the library. Next, automatic placement / wiring is performed based on the circuit connection information and the library information (step 32). Then, the wiring length is calculated from the result of the automatic placement / wiring, but at that time, the length of the feedthrough terminal is not included (step 33).

[0005]

However, the above-described conventional automatic layout device for a semiconductor integrated circuit does not have the function of calculating the wiring length of the feed-through terminal which is built in the cell in advance, and therefore the automatic layout is performed. When calculating the length of each wiring from the result, the wiring length of the feedthrough terminal is omitted, and the delay value cannot be taken into consideration during back annotation.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an automatic layout device for a semiconductor integrated circuit capable of considering the delay value of the feedthrough terminal during back annotation.

[0007]

An automatic layout apparatus for a semiconductor integrated circuit according to the present invention includes a design database, a library creating means for converting each cell information into a library for automatic layout, and a writing means written in the design database. Automatic layout / wiring means for automatically laying out based on the circuit connection information and library stored, and wiring to be passed to the delay simulator by extracting the length of each wiring from the design database in which the automatic layout / wiring results are written A wiring length including a length extraction means, the library generation means calculates the wiring length of the feed-through terminal preliminarily formed in the cell, and adds it when calculating the wiring length to output the wiring length calculation result. It is characterized by having a calculating means.

[0008]

In the semiconductor integrated circuit automatic layout apparatus of the present invention, the wiring length of the feed-through terminal which is built in the cell in advance is calculated at the time of creating the library for automatic layout, and the calculated value is wired. The delay value of the feedthrough terminal can be taken into consideration at the time of back annotation by the wiring length extraction means added and output at the time of length calculation.

[0009]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of an automatic layout apparatus for semiconductor integrated circuits according to the first embodiment of the present invention. The semiconductor integrated circuit automatic layout apparatus shown in FIG. 1 includes a design database 1A, a library creation function 1B for converting individual cell information into a library for automatic layout, and circuit connection information and a library written in the design database. It is equipped with an automatic placement / wiring function 1C that performs automatic layout based on the above, and a wiring length calculation function 1D that extracts the length of each wiring from the design database in which the automatic placement / wiring results are written and transfers it to the delay simulator. ..

Next, the first aspect of the present invention configured as described above
The operation of the automatic layout apparatus for a semiconductor integrated circuit according to the embodiment will be described. FIG. 4 is a flow chart showing a flow of operations of the automatic layout apparatus for semiconductor integrated circuits according to the first embodiment of the present invention. First, the library creation function 1B reads the cell information from the database 1A, recognizes the information of the input / output pins and feedthrough terminals and the cell outline necessary for the automatic layout, and recognizes the database 1A.
(Step 41), at that time, the wiring length of the feedthrough terminal is calculated (Step 42), and the result is used as the property of the feedthrough terminal in the database 1.
Write in Α. The automatic placement / wiring function 1C performs automatic placement / wiring processing based on the circuit connection information and library information of the design database 1A (step 43). In this way, the wiring length calculation function 1D calculates the length of each wiring after designing from the design database 1A for which automatic placement / wiring is completed. At that time, regarding the wiring using the feedthrough terminal, as a property. The wiring length written in the library is added and output to the design database 1A (step 44).

FIG. 5 is a block diagram showing the configuration of an automatic layout apparatus for semiconductor integrated circuits according to the second embodiment of the present invention. The semiconductor integrated circuit automatic layout apparatus shown in FIG. 5 includes a design database 5A, a library creation function 5B for converting individual cell information into a library for automatic layout, and circuit connection information and a library written in the design database. It is equipped with an automatic placement / wiring function 5C that performs automatic layout based on the above, and a wiring length calculation function 5D that extracts the length of each wiring from the design database 5A in which the automatic placement / wiring results are written and passes it to the delay simulator. In addition, the interface file 5E is provided as one of the output destinations of the wiring length calculation function 5D.

The operation flow of the automatic layout device for a semiconductor integrated circuit shown in FIG. 5 is such that library creation and automatic placement and routing are performed as in the first embodiment of the present invention. At the same time as outputting to the design database 5A, it is also output to the interface file 5E. The format of this interface file 5E is a standard text format suitable for delay simulators.

In the first embodiment of the present invention, back annotation is performed in one integrated system, whereas in the second embodiment of the present invention, the design database 5A can be directly read and written to a delay simulator. Back annotation can be performed.

[0015]

As described above, according to the automatic layout apparatus for a semiconductor integrated circuit of the present invention, the wiring length of the feed-through terminal prefabricated in the cell is calculated at the time of creating the library, and By adding and outputting when calculating the wiring length, the delay value of the feedthrough terminal can be taken into consideration during back annotation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an automatic layout device for a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a feedthrough of a semiconductor integrated circuit according to a conventional technique.

FIG. 3 is a flowchart illustrating a conventional automatic layout device for semiconductor integrated circuits.

FIG. 4 is a flowchart illustrating an automatic layout device for a semiconductor integrated circuit according to the first exemplary embodiment of the present invention shown in FIG.

FIG. 5 is a block diagram showing an automatic layout device for a semiconductor integrated circuit according to a second embodiment of the present invention.

[Explanation of symbols]

 1A; Design database 1B; Library creation function 1C; Automatic placement / wiring function 1D; Wiring length calculation function 2A, 2B, 2C; Feedthrough

Claims (1)

[Claims] 1. A design database, library creating means for converting each cell information into a library for automatic layout, and automatic layout for automatically laying out based on the circuit connection information and the library written in the design database. -Feed-through built in the cell in advance, including wiring means and wiring length extraction means for extracting the length of each wiring from the design database in which automatic placement / wiring results are written and passing it to the delay simulator. An automatic layout device for a semiconductor integrated circuit, comprising: wiring length calculation means for calculating the wiring length of terminals by the library creating means and adding the calculated wiring length calculation result to the wiring length calculation result.