JPH04299843A - Mask layout method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To efficiently design a new mask layout on the basis of a mask layout designed in the past by a manual operation. CONSTITUTION:Standard cell information (c) is extracted from an old graphic pattern (f) designed in the past by a manual operation. A netlist (b) is formed from the old graphic pattern (f) by utilizing an existing netlist verification device 30. The netlist (b) which has been format-converted and the standard cell information (c) are given to an existing automatic arrangement and interconnection device 20; in addition, a new design rule (d) is set. When the new design rule (d) is applied to the old graphic pattern (f), a new graphic pattern (g) can be obtained.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask layout method for semiconductor integrated circuits, and more particularly to a mask layout method using an automatic placement and routing device and a netlist verification device.

0002

[Prior Art] Traditionally, mask layout design for semiconductor integrated circuits has been carried out by manually creating two-dimensional layout patterns corresponding to devices such as transistors, capacitors, and resistive elements based on circuit design drawings. Ta. However, in recent years, with the development of computer technology, devices for automating such mask layout design have been developed. For example, if you use an automatic placement and routing system, you can prepare netlists and standard cell information as data, add information about desired design rules to this data, and automatically create graphic patterns related to the mask layout of semiconductor integrated circuits. can be created. Additionally, a device has been developed to verify whether the graphic pattern created in this way is correct. For example, LVS (Layou
By using a netlist verification device called t vs Schematic, it is possible to automatically verify whether an automatically created graphic pattern is compatible with the original netlist. That is,
This netlist verification device has a function of converting an automatically created graphic pattern into a netlist, and a function of comparing and verifying the converted netlist with the original netlist.

0003

[Problem to be Solved by the Invention] The mask layout design system using the above-mentioned automatic placement and routing device and netlist verification device provides an extremely rational design when designing a mask layout for a new semiconductor integrated circuit. In addition, since various information used in the design can be stored as data, it is easy to make modifications to the mask layout designed using this system. However, this system cannot be applied to mask layouts that were manually designed in the past because no information has been accumulated.

Semiconductor integrated circuits are progressing year by year, and new mask layouts are often designed by applying new design rules to mask layouts designed in the past. However, the above-mentioned automated system cannot be applied to mask layouts that were designed manually in the past, so corrections to such manually designed mask layouts are still done manually. It is.

SUMMARY OF THE INVENTION An object of the present invention is to provide a mask layout method for semiconductor integrated circuits that can efficiently create a new mask layout based on a mask layout that has been manually designed in the past.

[0006]

[Means for Solving the Problems] The present invention provides an automatic placement and routing device that generates a graphic pattern related to a mask layout of a semiconductor integrated circuit by providing three pieces of information: a netlist, standard cell information, and design rules; Netlist verification that converts the generated graphic pattern into a netlist and compares this converted netlist with the netlist given to the automatic placement and routing device to verify that the generated graphic pattern is correct. The device performs mask layout of a semiconductor integrated circuit using a device, and includes a first step of extracting standard cell information from an old graphic pattern related to the mask layout, feeding this old graphic pattern to a netlist verification device, The second step is to convert this old figure pattern into an upper layer netlist that does not include the inside of the standard cell, and the second step is to convert this upper layer netlist into a format suitable for giving to automatic placement and routing equipment. 3, the standard cell information extracted in the first stage, and the netlist converted in the third stage,
A fourth step of generating a new figure pattern by giving the new design rule to the automatic placement and routing device, and applying the new design rule to the old figure pattern to obtain the new figure pattern. This is what I did.

[0007]

[Operation] In a manually designed mask layout, the only remaining design assets are the drawings in which the graphic patterns are drawn. A feature of the method according to the present invention is that the graphic pattern left in the form of a drawing is converted into a netlist by using an existing netlist verification device. The netlist converted in this way is in the form of digital data that can be handled by a computer. On the other hand, standard cell information is extracted based on the graphic pattern left in the form of this drawing. In this way, if the netlist and standard cell information are prepared, it becomes possible to automatically design a mask layout based on new design rules using an existing automatic placement and routing device.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below based on illustrative embodiments. The gist of the present invention is that a manually designed mask layout is corrected using an existing automatic placement and routing device and a netlist verification device. First, the procedure of a conventional mask layout automatic design method using an automatic placement and routing device and a netlist verification device will be briefly explained based on FIG.

The mask layout automatic design system shown in FIG. 1 uses devices such as a netlist creation device 10, an automatic placement and routing device 20, and a netlist verification device 30. The netlist creation device 10 is a device that has a function of creating a netlist b based on a circuit diagram a created by a designer. That is, the standard cells and their terminals in the circuit diagram a are recognized, and their connection relationships are output in the form of data called a netlist b. On the other hand, standard cell information c indicating the cell size and terminal position regarding each standard cell in circuit diagram a
is prepared as data. Further, a design rule d having numerical information necessary for designing a semiconductor integrated circuit, such as the width of a wiring layer and the thickness of an insulating film, is prepared as data. The automatic placement and routing device 20 generates a graphic pattern e regarding the mask layout of a semiconductor integrated circuit based on the netlist b, standard cell information c, and design rule d.
This is a device that has the function of outputting. If the graphic pattern e is output in paper form, a drawing in which the desired graphic pattern is drawn will be created.

[0010] Generally, the netlist verification device 30
This is a device called VS (Layout vs Schematic) and is a device for verifying whether the graphic pattern e automatically created as described above is correct. Functionally, this device can be considered to be a device that includes three components: a netlist conversion section 31, a format conversion section 32, and a netlist comparison section 33. The netlist conversion unit 31 has a function of converting the graphic pattern e created by the automatic placement and routing device 20 into a netlist. That is, pattern recognition is performed on a graphic pattern e given in the form of a drawing, and the connection relationship between each terminal is recognized.
It creates a netlist. On the other hand, the format conversion unit 32 determines that the format of the netlist b created by the netlist creation device 10 is
It has a function to perform format conversion to match the format of the output netlist of No. 1. In this way, the netlist converted by the netlist conversion section 31 and the netlist converted by the format conversion section 32 are compared in the netlist comparison section 33. Since both formats are unified, it is possible to compare whether or not the two netlists match. In this way, it can be verified whether the graphic pattern e created by the automatic placement and routing device 20 is compatible with the original netlist b.

The conventional automatic mask layout design system has been briefly described above. A netlist creation device 10, an automatic placement and routing device 20, used in this system,
Since the netlist verification device 30 is a well-known device, a detailed explanation of its internal configuration will be omitted. For details regarding such a mask layout automatic design system, please refer to various known documents.

Now, with the above-mentioned automatic design system, it is very difficult to design a new mask layout for a semiconductor integrated circuit or to modify a mask layout that was automatically designed using this system in the past. It can be done efficiently. However, when designing a new mask layout by applying new design rules to a mask layout that was created manually in the past, the above-mentioned system cannot handle this. The present invention makes it possible to perform efficient mask layout design using the above-described system even in such a case. This method will be explained below with reference to FIG.

In FIG. 2, the automatic placement and routing device 20 and netlist verification device 30 used in the conventional system shown in FIG. 1 can be used as they are. Here, it is assumed that a drawing in which a mask layout was manually designed in the past is prepared as the old figure pattern f, and a new design rule d is applied to this,
This method will be explained using an example of creating a new graphic pattern g. A conceptual diagram of the prepared old figure pattern f is shown in FIG. The example shown here is six standard cells C
This is a graphic pattern of a mask layout composed of standard cells C1 to C6, and the graphic pattern inside each standard cell C1 to C6 is omitted in the figure. Furthermore, although the wiring between each cell is shown as a single line in the figure, in the actual graphic pattern, these wirings form a wiring layer with a width. Here, the codes C1 to C6 given to each cell are names unique to each cell, called instance names. On the other hand, the cell names "Cell L", "Cell M", and "Cell N" written in each cell are names indicating the type of cell, and standard cells with the same cell name have exactly the same graphic pattern. X1, X2, X3 in each cell
, X4 are terminal names of terminals provided for each cell for external wiring, and blocks P1, P2, and P3 are terminal names of external terminals of this semiconductor integrated circuit as a whole. Also, N1 to N attached on the wiring path between each terminal
10 is the node name given to these wiring paths.

Once such an old figure pattern f is prepared, standard cell information c is extracted from this old figure pattern f by the standard cell information extracting device 40. The standard cell information c is information indicating the size and terminal position of each standard cell, and is data as shown in FIG. 4, for example. The standard cell information shown in FIG. 4 is text data written in five lines, and indicates information about "cell L." That is, the first line shows the cell name, and the second line shows the coordinate values (x0, y0) of two vertices at diagonal positions in the outline rectangle of this cell (
x1, y1), and the third row is the input terminal X of this cell.
2, the fourth line shows the coordinates (x3, y3) of the input terminal X3 of this cell, and the fifth line shows the coordinates (x4, y3) of the output terminal X4 of this cell. , y4). In the case of the graphic pattern shown in FIG. 3, information regarding "cell M" and "cell N" is also extracted. The standard cell information extraction device 40 may be any device that can extract information regarding such coordinates.
It doesn't matter what you use. For example, if a coordinate input device such as a digitizer is used, the operator can
All you have to do is spread the drawing of the old figure pattern f on the tablet constituting the digitizer, and specify the apex position of the outline rectangle and the terminal position of the necessary cell using a pen or mouse for inputting coordinates. Of course, actual measurements may be made using primitive methods such as rulers and scales.

Next, the old graphic pattern f is converted into a netlist b using the netlist verification device 30. As mentioned above, the netlist verification device 30 is originally a device for verifying a netlist, but since it is equipped with the netlist conversion section 31 that has the function of converting a graphic pattern into a netlist, It is possible to have the netlist b created based on the old graphic pattern f. However, here, instead of creating a netlist for the entire old graphic pattern f, a higher-level netlist that does not include the inside of the standard cell is created. For example, regarding the graphic pattern shown in Figure 3,
An upper layer netlist as shown in FIG. 5 is created. This netlist is text data written over multiple lines. The first line shows that this netlist is a mask layout of a semiconductor integrated circuit named "TOP", and the second line shows that this netlist has three external terminals P1, P2, and P3. It shows that it is equipped with Furthermore, in the third and fourth rows, among the three external terminals, P1 and P2 are input terminals, and P3 is the input terminal.
indicates that it is an output terminal. Subsequently, the fifth to seventh lines contain two "cells L" given instance names C3 and C6, two "cells M" given instance names C2 and C5, and instance names C1 and C4. Two "cells N" are defined. The 8th line indicates that information regarding each node follows, and the node information is described from the 9th line onwards. For example, in the ninth line, node N1 has external terminal P1.
It is defined that and terminal 1 of cell C5 are connected. The 19th line and the 20th line indicate the end of this netlist. In this way, the netlist shown in FIG. 5 is an upper layer netlist that does not include connection relationships within each standard cell.

The netlist b thus obtained is provided to the automatic placement and routing device 20. However, since the format of the netlist that can be accepted by the automatic placement and routing device 20 and the format of the netlist created by the netlist verification device 30 are generally different, the format of the netlist b is changed by the format inverse conversion unit 50. It is converted into a format that can be accepted by the automatic placement and routing device 20. The conversion process performed by the format inverse conversion unit 50 is the inverse conversion of the conversion process performed by the format conversion unit 32. In this way, the automatic placement and routing device 20 stores the netlist b whose format has been converted.
, the standard cell information c extracted from the old figure pattern f, and the newly set design rule d are given, and a new figure pattern g is created.

As described above, according to the method of the present invention, it is possible to obtain a new graphic pattern g by applying the new design rule d to the manually created old graphic pattern f. Moreover, this method can be implemented using the existing automatic placement and routing device 20 and netlist verification device 30, and the only new components that need to be prepared are the standard cell information extraction device 40 and the format inversion section 50. It is.

[0018]

[Effects of the Invention] As described above, according to the mask layout method for a semiconductor integrated circuit according to the present invention, a graphic pattern is converted into a netlist using an existing netlist verification device, and a graphic pattern is converted into a netlist using an existing automatic placement and routing device. Since mask layout design is performed based on new design rules, it becomes possible to efficiently create a new mask layout based on a mask layout that was manually designed in the past.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system configuration for implementing a conventional mask layout method.

FIG. 2 is a block diagram showing a system configuration for implementing the mask layout method of the present invention.

FIG. 3 is a conceptual diagram showing an example of a graphic pattern.

FIG. 4 is a diagram showing an example of data configuring standard cell information.

FIG. 5 is a diagram showing an example of data configuring a netlist.

[Explanation of symbols]

10...netlist creation device 20...automatic placement and routing device 30...netlist verification device 31...netlist conversion section 32...format conversion section 33...netlist comparison section 40...standard cell information extraction device 50...format inverse conversion section a... Circuit diagram b...Netlist c...Standard cell information d...Design rule e...Graphic pattern f...Old graphic pattern g...New graphic pattern C1-C6...Standard cell instance name N1-
N10...Node name of wiring path P1-P3...External terminal name X1-X4...Inter-cell connection terminal name

Claims (1)

[Claims] 1. An automatic placement and routing device that generates a graphic pattern related to a mask layout of a semiconductor integrated circuit by providing three pieces of information: a netlist, standard cell information, and design rules, and a netlist that generates the generated graphic pattern. and a netlist verification device that verifies that the graphic pattern is correct by comparing the converted netlist with a netlist given to the automatic placement and routing device. The circuit mask layout method includes a first step of extracting standard cell information from an old graphic pattern related to the mask layout, providing the old graphic pattern to the netlist verification device, and converting the old graphic pattern into standard cell information. a second step of converting the upper layer netlist to an upper layer netlist that does not include internals; a third step of converting the upper layer netlist into a format suitable for providing to the automatic placement and routing device; a fourth step of generating a new graphic pattern by supplying the standard cell information extracted in the step, the netlist converted in the third step, and the new design rule to the automatic placement and routing device; A mask layout method for a semiconductor integrated circuit, characterized in that a new graphic pattern is obtained by applying a new design rule to an old graphic pattern.