JPH0515165A - Control method for three-phase three-wire neutral clamping inverter - Google Patents

Abstract

PURPOSE:To make an inverter controllable over the entire operating range regardless of the amplitude of PWM control input signal and to make it possible to feed a motor load with a sine wave current having suppressed ripple. CONSTITUTION:In the control method for neutral clamping inverter, when three- phase input signals eU, eV, eW for PWM control have a low amplitude Em, a DC bias voltage eb(DC) and/or an AC bias voltage eb(AC) is added to each of the input signals eU, eV, eW and when the amplitude Em is high, the bias voltage is brought to zero.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a neutral point clamp type inverter control method for pulse width modulation control (PWM control) for supplying electric power of variable voltage variable frequency to a three-phase three-wire type AC load.

[0002]

2. Description of the Related Art FIG. 10 (a) shows a main circuit configuration diagram of a conventional three-phase three-wire neutral point clamp type inverter. Here, only one phase (U phase) is shown. In the case of a three-phase output inverter, the V and W phases are similarly constructed.

Four self-extinguishing elements S ₁ ... connected in series
S ₄ and the freewheeling diodes D _{1 to} D ₄ connected in antiparallel to the self-extinguishing elements S _{1 to} S ₄ , respectively.
And two clamping diodes D ₅ and D ₆ in parallel with the self-extinguishing elements S ₂ and S ₃ and connected in series in the opposite polarity to each other. The voltage sources V _d1 and V _d2 are connected, and the load LOAD is connected to the output side thereof.

As the control circuit, as shown in FIG. 10B, comparators C _U , C ₁ and C ₂ , a current control compensation circuit G _u (S), a triangular wave generator TRG, a Schmitt circuit SH.
₁ and SH ₂ are prepared.

The output voltage V _U of this inverter changes as follows by turning on and off the _four elements S _{1 to} S ₄ . However, the total DC voltage is V _d ,
Let V _d1 = V _d2 = V _d / 2. That is, when S ₁ and S ₂ are on, V _U = + V _d / 2 When S ₂ and S ₃ are on, V _U = 0 When S ₃ and S ₄ are on, V _U = −V _d / It becomes 2. At this time, two devices must be turned on each. When three elements are turned on at the same time, the direct current power supply is short-circuited and the elements are destroyed by the overcurrent. For example, S
_{When the} ON signals are simultaneously input to _{1 to} S ₃ , the DC voltage V _d1 is short-circuited by the element S ₁ → S ₂ → S ₃ → diode D ₆ , and an excessive short-circuit current flows through the element, which destroys the element.

In order to prevent such a DC short circuit, the elements S ₁ and S ₃ are operated in reverse and the elements S ₂ and S ₄ are operated in reverse. That is, when S ₁ is ON turns off the S _3, when S ₃ is turned on and turns off the S _1. Similarly, when S ₂ is on turns off the S _4, when S ₄ is on and turns off the S _2.

The load current I _U is controlled as follows.

That is, the load current I _U detected by the current detector CT _U as shown in FIG.
It is input to the comparator C _U shown in (b) and compared with the command value I _U ^* . The deviation ε _U is amplified by the current control compensation circuit G _U (S), and the pulse width modulation control (PWM control) input signal e _i is amplified.
make. TRG outputs carrier waves X and Y of PWM control,
The comparators C ₁ and C ₂ compare with the input signal e _i ,
Through the Schmitt circuits SH ₁ and SH ₂ , the elements S _{1 to} S _1
4 gate signals g ₁ and g ₂ are generated.

When I _U ^* > I _U , the deviation ε _U becomes a positive value, and the value of the PWM control input signal e _i is increased. Neutral point clamped inverter generates a voltage V _U which is proportional to the input signal, increasing the load current I _U, I _U
= I _U ^* . Conversely, I _U ^* <I _U
Then, the deviation ε _U becomes a negative value, and the value of the PWM control input signal e _i is reduced. Therefore, the output voltage V _{U of the} inverter increases, which increases the load current I _U , again
It is controlled so that I _U = I _U ^* .

FIG. 11 is a time chart for explaining the pulse width modulation control operation of the conventional neutral point clamp type inverter.

In the figure, X and Y are carrier wave signals of PWM control, X (solid line) is a triangular wave varying between 0 and + E _max ,
Y (dashed line) is a triangular wave that varies between 0 and -E _max . Further, e _i is a PWM control input signal.

The input signal e _i is compared with the triangular waves X and Y,
The gate signals g ₁ and g ₂ of the elements S _{1 to} S ₄ are produced. That is, when e _i > X, g ₁ = 1 and S ₁ : on (S ₃ : off) e _i ≦ X, g ₁ = 0 and S ₁ : off (S ₃ : on) e _i <Y, g ₂ = 1 and S ₄ : ON (S ₂ : OFF). When e _i ≧ Y, g ₂ = 0 and S ₄ : OFF (S ₂ : ON).

As a result, the output voltage V _U becomes as shown at the bottom of the figure. As described above, in the neutral point clamp type inverter, as the output voltage V _U , three levels (+ V _d / 2,
0, the voltage of -V _d / 2) is obtained, and less voltage waveform of the harmonic component. In the case of a motor load, there are advantages that current pulsation is reduced and torque ripple is also reduced.

[0014]

However, the conventional control method of the neutral point clamp type inverter has the following problems.

FIG. 12 is a time chart for explaining the conventional PWM control method as in FIG.
It represents the operation when the input signal e _i is very small.

When the input signal e _i is small, the pulse width of the gate signals g ₁ and g ₂ becomes narrow. This width is the minimum on-time Δt of the self-extinguishing elements S _{1 to} S ₄ forming the inverter.
The problem occurs when it becomes narrower than.

That is, in a large capacity inverter, a GTO (gate turn-off thyristor) is used as a self-extinguishing element.
A snubber circuit is installed to suppress overvoltage at turn-off. In order to initialize (discharge) the voltage of the capacitor of this snubber circuit, when the GTO is turned on, the on state must be maintained for a certain time (minimum on time Δt: for example, about 100 microseconds).

In the case of FIG. 12, the input signal e _i becomes small and the period of the gate signal g ₁ = 1 that is, the period in which the element S ₁ is on (S ₃ is off) becomes shorter than the minimum on-time Δt. There is. Therefore, in order to secure the minimum on-time of the device, the gate signal g ₁ is corrected as g ₁ ′. Similarly, the gate signal g ₂ is also corrected like g ₂ ′, and the output voltage V _U has the lowest waveform. The average value V _U of the output voltage becomes a positive or negative constant value regardless of the value of the input signal e _i , as shown by the broken line.

That is, in the conventional neutral point clamp type inverter, when the level of the input signal e _i becomes low, the output voltage V _U becomes a constant value regardless of the value of the input signal e _i , and the load is reduced. It becomes impossible to control the current I _U. In particular, when the output frequency is low, this voltage error is integrated and the load current I _U is increased, and in the worst case, the element is destroyed.

The present invention has been made in view of the above problems, and enables PWM control in all areas regardless of the magnitude of the input signal of PWM control while ensuring the minimum on-time of the element. An object of the present invention is to provide a control method of a neutral point clamp type inverter that can supply a sinusoidal current with less ripple to a three-phase phase AC load.

[0021]

In order to achieve the above object, the method of the present invention is as follows. That is, invention corresponding to claim 1, when 3-phase input signals e _U the pulse width modulation control, e _V, the amplitude value E _m of e _W small direct current input signals e _U, e _V, e _W Bias voltage e _{b (DC)} , or either DC bias voltage e _{b (DC)} and AC bias voltage e _{b (AC)} is applied, and amplitude value E _m
Is set to 0, the bias voltage is set to zero.

In the invention corresponding to claim 2, of the three-phase input signals e _U , e _V , and e _W of the pulse width modulation control, the absolute value of the one-phase input signal becomes smaller than a certain reference level E _G. At that time, the input signal of the phase is fixed to zero or to a positive or negative constant value E _G , and during that period, the three-phase output current of the neutral point clamp type inverter is controlled by pulse width modulation with the other two phases. Is a method characterized by.

In the invention corresponding to claim 3, when the amplitude value E _m of the three-phase input signals e _U , e _V , and e _W of the pulse width modulation control is small, each of the input signals e _U , e _V , and e _W is changed. Pulse width modulation control by adding DC bias voltage eb _(DC) or bias voltage eb _(DC) + eb _(AC) which is the sum of DC and AC,
When the amplitude value E _m becomes large, the bias voltage is set to zero, and the absolute value of the one-phase input signal among the three-phase input signals e _U , e _V , and e _W is smaller than a certain reference level E _G. , The input signal of the phase is fixed to zero or a positive or negative constant value E _G , and during that period, the three-phase output current of the neutral point clamp type inverter is pulse width modulated controlled by the other two phases. This is a characteristic method.

[0024]

The present invention relates to a control method of a neutral point clamp type inverter for supplying electric power of a variable voltage variable frequency to a load of a three-phase three-wire type, and when the amplitude of the PWM control input signal is small, A bias voltage is applied to the input signal so that the gate pulse width is always longer than the minimum on-time of the device so that control cannot be lost. This bias voltage is basically a DC bias, but a slight AC bias voltage may be superimposed to improve the utilization factor of the inverter.

By applying the same bias voltage to the three-phase input signals, the potential at the neutral point of the load is biased. However, as the three-phase line voltage, the bias voltages cancel each other out, and the output current Can be continuously controlled.

When the amplitude value of the three-phase PWM control input signal becomes large, the bias voltage is set to zero and the normal P
Perform WM control. In this case, the instantaneous value of each phase input signal crosses the zero point and passes through the uncontrollable region. But,
Not all of the three-phase input signals cross the zero point at the same time, but if any one phase crosses the zero point, the other two
The phase input signal is sufficiently large and PWM control is possible. If the load current of the three-phase three-wire system is controlled for two phases out of three phases, the remaining one phase is automatically determined. Therefore, when the input signal for any one phase is near the zero point, the load current is controlled by the other two phases, and as a result, the three-phase current is controlled so as to match the command value.

When the input signal for one phase is near the zero point,
The output voltage of the phase becomes a positive or negative constant value, which gives a disturbance to the current control of other phases. Therefore,
Compensation voltage that cancels this disturbance is applied to the other two-phase PWM
In addition to the control input signal.

In this way, the three-phase load current can be continuously controlled regardless of whether the PWM control input signal is small or large, and the conventional problems can be eliminated.

[0029]

1 is a block diagram of a three-phase three-wire neutral point clamp type inverter device for explaining a first embodiment of a control method of the present invention. This is a roughly three-phase, three-wire type AC load, for example, a three-phase AC motor M, a neutral point clamp type inverter INV for obtaining a three-phase output, and the inverter INV.
Means for detecting the output current of each of them by current detectors CT _U , CT _V , CT _W , and controlling so as to match the command value, for example, comparators C _d , C _q , current control compensation circuits G _d (S), G
_q (S), coordinate converters VEC-1, VEC-2,
A pulse width modulation control circuit PWM _U , PWM _V , PWM _W that receives the signal from the current control means as an input signal, and means for applying a bias voltage to the input signal of the pulse width modulation control circuit, such as a bias circuit BIAS and an adder A. _U , _AV ,
A _W and a means (not shown) for turning on and off the bias voltage are provided.

FIG. 1A is a main circuit diagram, which has a structure in which three sets of the conventional single-phase neutral point clamp type inverters described above are connected in a Y-shape. That is, one of them is four self-extinguishing elements S _{11 to} S connected in series.
₁₄ and free wheeling diodes D _{11 to} D ₁₄ connected in antiparallel to the self-extinguishing elements S _{11 to} S ₁₄ , respectively.
And three clamping diodes D ₁₅ and D ₁₆ which are parallel to the two self-extinguishing elements S ₁₂ and S ₁₃ and which are connected in series in reverse polarity to each other. It is designed to generate the output voltage of.

Similarly, the other two sets of single-phase neutral point clamp type inverters also have self-extinguishing elements S _{21 to} S ₂₄ , S _{31 to} S ₃₄ ,
Is composed of a freewheeling diode _{D 21 ~D 24, D 31 ~D} 34 and clamping diode _{D 25, D 26, D 35} , D 36. On the input side of the neutral point clamp type inverter body INV having such a configuration, DC voltage sources V _d , V _d1 ,
V _d2 is connected, and a three-phase AC motor M (load LOAD) is connected to the output side thereof. Then, each self-extinguishing element S ₁₁
Up to S ₁₄ , S _{21 to} S ₂₄ , and S _{31 to} S ₃₄ are PWM-controlled.

As the control circuit, as shown in FIG. 1B, comparators C _d and C _q and a current control compensating circuit G are provided.
_d (S), G _q (S), coordinate converter VEC-1, VEC
-2, adders A _U , A _V , A _W , bias circuit BIA
S, PWM control circuits PWM _U , PWM _V , and PWM _W are prepared.

The three-phase load currents I _U , I _V , and I _W are shown in FIG.
Current detector CT _U of (a), detected by CT _V, CT _W, the coordinate converter VEC-1, a current of d-q coordinates I
Convert to _d , I _q . The dq coordinates are a coordinate system synchronized with the rotation of the rotor of the electric motor, and the d axis is the coordinates of the field pole. The currents I _d and I _q converted in this way are direct current amounts, and generally, I _d represents an exciting current (field current) component, and I _q represents a torque current component.

The exciting current command value I _d ^* of the electric motor and the exciting current detection value I _d are input to the comparator C _d , and the deviation ε _d
= I _d ^* -I _d is obtained. In addition, the comparator C _q has
The torque current command value I _q ^{* of the} electric motor and the detected torque current value I _q are input, and the deviation ε _q = I _q ^* −I _q is obtained. These deviations ε _d and ε _q are amplified by the current control compensation circuits G _d (S) and G _q (S), respectively, and the signals e _d and
the e _q. The signal e _d, e _q coordinate converter VEC-
By 2, the three-phase alternating current amounts e _U , e _V , and e _W are again converted back.

On the other hand, the bias circuit BIAS generates a constant or variable DC bias voltage e _b and inputs it to the adders A _U , A _V and A _W. The adder A _U adds the three-phase AC amount e _U and the bias voltage e _b , and inputs e _U1 = e _U + e _b to the U-phase PWM control circuit PWM _U. The same applies to the V phase and the W phase. This bias voltage e _b is applied only when the amplitude of the three-phase alternating current amounts e _U , e _V , and e _W is small,
When the amplitude becomes large, the bias voltage e _b is made zero.

FIG. 2 shows the relationship between the PWM control input signals e _U1 , e _V1 , e _W1 and the triangular wave X when the bias voltage e _b is applied. -E _{G to} E _G represent the uncontrollable range determined by the initial on-time of the device. By applying the positive bias voltage e _b , the input signals e _U1 , e _V1 and e _W1 fall into a range smaller than the maximum value E _max of the triangular wave X and larger than the level E _G. Output voltage V _{U of the} inverter,
V _V and V _W have values proportional to the input signals e _U1 , e _V1 and e _W1 .

In the load M of the three-phase three-wire type, the load current is determined by the line voltage, and the bias voltage of each phase is canceled. That is, the line voltages V _UV , V _VW , and V _WU are as follows, where k is a proportional constant.

V _UV = V _U −V _V = k · (e _U1 −e _V1 ) = k · (e _U + e _b −e _V −e _b ) = k · (e _U −e _V ) V _VW = V _{V -V W = k · (e} V1 -e W1) = k · (e V + e b -e W -e b) = k · (e V -e W) V WU = V W -V U = k · _{(e W1 -e U1) = k} · (e W + e b -e U -e b) = k · (e W -e U) Thus, the line voltage applied to the load of a three-phase three-wire V
_UV , V _UW and V _WU are only related to the original control inputs e _U , e _V and e _W and are independent of the bias voltage e _b . Moreover, the load current can be continuously controlled without being caught in the uncontrollable region.

When the amplitudes of the three-phase alternating current amounts e _U , e _V , and e _W become large, the bias voltage e _{b is set} to zero.

FIG. 3 is a time chart showing the PWM operation of the device of FIG. 1 when the bias voltage e _{b is set} to zero. In the figure, X and Y are positive and negative triangular waves (carrier waves), e _U1 , e _V1 , and e _W1 are PWM control input signals when e _b = 0, V _U , V _V , and V _W are Indicates the output phase voltage of the inverter. Input signal e _U1 is out of control-
When entering into E _{G to} E _G , the pulse width of the gate signal becomes constant and the output voltage V _U becomes a constant value of V _G or −V _G. The same applies to the output voltages of the other phases. That is, the shaded portions of the output voltages V _U , V _V , and V _W act as a disturbance when viewed from the load current control.

[0041] However, for example, between point b from point a voltage V _U, U-phase voltage V _U is becomes uncontrollable, this time, V
The voltages V _V and V _W of the phase and the W phase are in a controllable region, and when the current control is performed, the voltages V _V and V _W are corrected and the load current is controlled to a waveform close to a sine wave.

The uncontrollable period (ab) becomes shorter as the amplitude E _m of the input signal e _U1 becomes larger, and the influence of disturbance becomes smaller. Therefore, it is desirable to set the bias voltage e _b to zero when the amplitude _Em is as large as possible.

In FIG. 4, the bias voltage e _b is the direct current component e _{b (DC)} , and the third harmonic voltage e _{b (AC)} synchronized with the output frequency is superimposed. The amplitude values of the control input signals e _U1 ′, e _V1 ′, e _W1 ′ are smaller than the amplitude values of the input signals e _U1 , e _V1 , e _W1 in FIG. Therefore, the amplitudes of the original signals e _U , e _V , and e _W can be increased by that amount, and the bias voltage e _b is switched to zero when the amplitude of the signals e _U , e _V , and e _W is large. You can That is, by adding an AC component in addition to the DC component as the bias voltage, it is possible to reduce the disturbance when the bias voltage is zero.

FIG. 5 is a control circuit block diagram for explaining the second embodiment of the control method of the present invention. BI in the figure
AS is a bias voltage generator, A _{1 to} A ₁₂ are adder / subtractor, H
_{1 to} H ₃ are signal correction circuits, PWM _U , PWM _V , PWM
_W is a PWM control circuit.

The bias voltage generator BIAS generates the bias voltage e _b when the amplitude value E _m of the three-phase input signals e _U , e _V and e _W is small, and when the amplitude value becomes large,
Let e _b = 0.

Each input signal e is added by the adders A _{1 to} A ₃ .
_A bias voltage e _b is applied to _U , e _V , and e _W, and e _U1 = e _U + e _b , e _V1 = e _V + e _b , e _W1 = e _W +, respectively.
The signal e _b is output.

[0047] Figure 6 represents the input-output characteristics of the signal correction circuit H ₁ to H ₃ in FIG. 5, when the input signal e ₁ is in among 0 to E _G is the output signal e ₂ = E _G , Input signal e ₁
There When in among 0 to-E _G, the output signal e ₂ = -E _G
And in other areas, e ₂ = e ₁ . Here, E _G is a constant value in consideration of the uncontrollable region described above.

In FIG. 5, the subtractor A ₄ calculates the difference between the output signal e _U2 and the input signal e _U1 of the signal correction circuit H ₁ , and Δe
_U = e _U2 −e _U1 is required. Similarly, the subtractors A ₅ , A
₆ are Δe _V = e _V2 −e _V1 , and Δe _W = e _W2 −e _{W1 respectively.}
To calculate. These difference voltages Δe _U , Δe _V , Δe
_W is an amount proportional to the disturbance voltage associated with the uncontrollable region.

Output signal e of U-phase signal correction circuit H _1
U2 is added with the difference voltages Δe _V and Δe _W via the adders A ₇ and A ₈ , and is input to the PWM control circuit PWM _U as e _U3 = e _U2 + Δe _V + Δe _W.

Similarly, the V-phase and W-phase input signals are also added via adders A ₉ , A ₁₀ and A ₁₁ , A ₁₂ , respectively, e _V3 = e _V2 + Δe _U + Δe _W e _W3 = e _W2 + Δe _U It becomes + Δe _V.

FIG. 7 shows the PW obtained as described above.
The waveforms of the M control input signals e _U3 , e _V3 , and e _W3 are shown. However, the case where the bias voltage e _b is zero in the state where the amplitude values of the initial input signals e _U , e _V , and e _W are large is shown.

When the input signals e _U1 , e _V1 and e _W1 are between the uncontrollable areas −E _{G to} E _G , the signal correction circuits H _{1 to} H _{3 are} generated.
Fixed to either -E _G or E _G by a fixed value. For example, during the period in which the U-phase signal e _U2 is fixed at a constant value, a disturbance is generated by the difference voltage Δe _U , which disturbs the output current of the inverter. Therefore, another V voltage is used to cancel the disturbance voltage Δe _U. Phase and W phase input signals e _V2 , e _W2
In addition to. That is, finally the PWM control input signals e _U3 , e _V3 , and e _W3 become as shown in FIG.
When the M control is disabled, the PWM control can be performed so that the other two phases compensate for it, and the influence of the disturbance can be eliminated.

In FIG. 5, the original input signal e _U ,
When the amplitude values of e _V and e _W are small, the bias voltage e _b is added, and the inputs e _U1 , e _{V1 of} the signal correction circuits H _{1 to} H ₃ ,
e _W1 is always outside the uncontrollable area, and signal correction circuit H
_{1 to} H ₃ output signals e _U2 , e _V2 , e _W2 are input signals e _U1 ,
It becomes equal to e _V1 and e _W1 . Therefore, the difference voltage Δe _U , Δ
e _V and Δe _W become zero at this time, and the PWM control input signals e _U3 , e _V3 , and e _W3 are: e _U3 = e _U1 = e _U + e _b e _V3 = e _V1 = e _V + e _b e _W3 = e _W1 = e _W + e _b . The operation at this time is the operation described in FIGS. 1 and 2, and the three-phase load current can be continuously controlled.

FIG. 8 shows another example of the input / output characteristics of the signal correction circuits H _{1 to} H ₃ shown in FIG. 5. When the input e ₁ is between the uncontrollable areas −E _{G to} E _G , The output e _{2 is set} to zero. Meanwhile, the PWM control input becomes zero, no gate pulse is generated, and the output voltage also becomes zero.

FIG. 9 shows a signal correction circuit H having the characteristics shown in FIG.
Difference voltages Δe _U , Δe _V , Δe when _{1 to} H ₃ are used
_The waveforms of _W and the PWM control input signals e _U3 , e _V3 , and e _W3 are shown. However, the case where the bias voltage e _b is zero in the state where the amplitude values of the initial input signals e _U , e _V , and e _W are large is shown.

When the input signals e _U1 , e _V1 and e _W1 are between the uncontrollable areas −E _{G to} E _G , the signal correction circuits H _{1 to} H _{3 are} generated.
Fixed to zero by. For example, during a period in which the U-phase signal e _U2 is fixed to zero, a disturbance is generated by the difference voltage Δe _U , which disturbs the output current of the inverter. Therefore, the other V-phase is canceled so as to cancel the disturbance voltage Δe _U. And W phase input signals e _V2 and e _W2 . That is, finally PW
The M control input signals e _U3 , e _V3 , and e _W3 are as shown in FIG. 9, and in this case as well, when one phase is PWM control disabled, the other two phases are PWM controlled so as to compensate for it. In addition, it is possible to eliminate the influence of the disturbance.

In this way, the three-phase load current can be continuously controlled regardless of whether the PWM control input signal is small or large, and the conventional problems can be eliminated.

[0058]

As described above, according to the control method of the three-phase three-wire type neutral point clamp type inverter of the present invention, the PWM
Regardless of the magnitude of the amplitude of the control input signal, the control can be performed in the entire range, and the sinusoidal current with less ripple can be supplied to the motor load or the like.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a neutral point clamp type inverter device for explaining a first embodiment of a control method of the present invention.

FIG. 2 is a chime chart for explaining a control method of the device of FIG.

FIG. 3 is a chime chart for explaining a control method of the apparatus of FIG.

FIG. 4 is a chime chart for explaining a control method of the apparatus of FIG.

FIG. 5 is a configuration diagram of a control circuit for explaining a second embodiment of the present invention.

6 is a characteristic diagram for explaining the operation of the circuit of FIG.

7 is a time chart for explaining the operation of FIG.

8 is a characteristic diagram for explaining the operation of the circuit of FIG.

9 is a time chart for explaining the operation of FIG.

FIG. 10 is a main circuit configuration diagram for explaining a control method of a conventional neutral point clamp type power converter.

FIG. 11 is a time chart for explaining the control method of FIG.

12 is a time chart for explaining the control method of FIG.

[Explanation of symbols]

V _d , V _d1 , V _d2 ... DC voltage source, INV ... Neutral point clamp type inverter, M ... 3-phase AC motor, S _{11 to} S ₁₄ , S
_{21 ~S 24, S 31 ~S 34} ... self-turn-off device, D ₁₁ ~D _14, D
_{21 to} D ₂₄ , D _{31 to} D ₃₄ ... Free wheeling diode,
_{D 15, D 16, D 25} , D 26, D 35, D 36 ... clamping _{diodes, CT U, CT V, CT} W ... current detector, C _d,
C _q ... _{comparator, G d (S), G} q (S) ... current control compensation circuit, VEC-1, VEC-2 ... coordinate converter, A _U, A
_V , A _W ... Adder, BIAS ... Bias circuit, PW
M _U , PWM _V , PWM _W ... PWM control circuit, A _{1 to} A
₁₂ ... subtractor, H ₁ to H ₃ ... signal correction circuit.

Claims (3)

[Claims] 1. Four self-extinguishing elements connected in series,
A freewheeling diode connected to each self-extinguishing element in anti-parallel, and two clamps connected in series to the two self-extinguishing elements in reverse polarity to each other. Three sets of single-phase neutral point clamp type inverters for generating three-level output voltage composed of diodes are prepared, each inverter is connected in Y-shape, and each self-extinguishing element is controlled by pulse width modulation. In the neutral point clamp type inverter, the three-phase input signals e _U , e _V , e _{W of the} pulse width modulation control are provided.
When the amplitude value E _{m of} is small, the input signals e _U ,
e _V, direct current e _W bias voltage e _{b (DC),} or DC bias voltage e _{b (DC)} and AC bias voltage e _{b (AC)}
Any added, when the amplitude value E _m is increased, the three-phase three-wire neutral point clamp type inverter control method of which is characterized in that the said bias voltage to zero. 2. Four self-extinguishing elements connected in series,
A freewheeling diode connected to each self-extinguishing element in anti-parallel, and two clamps connected in series to the two self-extinguishing elements in reverse polarity to each other. Three sets of single-phase neutral point clamp type inverters for generating three-level output voltage composed of diodes are prepared, each inverter is connected in Y-shape, and each self-extinguishing element is controlled by pulse width modulation. In the neutral point clamp type inverter, the three-phase input signals e _U , e _V , e _{W of the} pulse width modulation control are provided.
Of these, the reference level E _{G that} has the absolute value of the one-phase input signal
When it becomes smaller, the input signal of the phase is fixed to zero or to a positive or negative constant value E _G , while
A method for controlling a three-phase three-wire neutral point clamp type inverter, characterized in that the pulse width modulation control of the other three phases of the three-phase output current of the neutral point clamp type inverter is performed. 3. Four self-extinguishing elements connected in series,
A freewheeling diode connected to each self-extinguishing element in anti-parallel, and two clamps connected in series to the two self-extinguishing elements in reverse polarity to each other. Three sets of single-phase neutral point clamp type inverters for generating three-level output voltage composed of diodes are prepared, each inverter is connected in Y-shape, and each self-extinguishing element is controlled by pulse width modulation. In the neutral point clamp type inverter, the three-phase input signals e _U , e _V , e _{W of the} pulse width modulation control are provided.
When the amplitude value E _{m of} is small, the input signals e _U ,
e _V, e _W DC bias voltage e _{b (DC)} or bias voltage e _b of the sum of the DC and AC _{(DC) + e b (AC} ) was added to pulse width modulation control on the amplitude value E _m is increased When the bias voltage is zero and the absolute value of the one-phase input signal among the three-phase input signals e _U , e _V , and e _W is smaller than a certain reference level E _G , the input signal of the phase Is fixed to zero or to a positive or negative constant value E _G , during which the three-phase output current of the neutral point clamp type inverter is pulse width modulated controlled by the other two phases. Control method for 3-wire neutral point clamp type inverter.