JPH05151298A - Automatic inspection processing method for printed circuit - Google Patents

Abstract

PURPOSE:To obtain an automatic inspection processing method capable of economically automating the inspection of a printed circuit by utilizing the inspection data of a scanning circuit. CONSTITUTION:Definition data forming processing 1 forms definition data of required observation points and respective signal conditions from LSI inspection data 2 and printed circuit logical circuit data 3 and simulation execution processing 5 executes logical simulation based upon the data 3, 4, inspects the signal of a required observation point in an LSI by simulation for inputting signal from a printed circuit terminal and simulating the arriving state of the signal at the point, collates and inspects between an output signal and an input signal by simulation for inputting a signal to an observation point corresponding to the output of the LSI and then outputting the signal to a required printed circuit terminal, and obtains the inspection result 6 of a logical model based upon respective collated results.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board mounted with a large-scale integrated circuit having a scan circuit, and to a method for automatically verifying a circuit related to the scan circuit by a computer.

[0002]

2. Description of the Related Art In a large scale integrated circuit (hereinafter referred to as LSI), an LSI
A known scan circuit is incorporated in the LSI when it is necessary to diagnose the internal circuit.

When such an LSI is mounted on a printed board, the printed board circuit controls the scan circuit of each LSI by a signal given from the outside of the printed board for diagnosis of the required LSI. , A circuit for taking out the output from the scan circuit is added.

FIG. 2 shows an example of a printed circuit board on which an LSI having the above-described scan circuit is mounted. On the left side is an external terminal for connecting the printed circuit board to the outside, which is a terminal related to the scan circuit. There are LA0 to LAn, RESET, SI and SO, and the signals of these terminals are distributed to each LSI via the SCAN LSI.

In each SCAN LSI, a part of LA0 to LAn is
It receives it as its own selection signal, decodes the other part into a chip select (CS) signal, and the remaining part of each LSI
As an address (ADDRESS) signal for selecting the scan / latch of the internal scan circuit, it is connected together with other signals so as to be distributed to each of m LSIs (LSI1 to LSIm).

It should be noted that SET is ADDRE for other signals shown in the figure.
The signal that determines the set / reset of the latch selected by the SS signal, SI is the scan-in signal, and SO is the scan-out signal.

When verifying the connection of such a printed circuit board, a logical simulation of the printed circuit board including the scan circuit of the LSI is performed, and therefore, the LSI is used for that purpose.
It is necessary for the circuit designer to perform definition of the scan circuit and definition of input / output signal conditions.

For this reason, there is a problem that a relatively large amount of manpower is required, the amount of logic simulation is large, the simulation takes time, and definition errors due to manpower are likely to occur.

According to the present invention, since the verification of the scan circuit of the LSI is carried out by itself, the data is used to carry out the verification by the simulation of the printed circuit board economically and automatically. With the goal.

[0010]

FIG. 1 is a flow chart of processing showing the configuration of the present invention. The figure shows the structure of an automatic verification processing method for a printed circuit board, in which a printed circuit board equipped with a large-scale integrated circuit having a predetermined scan circuit is
The predetermined logical model of the printed circuit board is verified.

In the definition data generation process 1, from predetermined verification data 2 relating to the large scale integrated circuit and predetermined logic circuit data 3 representing the logic model, required observation points on the logic model and the respective observation points. The definition data 4 having the signal condition of the observation point is generated.

In the simulation execution process 5, with reference to the definition data 4, a logic simulation of the printed circuit according to the logic circuit data 3 is executed. In the simulation, a required signal is input from a required printed circuit board terminal that connects the printed circuit board circuit to the outside, and the signal is caused at the required observation point of the large scale integrated circuit to be selected by the signal. The signal at the observation point is inspected by referring to the signal condition by the simulation of the arrival of the signal.

Further, the simulation of a state in which a signal according to the signal condition is input to a required observation point corresponding to the output of the scan circuit of the large scale integrated circuit and the signal is output to the required printed circuit board terminal. Thus, the processing of verifying the output signal with the input signal and verifying the logical model by the respective inspection results is sequentially executed for each of the large-scale integrated circuits to obtain the verification result 6.

[0014]

According to the automatic verification processing method of the present invention, data concerning a predetermined terminal (pin) related to the scan circuit is extracted from the verification data created in the logic simulation of the LSI alone, and the logic circuit data of the printed circuit is referred to. , The definition data indicating the position information and the signal conditions such as the signal polarity is automatically generated with the point on the printed circuit board where the terminal extracted above is placed as an observation point.

For the observation points indicated by the definition data, a logic simulation is executed using logic circuit data, and the input signal from the external terminal of the printed board is changed to a signal condition at each observation point of the intended LSI designated by the signal. If it arrives at the correct value in light, the LSI is supposed to operate correctly. Therefore, it is not necessary to perform the simulation inside the LSI.

Further, on the output side of the scan circuit of the LSI, it is assumed that a signal complying with the signal condition appears at the observation point, a logic simulation of the printed circuit board is performed, and the signal is correctly output to a predetermined external terminal. For example, it is assumed that the output side has been verified.

Therefore, in order to verify the printed circuit board related to the scan circuit, no manual definition input is required, and the processing amount of the logic simulation is reduced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a flow chart of processing showing an embodiment of the present invention. LSI verification data 2 is data generated as a result of a single verification of a scan circuit of each LSI mounted on a printed board to be verified. To use.

In this embodiment, the definition data generation process 1 of FIG. 1 comprises an information extraction process 10 and a definition data editing process 11. The information extraction process 10 includes an LSI verification data 2 and a printed circuit circuit logic circuit data 3. With the input as the input, by using the identification name of the required pin of the LSI extracted from the LSI verification data 2 (ADDRESS, CS, SET, SI, SO, etc. in the example of FIG. 2), the point to be observed on the logic circuit data is observed. Point data is selected, and the input / output pin name of each observation point and data such as signal conditions are output as input / output pin data 12.

The definition data editing process 11 receives the input / output pin data 12 as an input, encodes the content so that it can be used efficiently in simulation execution, and edits it into a predetermined simulation table to obtain definition data 4. ..

As for the logic circuit data 3, the logic circuit data editing process 13 extracts only the data required for the simulation from the logic circuit data 3 and edits it into an appropriate data structure so that the simulation can proceed efficiently. The simulation table 14 is created.

In the simulation execution processing 15, the definition data 4 and the simulation table 14 are input,
Perform a logical simulation. In this logical simulation, for the input signal, from the external terminal of the printed board to the observation point provided on the input pin of the LSI,
Regarding the output signal, the signal flow from the observation point provided on the output pin of the LSI to the external terminal is simulated, and the simulation inside the LSI is not performed.

That is, the printed circuit board of FIG. 2 will be described as an example. LA0 to LAn, RESET, SI, SO, ADDRESS1 to ADDRES are used as terminals and observation points related to the scan circuit.
Information such as Sm, CS1 to CSm, SET1 to SETm, SI1 to SIm, SO1 to SOm is given by the definition data 4 and the simulation table 14.

In the simulation execution process 15, the input side is processed in the first stage, addresses are set in LA0 to LAn, and appropriate values are input to RESET, SI, and SO to simulate the scan-in operation. , LSI1 to LSIm, and observe whether the input observation point becomes the desired scan-in state.

If the desired state is obtained at the input observation point, the fact that scan-in is performed in the designated scan latch inside the LSI has already been verified separately as described above. There is no need to observe.

Next, as a second step, the output side is processed to verify that the output of the scan circuit of each LSI is correctly transmitted to the external terminal of the printed board. This is the observation point on the output side, SO, of the LSIj that has the scan latch in the selected state at a certain address as described above.
By setting a signal value (1 or 0) in j and giving the address of the LSIj from the external terminal, it is confirmed that the signal set in SOj is output to SO of the external terminal.

By performing the above processing for each LSI, the verification result 6 regarding the scan circuit of the printed circuit board can be obtained.

[0028]

As is apparent from the above description, according to the present invention, by using the verification data of the scan circuit of the LSI in the computer processing for verifying the printed circuit board mounting the LSI having the scan circuit, There is a remarkable industrial effect that the automatic verification process by the logic simulation of the printed circuit board is realized as an economical and highly reliable process.

[Brief description of drawings]

FIG. 1 is a process flow chart showing the configuration of the present invention.

FIG. 2 is a diagram showing an example of a printed circuit board model.

FIG. 3 is a flow chart of processing showing an embodiment of the present invention.

[Explanation of symbols]

 1 Definition data generation processing 2 LSI verification data 3 Printed circuit logic circuit data 4 Definition data 5, 15 Simulation execution processing 6 Verification result 10 Information extraction processing 11 Definition data editing processing 12 Input / output pin data 13 Logic circuit data editing processing 14 Simulation table

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location G06F 11/26 310 9072-5B 15/60 370 A 7922-5L

Claims (1)

[Claims] 1. When verifying a predetermined logical model of a printed circuit board on which a large-scale integrated circuit having a predetermined scan circuit is mounted, the definition data generation process (1) is performed by the large-scale integrated circuit. Definition data having a required observation point on the logical model and a signal condition of each observation point from the predetermined verification data (2) regarding the circuit and the predetermined logic circuit data (3) representing the logical model. (4) is generated, the simulation execution process (5) refers to the definition data (4), executes a logic simulation of the printed circuit board according to the logic circuit data (3), and executes the printed circuit board. A state in which a signal resulting from the signal reaches a required observation point of the large-scale integrated circuit to be selected by the signal by inputting a required signal from a required printed board terminal connected to the outside. By the simulation, the signal at the observation point is inspected with reference to the signal condition, and the signal according to the signal condition is input to the required observation point corresponding to the output of the scan circuit of the large-scale integrated circuit. , A process of verifying the output signal against the input signal by the simulation of the state in which the signal is output to the required printed circuit board terminal, and verifying the logical model by each of the inspection results,
An automatic verification processing method for a printed circuit board, which is configured to be sequentially executed for each of the large scale integrated circuits.