JPH06215067A - Method for verifying easiness of test of mounted board - Google Patents

Abstract

PURPOSE:To prevent a design of mount board hardly tested from being generated by verifying the easiness of a test of the mount board and to prevent variance in the easiness of the test of the mount board from being generated depending upon the skill of a designer. CONSTITUTION:A data input procedure 3 inputs net list information 1 and mounted component information 2 on the mount board and generates a table 4. A connection verification procedure 5 verifies the connection relation of a signal such as a loop net by referring to the table 4. A component discrimination procedure 7 discriminates the functions of the mounted components by referring to the table 4. A function verification procedure 8 verifies the easiness of tests by the functions. The verification results 6 of them are held. A result output procedure 9 reads the verification results 6 out and displays them in a circuit diagram, etc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting board testability verification method, and more particularly to a mounting board testability verification method for verifying a testability design of a mounting board.

[0002]

2. Description of the Related Art A conventional mounting board testability verification method is as follows.
Assuming that an in-circuit test will be performed using a tester at the time of inspection, the mounting board designer verifies the testability design for the mounting board by thoroughly checking the design restrictions on the desk. .

[0003]

In the conventional mounting board testability verifying method described above, the designer checks the design restrictions on the desk to verify the testability design for the mounting board. Therefore, check omissions may occur and variations due to the skill level of the designer may occur, which may interfere with the in-circuit inspection of the mounting board later, and the testability may be poor at the inspection stage. Even if it becomes clear, there is a drawback that it is difficult to change the circuit design of the mounting board.

[0004]

A mounting board testability verification method of a first invention is a mounting board testability verification method for verifying testability in an in-circuit test of a mounting board. The data input procedure for inputting the mounting information, which is the information of the components mounted on the board and the list information, and the netlist information and the mounting information input by the data input procedure, are mounted on the board. Connection verification procedure for verifying the connection relationship of signals transmitted and received between existing components, and a component identification procedure for identifying the function of each component mounted on the board from the mounted component information input by the data input procedure. , Verifying the inspectability of whether it is easy to test for each function of each component mounted on the board based on the function identified by the component identification procedure That a functional verification procedure, and a result output procedure for displaying on the connection verification step and the functional verification procedure each verification result by well screen identification result by the part identification procedure.

The mounting board testability verification method of the second invention is a mounting board testability verification method for verifying the testability of an in-circuit test of a mounting board. Input the mounted component information that is the information of the components mounted on the above, and verify the connection relation of the signals transmitted and received between the components mounted on the board with the input netlist information and the mounted component information. Then, it is easy to identify the function of each component mounted on the board from the input mounted component information, and to easily test each function of each component mounted on the board based on the identified function. This includes verifying the inspectability of whether or not the result of verification and the result of identification are displayed on a screen or output to a printer.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a flow chart showing an embodiment of a mounting board testability verification method of the present invention.

As shown in FIG. 1, the data input procedure 3 is
The netlist information 1 of the mounting board and the mounting part information 2 storing the function information of the mounting parts are input, converted into a table format and stored in the table 4.

Further, in the connection verification procedure 5, the nets output from the component referring to the table 4 are extracted as nets that are input to itself, and these are held in the verification result 6, etc. , The connection relationship of signals transmitted and received between each component mounted on the board is verified.

Then, the component identification procedure 7 refers to the table 4 to identify the function of each component mounted on the board from the component information.

Next, based on the function identified in the component identification procedure 7, the function verification procedure 8 determines whether or not the necessary test facilitation design is performed for each function of each component mounted on the board. The inspectability is verified, and the verification result 6 is held.

Therefore, in the result output procedure 9, the verification result 6 is read and the error location is displayed interactively on the screen of the circuit diagram.

The reason why the loop net is detected in the connection verification procedure 5 is that the output signal from the component under test returns as an input signal during the inspection of the in-circuit, so that the input signal from the tester is correct. This is because it cannot be applied.

FIG. 2 is a block diagram showing an example of the contents of the table 4. The table 4 created by the data input procedure 3 has a parts table 21, a pin table 22, a net table 23, and a pin link table 24, as shown in FIG.

Then, the parts table 21 is
Mounting position, component name, function, number of input pins, pin table 2
A pointer to the first input pin in 2 and the number of output pins, a pointer to the first output pin in the pin table 22 and the number of bidirectional pins are stored.

The pin table 22 includes a pin name, a pin input / output distinction for each pin, a wired net flag in which outputs from a plurality of components are combined, and a net table 23.
A pointer to a corresponding net in the table, a pointer to a pin having a function of controlling the signal value of this pin to the Hi-z state which is a high load state, and a pointer to the parts table 21 are stored.

On the other hand, the net table 23 has a net name,
Number of input pins connected to this net, pointer to pin link table 24 for each input pin connected to this net, number of output pins connected to this net, pin link table 24 for each output pin connected to this net Stores a pointer to.

Further, the pin link table 24 stores a pin table pointer and a next pin table pointer for linking pins connected to the same net.

In the present embodiment, by referring to each of these tables, tracing inside the circuit on the mounting board is performed and information necessary for the verification result is created.

FIG. 3 is a flow chart showing an example of the operation of the function verification procedure 8. First, in the function verification procedure 8, as shown in FIG. 3, in the judgment step 31, it is judged whether or not the verification processing has been executed for all mounted components. At this time, if all the parts have been verified, the process ends.

On the other hand, when there is a component to be verified, the next oscillator verification 32 determines whether or not the oscillation function can be stopped at the time of inspection when the component to be verified is an oscillator. Specifically, there is a control pin that enables the output signal value and it can be controlled from the tester, or there is a board connector or jumper mechanism on the output side, or the output side IC is enable control. Fig. 2
Table 4 of FIG.

Then, in the processor verification 33, when the component to be verified is a processor, there is a control pin capable of enabling the output value in the processor itself, and it can be controlled from the tester or the clock signal is supplied. Verify whether it is possible to control without inputting.

Next, in the CMOS-IC verification 34, when the component to be verified is a CMOS-IC, there is a control pin capable of enabling the output value in the CMOS-IC itself, and the control can be performed from the tester. Verify if possible.

Further, the RAM / ROM verification 35 verifies whether or not the input side signal can be controlled from the tester when the verification component is RAM or ROM.

On the other hand, the wired net verification 36 verifies whether each output signal can be enabled and controlled when there is a wired logic in which outputs from a plurality of components are combined with the output signal. If it is impossible, the output value cannot be observed when inspecting the parts of the same net.

On the other hand, the clamp signal verification 37 verifies whether the power source or the ground is directly used as the clamp source when the clamp signal exists in the component to be verified.

Further, the tester pin number verification 38 verifies whether or not the number of pins of the tester including the pins used for guarding control is sufficient when controlling or observing the component under test with the tester.

If an error occurs in any of the verifications, it is determined that the test is difficult, and information is output to the verification result 6 in FIG.

[0028]

As described above, the mounting board testability verification method of the present invention is different from the case where the designer performs the verification on the desk. Since it does not occur and is not affected by the skill of the designer, it has an effect that it is possible to prevent the in-circuit inspection of the mounting board from being disturbed in advance.

Further, according to the mounting board testability verification method of the present invention, it is easy to change the design of the circuit of the mounting board because the quality of the in-circuit test of the mounting board is determined at the design stage. Have an effect.

[Brief description of drawings]

FIG. 1 is a flowchart showing an embodiment of a mounting board testability verification method of the present invention.

FIG. 2 is a block diagram showing an example of contents of a table 4.

FIG. 3 is a flowchart showing an example of an operation of a function verification procedure 8.

[Explanation of symbols]

 1 Netlist information 2 Mounting component information 3 Data input procedure 4 Table 5 Connection verification procedure 6 Verification result 7 Component identification procedure 8 Function verification procedure 9 Result output procedure 21 Component table 22 Pin table 23 Net table 24 Pin link table

Claims (2)

[Claims] 1. In a mounting board testability verification method for verifying the easiness of a test in an in-circuit test of a mounting board, netlist information of the mounting board and mounted part information which is information of parts mounted on the board. And a connection verification procedure for verifying a connection relationship of signals transmitted and received between components mounted on a board with the netlist information and the mounting component information input by the data input procedure. , A component identification procedure for identifying the function of each component mounted on the board from the mounting component information input by the data input procedure, and mounting on the board based on the function identified by the component identification procedure. Function verification procedure for verifying the inspectability of whether or not it is easy to test for each function of each part, the connection verification procedure and the function verification procedure And a result output procedure for displaying the identification result obtained by the component identification procedure on the screen. 2. In a mounting board testability verification method for verifying the easiness of a test in an in-circuit test of a mounting board, netlist information of the mounting board and mounting part information which is information of parts mounted on the board. Input, verify the connection relationship of signals transmitted and received between the components mounted on the board with the input netlist information and the mounted component information, and mount on the substrate from the input mounted component information. The function of each component is identified and the inspectability of each component mounted on the board is verified based on the identified function to verify whether it is easy to test. A method of verifying testability of a mounting board, which displays an identification result on a screen or outputs to a printer.