JPH05150980A - Microcomputer - Google Patents

Abstract

PURPOSE:To efficiently execute a program by simplifying an instruction to vary a flag in an assembler program in which branch with a flag condition appears frequently by always performing the decision of a zero flag by a signal from a decoder, and setting a decision result on a flag register. CONSTITUTION:This microcomputer is comprised of a processor unit 10, and main memory 20 connected to the processor unit 10, and it is equipped with an ALU 11, a program counter 12, an A register 13, an instruction decoder 14, the flag registers 15, 16, and a decision circuit 17. When an instruction to always instruct decision on a status flag, for example, the zero flag is executed in the program, such execution is detected by the decoder 14, and hereinafter, the decision on the zero flag is always performed at the decision circuit 17 by the signal from the decoder 14 until the instruction of such decision is cancelled. The decision result is set on the zero flag register 16a of the flag register 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer for reducing the number of program steps in assembler language.

[0002]

2. Description of the Related Art A simple example of a conventional assembler program is shown in FIG. FIG. 3 (1) shows a part of the program list. To explain the contents, first, the contents of the address "1000" of the memory are registered in the A register according to the "LOAD A, 1000" of the statement number "10" of the program. Then, the contents of the A register and the data “0” are compared and judged according to the statement number “20”, “COMP A, 0”. At this time, if it is determined that the contents of the A register are "0" and the two are equal, the contents of the flag register (zero flag register) will be "0". And the sentence number “30”, “JMPZ
If the flag register is "0" according to "2000", the memory jumps to the address "2000" of the memory.

Changes in various registers and memories in the above program are shown in FIG. PC is a program counter, FR is a flag register (zero flag register),
ACC indicates the A register (accumulator), and is "10.
"00" to "2000" indicate memory addresses. "LOA
Since the "D" instruction does not change the flag, the contents of the flag register do not change even after the "LOAD" instruction is executed, as shown in the figure. Therefore, when a conditional branch such as "if the flag register is" 0 "" is required like "JMPZ" of the sentence number "30", the "COMP" of the sentence number "20" must be preceded by it. The comparison instruction for changing the flag is required.

[0004]

As described above, some assembler programs do not cause a change in the status flag in register operations with certain types of instructions, and when this requires a conditional branch, flag determination is performed. It was necessary to add an instruction for. Therefore, particularly in a program in which such conditional branching frequently occurs, there is a problem that the entire program becomes unnecessarily long and the processing efficiency becomes poor.

The present invention has been made in view of the above situation, and an object thereof is to provide an instruction for changing a flag in a program in which branches with a condition of the flag frequently appear. It is to provide a microcomputer capable of efficiently executing a program by omitting it.

[0006]

That is, according to the present invention, when an instruction for instructing constant determination for a specific status flag, for example, a zero flag is made in a program, this is detected by a decoder, and thereafter this constant determination is made. The zero flag is always judged by the signal from the decoder until the instruction of is cancelled, and the judgment result is set in the flag register. It is possible to execute the program efficiently by simplifying the instruction for changing the.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows its circuit configuration. 10 is a processor unit, 20 is a main memory connected to the processor unit 10, and in the processor unit 10, an ALU 11, a program counter (PC) 12, and an A register are provided. (ACC) 13, instruction decoder 14, flag register 15,
16 and a determination circuit 17.

When the instruction decoder 14 decodes a "FLAGON" instruction for performing a constant flag determination, it outputs a signal that turns on to the AND circuit 17a of the determination circuit 17 when it decodes a "FLAGOFF" instruction for canceling the constant flag determination. The AND circuit 17b of the determination circuit 17 outputs the signal to be turned on. The A register 13 sends the output of each bit to the OR circuit 17c of the determination circuit 17, and the output of the OR circuit 17c is input to the AND circuit 17a. Further, the flag register 15 holds various status flags, the least significant bit of which is the zero flag register 15a, and other flag contents except the zero flag register 15a are read to the flag register 16 as they are, The contents of the zero flag register 15a are the same as those of the judgment circuit 17 described above.
Is read by the AND circuit 17b. And circuit 17
The output of a or the output of the AND circuit 17b is the OR circuit 17d.
Via the flag register 16 to the zero flag register (Z) 16a in the least significant bit.

With such a configuration, it is assumed that the program list as shown in FIG. 2 (1) is executed. That is, first, the program statement number "1""FLAGO
In accordance with the "N" instruction, the flag determination state is always set to change the contents of the zero flag register 16a of the flag register 16 in all the subsequent instructions.

Next, the "LOAD A, 10
The contents of the address "1000" of the main memory 20 are transferred to the A register 13 according to "00", and then the sentence number "2"
According to "JMPZ 2000" of "0", jump to the address "2000" of the main memory 20.

Thereafter, in order to cancel the above-mentioned constant flag determination state, the normal flag determination state is set in accordance with the "FLAGOFF" command of the sentence number "3000".

Changes in various registers and memories in the program shown in FIG. 2 (1) are shown in FIG. 2 (2), which will be described. However, the configuration of each register is shown in Fig. 3 (2) above.
The description is omitted because it is the same as that shown in FIG.

When the instruction decoder 14 decodes the first "FLAGON" instruction, the instruction decoder 14 sets the signal to the AND circuit 17a of the decision circuit 17 to "H" level. This signal enables the output of the OR circuit 17c, and thereafter the logical sum of all bit outputs of the A register 13 is set in the zero flag register 16a of the flag register 16 via the AND circuit 17a and the OR circuit 17d.

Therefore, the following "LOAD A, 100
According to "0", the contents of the address "1000" of the main memory 20 are transferred to the A register 13, and the contents are "000".
In that case, "0" is automatically set in the zero flag register 16a without any instruction for changing the flag.

After that, according to the next "JMPZ 2000", since the content of the zero flag register 16a is "0", the program jumps to the address "2000" of the main memory 20. At this time as well, the content of the A register 13 is "000", so that "0" is set again in the zero flag register 16a as shown in FIG.

Thereafter, the program progresses in sequence, and "FLA
When the instruction decoder 14 decodes the "GON" instruction, the instruction decoder 14 sets the signal to the AND circuit 17a of the determination circuit 17 to "L" level and simultaneously sets the signal to the AND circuit 17b to "H" level. This signal causes the flag register 15
The output of the zero flag register 15a becomes valid, and the normal flag determination state according to the instruction for changing the flag is set.

With the above arrangement, the instruction for changing the zero flag register 16a can be omitted during the period of setting "FLAGON", so that the processing is simplified and the program is shortened. You can

In the above embodiment, whether or not the judgment is always made is set only for the zero flag register among the flag registers. However, the present invention is not limited to this, and the same setting may be made for other status flags. Of course, it is possible.

[0020]

As described above in detail, according to the present invention, when an instruction for instructing a constant status flag, for example, a zero flag, is made in the program, the decoder detects the instruction, and thereafter the constant judgment is made. Until the instruction of is canceled, the zero flag is always judged by the signal from the decoder and the judgment result is set in the flag register.Therefore, the flag is set in the program in which the branch with the flag condition occurs frequently. It is possible to provide a microcomputer capable of simplifying an instruction for changing and efficiently executing a program.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of FIG.

FIG. 3 is a diagram illustrating the operation of a conventional microcomputer.

[Explanation of symbols]

10 ... Processor unit, 11 ... ALU, 12 ... Program counter, 13 ... A register, 14 ... Instruction decoder, 15 ... Flag register, 16 ... Flag register, 17 ... Judgment circuit, 20
… Main memory.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 9292-5B G06F 9/44 320 D

Claims (1)

[Claims] 1. An instructing means for instructing constant determination of a specific status flag, a detecting means for detecting an instructed state by the instructing means, and a determining circuit for constantly determining the status flag based on a detection signal of the detecting means. And a flag register that holds a result determined by the determination circuit.