JPH05145112A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which is mounted so as to shorten the distance between a semiconductor chip electrode and a capacitor and reduces an impedance at a high frequency for a bias power source of a semiconductor chip required by a DC bias. CONSTITUTION:Capacitors 14a and 14b and a chip carrier 22 are loaded on a metal block 12 in such a fashion that they may be stacked. The electrodes on the bottom of the chip carrier 22 is bonded with top electrodes 18a and 18b of the capacitor 14a as stacked while they are connected to electrodes 28a and 28b on their top by way of penetration electrodes 30a and 30b which penetrate an insulation layer at the same time. A semiconductor photodetector chip 34, such as a twin type PIN photodiode is flip-chip-bonded with the electrodes 28a, 28b and 28c.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device mounted so that the impedance of a bias power supply for a semiconductor element requiring a DC bias is reduced at high frequencies. In semiconductor elements such as transistors and photodiodes that require DC bias,
When driving this semiconductor element at a high frequency, it is necessary to reduce the impedance as much as possible. Usually, a method of connecting a capacitor to a semiconductor element is used to reduce impedance at high frequencies.
As high-frequency characteristics above Hz have begun to be demanded, it is desired to place a capacitor as close as possible to the active region of the device.

[0002]

2. Description of the Related Art A conventional semiconductor device mounting method will be described with reference to FIG. FIG. 9 is a plan view showing a semiconductor device mounted by a conventional method. Grounded metal block 8
The chip carrier 84 and the capacitor 86 are installed adjacent to each other on the second substrate 2. Here, the chip carrier 84 is the insulating layer 8
8 and an electrode, and an electrode 90 on the upper surface of the insulating layer 88.
a, 90b, 90c are formed, and the back surface electrode 90 is formed on the back surface.
d is formed. In the capacitor 86, the upper surface electrode 92a and the lower surface electrode 92b which are parallel to each other are formed with the dielectric layer interposed therebetween.

The chip carrier 84 and the capacitor 86 are mounted in the following manner. That is, the chip carrier 84 is mounted by a method of soldering the back surface electrode 90d of the chip carrier 84 to the surface of the metal block 82 with the flux 94a of the low melting point metal. Similarly, the capacitor 86 is mounted by a method of soldering the lower electrode 92b of the capacitor 86 to the surface of the metal block 82 with the flux 94b of the low melting point metal.

Then, a semiconductor light-receiving element chip 96 such as a twin PIN photodiode in which two PIN photodiodes are connected in series is mounted on the chip carrier 84 by flip chip bonding. That is, the semiconductor light receiving element chip 96
Of the bonding bumps 98a, 98b, 98c of the electrodes 90a, 90 on the upper surface of the insulating layer 88 of the chip carrier 84.
Adhere to b and 90c respectively.

Further, the electrode 90b on the upper surface of the insulating layer 88 of the chip carrier 84 and the upper electrode 92a of the capacitor 86 are connected by a gold wire 99 of 20 μmφ. Since the capacitor 86 can be regarded as a power source in a high frequency region, using the mounting method of arranging the capacitor 86 as shown in FIG. 9, for example, at a high frequency of a DC bias applied to the bonding bump 98b of the semiconductor light receiving element chip 96. The impedance is lower than it would be without the capacitor 86.

[0006]

However, according to the above-mentioned conventional mounting method, the chip carrier 84 and the capacitor 86 are provided.
When and are installed adjacent to each other on the metal block 82, soldering is performed with the low melting point metal fluxes 94a and 94b. Therefore, in consideration of the controllability of the positions of the chip carrier 84 and the capacitor 86 during soldering, the protrusion of the fluxes 94a and 94b, and the like, the chip carrier 84 and the capacitor 8 are considered.
It is necessary to have a certain distance between 6 and. Therefore, there is a limit to the distance that the chip carrier 84 and the capacitor 86 can be brought close to each other, and the length of the gold wire 99 becomes long, so that the inductance cannot be reduced below a certain level.

Further, in the conventional example, the electrode 90b on the upper surface of the chip carrier 84 and the upper electrode 9 of the capacitor 86 are used.
There is a drawback due to the connection with 2a by a gold wire 99. To connect gold wires, a tool called a collet is used. A wire is passed through a hole in the center of the collet to the bonding position, and the tip of the collet is wire-crimped for connection. Usually, the tip of the collet has a thickness of about 100 μm, and therefore the position for bonding the wire needs to be kept away from the chip. For example, in order to prevent the edge of the semiconductor light receiving element chip 96 from being damaged by the collet at the time of wire bonding to the bonding position 99a, the distance d between the edge of the semiconductor light receiving element chip 96 and the bonding position 99a should be at least It must be 1/2 or more of the diameter of the collet. Considering safety, a margin of about 50 μm is required. Therefore, the distance d needs to be at least 100 μm. The inductance of the wire decreases as the wire becomes thicker. Therefore, when a thicker wire is used, the collet also becomes thicker, and the distance d further increases. When the distance d increases,
The increase in the pattern of the electrode 90b causes a drawback that the inductance increases.

Usually, the chip carrier 84 and the capacitor 8
The distance from 6 is 200 to 300 μm, and this produces an inductance of about 1 nanohenry, so 10
At GHz, the impedance is about 60 ohms. For this reason, the cutoff frequency of a semiconductor light receiving element such as a PIN photodiode is 10 G with only the power source impedance.
There was a problem of being limited to less than Hz.

Therefore, the present invention provides a semiconductor device mounted such that the distance between the electrode of the semiconductor element and the capacitor is shortened, and the impedance of the bias power supply of the semiconductor element requiring a DC bias at high frequencies is reduced. The purpose is to

[0010]

Means for Solving the Problems The above-mentioned problem is a grounded metal block, and a capacitor provided on the metal block and having a top surface electrode and a bottom surface electrode that are parallel to each other with a dielectric layer in between. A chip carrier installed on the capacitor, wherein first and second electrodes are formed on the upper surface and the lower surface of an insulating layer, respectively, and the first and second electrodes are connected by an electric path penetrating the insulating layer. And a semiconductor chip flip-chip bonded to the first electrode of the chip carrier.

Further, in the above semiconductor device, a plurality of the capacitors are installed, and the first and second electrodes of the chip carrier are divided into a plurality of portions corresponding to the plurality of capacitors. It is achieved by a semiconductor device characterized in that the plurality of divided first and second electrodes are separately connected by the plurality of electric paths.

Further, in the above semiconductor device, the upper surface electrode of the capacitor is divided into a plurality of pieces, and the first and second electrodes of the chip carrier correspond to the plurality of upper surface electrodes. A semiconductor device, wherein each of the semiconductor devices is divided into a plurality of parts, and the plurality of divided first and second electrodes are separately connected by the plurality of electric paths. Achieved by

Further, in the above semiconductor device, a step having a predetermined height is provided on the surface of the metal block, and the capacitor and the chip carrier are placed so as to overlap each other on the metal block below the step. The height of the output terminal electrode formed on the upper surface of the insulating layer of the chip carrier is set on the metal block in the upper step of the step, and is almost equal to the height of the wiring layer connected to the output terminal electrode by a wire. This is achieved by a semiconductor device characterized by equality.

[0014]

According to the present invention, since the relative positions of the capacitor and the chip carrier can be matched by adopting the method of mounting the chip carrier on the capacitor, the relative position of the capacitor and the chip carrier can be controlled. It is possible to eliminate the difficulty of contact and the restriction of proximity due to the protrusion of the flux at the time of bonding with the metal block, and to shorten the connection distance between the electrode of the semiconductor element and the capacitor.

Further, by using a current path having a desired thickness instead of the gold wire for the connection between the chip carrier and the capacitor, the connection inductance can be greatly reduced. Furthermore, as a result of eliminating the need for gold wire connections,
The limitation due to the thickness of the wire-bonding collet, which was one of the drawbacks of the conventional example, is released.

Therefore, it is possible to reduce the high-frequency impedance of the bias power supply of the semiconductor device which requires the DC bias.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A concrete description will be given below based on the illustrated embodiments. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a partial sectional view thereof, FIG. 3 is an equivalent circuit diagram of the semiconductor device of FIG. 1, and FIG. FIG. 4 is a perspective view of a chip carrier showing a judgment part and showing an internal structure.
FIG. 4B is a bottom view of the chip carrier of FIG.

The metal block 12 is grounded. Then, on the metal block 12, a size of 900 μm × 9
Two capacitors 14a having a thickness of 00 μm and a thickness of 200 μm,
14b is installed. These capacitors 14a,
14b are bottom electrodes 16a, 16 which are parallel to each other.
b and the top electrodes 18a, 18b are dielectric layers 20a, 20
It is formed sandwiching b. And the bottom electrodes 16a, 1
6b is adhered to the metal block 12 by using the flux AuSn.

Further, on the capacitors 14a and 14b,
A chip carrier 22 having a size of 400 μm × 400 μm and a thickness of 200 μm is installed. In the chip carrier 22, electrodes 26a and 26b are formed on the lower surface of the insulating layer 24, and electrodes 28a, 28b and 28c are formed on the upper surface thereof. Then, as shown in FIG. 4A, the electrode 26 a and the electrode 28 a pass through the insulating layer 14 at about 1
Through electrode 30 embedded in a through hole of 00 μmφ
a and electrode 2b and electrode 2 in the same manner.
8b is connected by a through electrode 30b embedded in a through hole of about 100 μmφ that penetrates the insulating layer 14.

The electrodes 26 on the lower surface of the chip carrier 22 are also provided.
As shown in FIG. 4B, a and 26b each have a size of 360 μm × 360 μm and are 50 μm apart from each other.
It is formed with an interval of m, and using the flux Sn,
The upper electrodes 18a and 18b of the capacitors 14a and 14b are overlaid and bonded. In addition, for example, two PIN photodiodes 32 are provided on the chip carrier 22.
200 μm size in which a and 32b are connected in series
A semiconductor light receiving element chip 34 such as a twin PIN photodiode having a thickness of 300 μm and a thickness of 100 μm is flip-chip bonded.

That is, the bonding bumps 36a and 36b of the semiconductor light receiving element chip 34 are adhered to the electrodes 28a and 28b on the upper surface of the chip carrier 22 by the flux AuSn, and the bonding bump 36c as an output terminal of the semiconductor light receiving element chip 34 is used. Chip carrier 22
It is adhered to the output terminal electrode 28c on the upper surface. Furthermore,
On the metal block 12, a ceramic substrate 38 with a wiring pattern is bonded by a flux AuSn adjacent to the capacitor 14a. Then, the feeding pattern 40 and the capacitor 1 on the ceramic substrate 38 with the wiring pattern
The upper electrode 18a of 4a is connected by a gold wire 42.

As described above, according to the first embodiment, since the two capacitors 14a and 14b, the chip carrier 22, and the semiconductor light receiving element chip 34 are mounted in this order on the metal block 12, the capacitor 14a is mounted. 1
4b and the chip carrier 22 can be matched in relative position, the bonding bumps 36a and 36b of the semiconductor light receiving element chip 34 and the capacitors 14a and 14b.
The connection distance with can be shortened.

Further, the PIN photodiodes 32a, 3
The bonding bumps 36a, 36b of 2b and the capacitors 14a, 14b are connected by the through electrodes 30a, 30b of about 100 μmφ penetrating the insulating layer 14 of the chip carrier 22 instead of the conventional gold wires of 20 μmφ. The connection inductance can be significantly reduced.

Therefore, the conventional mounting method has an inductance of about 1 nanohenry and thus an impedance of about 60 ohms at 10 GHz, whereas the inductance is reduced to 1/10 or less and the impedance at 10 GHz is reduced. It can be reduced to less than 5 ohms, and thus does not cause the cutoff frequency to be limited to less than 10 GHz.

The through electrodes 30a and 30b are the electrodes 2
It is desirable to provide the position near 8a and 28b in order to reduce the connection inductance. Next, the second aspect of the present invention
A semiconductor device according to this embodiment will be described with reference to FIG.
FIG. 5A is a plan view showing a semiconductor device according to the second embodiment, and FIG. 5B is a plan view of the capacitor. The same components as those of the semiconductor device shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the semiconductor light receiving element chip 34 is mounted on the two capacitors 14a and 14b via the chip carrier 22 in the first embodiment, whereas the same semiconductor light receiving element chip is mounted. Is mounted on one capacitor via a chip carrier. On the grounded metal block 12, the size 9
One capacitor 44 having a size of 00 μm × 900 μm and a thickness of 200 μm is installed. The capacitor 44 includes lower surface electrodes and upper surface electrodes 46a and 46 which are parallel to each other.
b is formed so as to sandwich the dielectric layer 48. That is, the lower surface electrode is formed on the entire bottom surface of the dielectric layer 48, while the upper surface electrode is divided into two upper surface electrodes 46a and 46b with a central interval of 100 to 200 μm. There is a feature of.

On the capacitor 44, the chip carrier 22 is installed as in the first embodiment. The two electrodes on the lower surface of the chip carrier 22 are the upper electrodes 46a, 4a of the capacitor 44.
6b are respectively laminated and adhered. Further, the semiconductor light receiving element chip 34 is flip-chip bonded to the electrodes 28a, 28b and the output terminal electrode 28c on the upper surface of the chip carrier 22 as in the first embodiment.

As described above, according to the second embodiment, one capacitor 44, the chip carrier 22, and the semiconductor light-receiving element chip 34 are sequentially mounted on the metal block 12 so as to be mounted in this order. The same effect as that of the embodiment can be obtained. Further, in the case of the first embodiment described above, the relative positioning of the two capacitors 14a and 14b requires precision, but such relative positioning itself is not necessary, and the capacitor mounting step is performed only once.
Bonding of the capacitor 44 onto the metal block 12 can be simplified, and therefore the reliability of the semiconductor light receiving element and the efficiency of the assembling work can be improved.

Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a plan view showing a semiconductor device according to the third embodiment. The same components as those of the semiconductor device shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, one semiconductor light-receiving element chip 34 is mounted on the two capacitors 14a and 14b via the chip carrier 22 in the first embodiment, while four capacitors are used. It is characterized in that one semiconductor light receiving element chip is mounted on the chip via a chip carrier.

On the metal block 12, four capacitors 50a, 50b, 50c and 50d are installed. These capacitors 50a, 50b, 50c and 50d are
The lower electrode and the upper electrode 52a, 5 which are parallel to each other.
2b, 52c and 52d are formed with the dielectric layer sandwiched therebetween. Also, the capacitors 50a, 50b, 50c, 50d
A chip carrier 54 is installed on the top. The electrodes on the lower surface of the insulating layer 55 of the chip carrier 54 are divided into four, and are laminated and adhered to the upper electrodes 52a, 52b, 52c, 52d of the capacitors 50a, 50b, 50c, 50d, respectively. Further, the electrodes on the upper surface of the insulating layer 55 of the chip carrier 54 are similarly electrodes 56a, 56b, 56.
It is divided into c and 56d. The lower and upper electrodes are connected to each other by through electrodes penetrating the insulating layer 55.

The electrodes 56 on the upper surface of the chip carrier 54 are also provided.
A semiconductor light-receiving element chip 58 provided with two twin PIN photodiodes is flip-chip bonded to a, 56b, 56c, 56d and the like. In this way, according to the third embodiment, the metal block 12 has four
By mounting the individual capacitors 50a, 50b, 50c, 50d, the chip carrier 54, and the semiconductor light receiving element chip 58 in this order, the semiconductor light receiving element chip 58 has a plurality of twin PIN photodiodes. Even with the light receiving element, the same effect as that of the first embodiment can be obtained.

Next, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 7A is a plan view showing a semiconductor device according to the fourth embodiment, and FIG. 7B is a plan view of the capacitor. The same components as those of the semiconductor device shown in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the third embodiment has one semiconductor light receiving element chip 58 in which a twin PIN photodiode is provided on the four capacitors 50a, 50b, 50c and 50d via a chip carrier 54. It is characterized in that the same one semiconductor light receiving element chip is mounted on one capacitor via the chip carrier, while being mounted.

One capacitor 60 is installed on the metal block 12. The capacitor 60 includes lower surface electrodes and upper surface electrodes 62a, 62 which are parallel to each other.
b, 62c, and 62d are formed so as to sandwich the dielectric layer 64. That is, the lower surface electrode is formed on the entire bottom surface of the dielectric layer 64, while the upper surface electrode has a cross shape of 100 to 20 in the center.
The upper surface electrodes 62a, 62b, 62 are spaced apart by 0 μm.
This embodiment is characterized in that it is divided into four parts c and 62d.

A chip carrier 54 is placed on the capacitor 60, as in the third embodiment. Then, the electrodes divided into four on the lower surface of the chip carrier 54 are the upper surface electrodes 62 a and 6 a of the capacitor 60.
2b, 62c and 62d are overlapped and adhered respectively. In addition, the electrodes 56a, 56 on the upper surface of the chip carrier 54
b, 56c, 56d, etc., as in the third embodiment,
The semiconductor light receiving element chip 58 is flip-chip bonded.

As described above, according to the fourth embodiment, one capacitor 60, the chip carrier 54, and the semiconductor light-receiving element chip 58 are mounted in this order on the metal block 12, so that the third block is mounted. The same effect as that of the embodiment can be obtained. Further, the four capacitors 50a, 50b, 50 required in the case of the third embodiment described above.
Since the relative positioning of c and 50d is not required and the capacitor mounting process is performed only once, the reliability of the semiconductor light receiving element and the efficiency of the assembling work can be improved.

Next, a semiconductor device according to the fifth embodiment of the present invention will be described with reference to FIG. FIG. 8A is a plan view showing a semiconductor device according to the fifth embodiment, and FIG. 8B is a sectional view thereof. The same components as those of the semiconductor device shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the capacitors 14a and 14b, the chip carrier 22, and the semiconductor light receiving element chip 34 are sequentially stacked and mounted on the flat metal block 12 in the first embodiment. A feature is that a step is provided, and the same capacitor, chip carrier, and semiconductor light-receiving element chip are sequentially stacked and mounted on the metal block below the step.

On the surface of the metal block 68, the capacitor 14
A step having a height of 200 μm, which is equivalent to the thickness of a and 14b, is provided. And the metal block 68 at the bottom of this step
Similar to the first embodiment, the two capacitors 14a and 14b, the chip carrier 22, and the semiconductor light-receiving element chip 34 are sequentially stacked and mounted on the top. Further, a ceramic substrate 70 with a wiring pattern is provided on the lower metal block 68 adjacent to the capacitors 14a and 14b on the step.
Are arranged. The power feeding patterns 72a, 72b on the ceramic substrate 70 with wiring patterns and the upper electrodes 18a, 18b of the capacitors 14a, 14b are connected by gold wires 74a, 74b, respectively.

Further, a ceramic substrate 76 with a microstrip line for propagating an RF signal of the semiconductor light receiving element chip 34 is arranged on the upper metal block 68 adjacent to the capacitors 14a and 14b on the step. .. The microstrip line pattern 78 on the ceramic substrate with microstrip line 76 and the output terminal electrode 28c on the upper surface of the chip carrier 22 are
It is connected by a gold wire 80.

As described above, according to the fifth embodiment, the capacitors 14a and 14b, the chip carrier 22, and the semiconductor light-receiving element chip 34 are mounted in this order on the metal block 68. The same effect as that of the example can be obtained. Further, a step having a height equivalent to the thickness of the capacitors 14a and 14b is provided on the surface of the metal block 68, and the capacitors 14a and 14b and the chip carrier 22 are installed on the metal block 68 below the step, The height of the output terminal electrode 28c on the upper surface of the chip carrier 22 is such that the microstrip line pattern 7 on the ceramic substrate with microstrip line 76 installed on the metal block 68 in the upper step of the step.
It is almost equal to the height of 8.

Therefore, the short gold wire 8 is provided between the output terminal electrode 28c and the microstrip line pattern 78.
Since wire bonding can be easily performed with 0,
The connection distance of the RF signal can be shortened, and deterioration of high frequency characteristics due to mounting can be prevented. That is, capacitor 1
As the chip carrier 22 and the semiconductor light receiving element chip 34 are mounted on the chips 4a and 14b in an overlapping manner, the height of the output terminal electrode 28c on the upper surface of the chip carrier 22 becomes high, which makes wire bonding difficult. Can be eliminated.

Further, since the capacitors 14a and 14b can be installed by using the step provided on the surface of the metal block 68 as a guide, the accuracy of relative positioning of the capacitors 14a and 14b can be easily improved.

[0042]

As described above, according to the present invention, a capacitor in which an upper surface electrode and a lower surface electrode which are parallel to each other with a dielectric layer sandwiched therebetween are formed on a grounded metal block, an upper surface of an insulating layer, and First and second electrodes are formed on the lower surface, respectively, and a chip carrier in which the first and second electrodes are connected by an electric path penetrating an insulating layer and a semiconductor chip are sequentially stacked and mounted. By
Since the distance between the electrode of the semiconductor element and the capacitor can be shortened, and the electric path through the insulating layer of the chip carrier can be used instead of the wire for connecting the chip carrier and the capacitor, the connection inductance can be reduced. Can be significantly reduced.

As a result, it is possible to reduce the high frequency impedance of the bias power supply of the semiconductor element that requires a DC bias, and it is possible to drive at a high frequency.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of the semiconductor device shown in FIG.

FIG. 3 is an equivalent circuit diagram of the semiconductor device shown in FIG.

FIG. 4 is a diagram for explaining a chip carrier of the semiconductor device shown in FIG.

FIG. 5 is a diagram for explaining a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a plan view showing a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a diagram for explaining a semiconductor device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram for explaining a semiconductor device according to a fifth embodiment of the present invention.

FIG. 9 is a plan view showing a conventional semiconductor device.

[Explanation of symbols]

12, 68, 82 ... Metal block 14a, 14b, 44, 50a, 50b, 50c, 50
d, 60, 86 ... Capacitors 16a, 16b, 92b ... Lower surface electrodes 18a, 18b, 46a, 46b, 52a, 52b, 5
2c, 52d, 62a, 62b, 62c, 62d, 92
a ... Top surface electrode 20a, 20b, 48, 64 ... Dielectric layer 22, 54, 84 ... Chip carrier 24, 88 ... Insulating layer 26a, 26b, 28a, 28b, 56a, 56b, 5
6c, 56d, 90a, 90b, 90c ... Electrode 28c ... Output terminal electrode 30a, 30b ... Through electrode 32a, 32b ... PIN photodiode 34, 58, 96 ... Semiconductor light receiving element chip 36a, 36b, 36c, 98a, 98b, 98c ... Bonding bumps 38 ... Ceramic substrate with wiring pattern 40 ... Feeding patterns 42, 74a, 74b, 80, 99 ... Gold wire 70 ... Ceramic substrate with wiring pattern 72a, 72b ... Feeding pattern 76 ... Ceramic substrate with microstrip line 78 ... Microstrip line pattern 90d ... Backside electrodes 94a, 94b ... Fusing agent of low melting point metal 99a ... Wire bonding position

Claims (4)

[Claims] 1. A grounded metal block, a capacitor provided on the metal block and having an upper surface electrode and a lower surface electrode that are parallel to each other with a dielectric layer interposed therebetween, and a capacitor installed on the capacitor and insulated. A chip carrier in which first and second electrodes are formed on the upper surface and the lower surface of the layer, respectively, and the first and second electrodes are connected by an electrical path penetrating the insulating layer; 1. A semiconductor device having a semiconductor chip flip-chip bonded to one electrode. 2. The semiconductor device according to claim 1, wherein a plurality of the capacitors are installed, and a plurality of the first and second electrodes of the chip carrier are provided corresponding to the plurality of capacitors. The semiconductor device according to claim 1, wherein the semiconductor device is divided into a plurality of parts, and the plurality of the plurality of divided first and second electrodes are separately connected by the plurality of electric paths. 3. The semiconductor device according to claim 1, wherein the upper surface electrode of the capacitor is divided into a plurality of pieces, and the first and second upper surfaces of the chip carrier are corresponding to the plurality of upper surface electrodes. Each of the electrodes is divided into a plurality of portions, and the plurality of divided first and second electrodes are separately connected by the plurality of electric paths. Semiconductor device. 4. The semiconductor device according to claim 1, wherein a step having a predetermined height is provided on the surface of the metal block, and the capacitor and the capacitor are provided on the metal block below the step. Chip carriers are installed in an overlapping manner, and the height of the output terminal electrode formed on the upper surface of the insulating layer of the chip carrier is installed on the metal block in the upper stage of the step, and the output terminal electrode and the wire A semiconductor device having a height substantially equal to that of a wiring layer to be connected.