JPH09260429A - Semiconductor element mounting board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent increase in size of an element and increase in manufacturing processes for a mounting board, and restrain inclination of a mounted element, by forming a protrusion for supporting a semiconductor element in contact, near a wiring pattern at a mounting position of the semiconductor element to be directly mounted on the board surface. SOLUTION: On lateral sides of electric wirings 106a, 106b on a semiconductor element mounting board 101 for mounting a semiconductor element 200 thereon, solder metals 103a-103d for supporting the semiconductor element which are not related to electrical and mechanical connection between the semiconductor element 200 and the board 101 are provided. By supporting the semiconductor element 200 by the solder metals 103a-103d, the semiconductor element 200 is prevented from being inclined and erroneously contacting the electric wiring. Thus, a function to prevent a short circuit due to inclination may be provided simultaneously with formation of the electric wiring and the solder metal on the board, simply by adding some patterns, without causing increase in cost due to increase in size of the semiconductor element or increase in board working processes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication technology field and an information transmission technology, which relates to a substrate on which a semiconductor element is mounted and which is electrically wired.

[0002]

2. Description of the Related Art In the field of communication technology and information transmission technology, the amount of data that must be transmitted is increasing with the spread of multimedia, and moreover, real-time transmission is required for moving image transmission. Therefore, the demand for high-speed transmission is increasing. In order to meet this, it is necessary to broaden the system bandwidth.

By the way, as the band of signals that can be handled is widened, the capacitance and the inductance of the circuit elements become factors that limit the band and become large. In recent years, in order to reduce the size and weight of the device, semiconductor elements such as active elements and logic elements are mostly used. However, since the semiconductor element also has the circuit chip accommodated in the package, the external terminal of the circuit chip and the package Since the bonding wire, which is a wiring that connects the and, is used inside, the inductance of the bonding wire suddenly emerges as an element for band limitation.

To cope with this, all electrodes or signal line terminals of the semiconductor element are directly formed on a specific surface of the semiconductor element chip, and these electrodes and signal line terminals are directly used as connection terminals for mounting. A mounting method using a flip chip, in which the bonding wire is not used for the semiconductor element chip itself, is effective by directly connecting it to the wiring of the board (element mounting board) by soldering, etc. Research and development is being carried out.

For example, when considering a semiconductor laser device and a photodiode, these have only an anode and a cathode as terminals, but when these are flip-chips, the semiconductor device has an anode within one plane. Both electrodes and cathode electrodes are formed, and these electrodes are directly used as terminals to be directly connected to the wiring of the mount substrate.

Usually, in a flip chip device, a flat substrate is prepared by growing several epitaxial layers on a semiconductor substrate, and the polarity is changed by diffusion, ion implantation or the like, and electrodes of different polarities are formed in the same plane. Form an area.

After that, a groove reaching the semiconductor substrate is dug to separate the regions. FIG. 8 shows the appearance of a back illuminated photodiode as an example of a general flip chip device. 8A is a plan view seen from the back side, and FIG. 8B is a side view showing a back-illuminated photodiode element which is a flip chip, and 1101 and 1102 are anodes of this element. Electrode or cathode electrode, 1103 is an epitaxial layer, 1104 is a region separation groove, and 1105 is a semiconductor substrate.

That is, in the flip-chip element of the photodiode, the anode electrode 11 is formed on the semiconductor substrate 1105 for playing the role of a supporting substrate and forming the element.
02 and the cathode electrode 1101 are formed, and the solder bumps or solder metal layers for electrical and mechanical connection are electrodes 1101, 1 of the mount substrate or flip chip element.
Formed on 102, or both. At the time of mounting, the electrodes of the flip chip device and the device connection electrodes on the mounting substrate are aligned with each other, and then the solder is melted to be fused and mounted.

Therefore, in the flip-chip element, each electrode region needs to be separated within the surface where the electrode is formed. In addition, for a two-terminal element such as a photodiode, it suffices to provide one anode electrode and one cathode electrode, but in that case, the size of the area of each solder portion for connection should be large. Depending on the balance, the flip chip element may tilt and a part of the flip chip element may contact the mount substrate, as shown in FIG.

That is, in FIG. 9, 1201 is a flip-chip element semiconductor substrate, 1202 and 1203 are anode or cathode electrodes of the flip-chip element, and 120.
4 is solder for connection, 1205 is a mount substrate, 1206
Is an electrode wiring formed on the mount substrate 1205.

The electrode wiring 1206 formed on the mount substrate 1205 and the anode and cathode electrodes 1202 and 1203 of the flip chip element are connected by solder 1204. Two electrodes, an anode electrode and a cathode electrode, are used to connect the flip chip element. In the case where only two electrodes are used, if the amount of the solder 1204 is unbalanced in the connection between the two electrodes, the flip chip element is tilted. Then, due to this inclination, the electrode wiring 1206 formed on the mount substrate 1205.
By contacting a part of the flip chip element,
In some cases, the electrodes may be short-circuited, the dielectric strength may be lowered, and the capacitance may be increased, resulting in deterioration of characteristics.

Therefore, as in the structure shown in FIG. 8, electrodes are formed at the four corners of the electrode formation surface on the flip chip element side, or wiring is formed on the mount substrate as in the structure shown in FIG. Alternatively, the flip-chip element mounted by forming a protrusion of a separate component serving as a support base that is separate and independent may be supported by the protrusion serving as the support base.

In FIG. 10, reference numeral 1301 denotes a mounting substrate, 1304 denotes wiring patterned on the mounting substrate 1301, and 1302 and 1303 denote the wiring 1.
Solder metal for electrical or mechanical connection with a flip chip element in 304, 1305 is a protrusion, and 1306 is an element mounting region portion.

Protrusion 1 serving as a support for the flip chip device
305 is formed in the edge region of the element mounting region portion 1306 and is electrically independent of the wiring 1304. Then, the protrusion 1305 is formed by processing the mount substrate 1301 or depositing a material, and even if the amount of solder is different at the electrode position and becomes unbalanced,
The flip chip element is supported by the protrusion 1305 so that it can be prevented from tilting.

However, if the structure is such that the electrodes are provided at the four corners of the flip-chip element, it may be necessary to form an electrode having an area larger than necessary in the flip-chip element, resulting in an increase in size of the element, and the mount substrate. In the case where the structure for providing the projections for supporting the flip chip element is provided in the above, it is necessary to process the projections on the mount substrate in a separate step, which causes a problem that the cost is increased due to the increase in the steps.

Although the case of the flip chip is described here, the connection electrode portion with the mount substrate, such as a back illuminated photodiode, an LED (light emitting diode) mounted by junction down, a laser diode, etc., is in the same plane. The same problem occurs in the mounting of the element which is separated from the other area in.

[0017]

As described above, when a semiconductor element having a structure such as a flip chip is mounted on a substrate, the electrodes, signal terminals, etc. formed on the element are directly soldered. Although it is connected to the wiring pattern of the mounting substrate, if the number of electrodes and signal terminals of the element is small, if there is a quantitative imbalance of solder depending on the position, the mounted element will tilt and the mounting If the peripheral portion of the element comes into contact with the wiring pattern of the substrate or the distance is too close, short circuit, insulation failure (decrease in withstand voltage), increase in capacitance, etc. are caused.

In order to prevent these, if measures are taken such as increasing the number of electrodes for electrical or mechanical connection provided on the semiconductor element at four corners of the connection surface of the element, the semiconductor element side will be provided. If the electrode area is formed more than necessary, the size of the device will be increased, and if a protrusion for supporting the device is provided on the mounting substrate side so that it is supported by this protrusion so as not to tilt, board manufacturing However, there is a problem that the cost is increased due to the increase of the process.

Therefore, in the case where an element such as a flip chip is directly mounted on a mounting substrate by soldering, etc., there is a mounting technique for preventing an increase in the size of the element and an increase in the manufacturing process of the mounting substrate. Development is hoped for.

An object of the present invention is to prevent an increase in the size of an element or an increase in the number of steps for manufacturing a mounting substrate when directly mounting an element such as a flip chip on a mounting substrate by soldering or the like. At the same time, it is another object of the present invention to provide a substrate for mounting a semiconductor element in which the tilt of the mounted element can be suppressed.

[0021]

In order to achieve the above object, the present invention is configured as follows. That is, in a semiconductor mounting substrate for connecting and mounting a semiconductor element having a connection terminal on the element surface by directly attaching the semiconductor element to the connection position on the wiring pattern of the substrate using the connection terminal, the direct attachment on the substrate surface is performed. A protrusion, such as a solder metal layer, which is in contact with and supports the semiconductor element is formed near the wiring pattern at the mounting position of the semiconductor element for use.

That is, when the semiconductor element for direct attachment is set at the mounting position of the semiconductor element, the protrusion such as the solder metal layer near the wiring pattern contacts and supports the semiconductor element. The protrusion of the solder metal layer or the like has a step higher than that of the wiring pattern. Therefore, when the semiconductor element is positioned in this state, even if the semiconductor element is tilted, it stops at the solder metal layer portion, and the wiring is further cut. Stay away from patterns. Therefore, in this state, the semiconductor element
If the terminal is directly attached to the connection position on the wiring pattern of the substrate, the peripheral portion of the semiconductor element does not come into contact with or come too close to the wiring pattern even if the semiconductor element is inclined.

As a semiconductor element for direct attachment, which has a connection terminal for direct attachment on the element surface, there is, for example, a flip chip element, and when the terminal is directly attached to the connection position on the wiring pattern of the substrate, Forming a solder metal layer having a step higher than the wiring pattern and supporting in contact with the semiconductor element at a mounting position of the semiconductor element for direct attachment on the surface of the semiconductor mounting substrate, in the vicinity of the wiring pattern, Since the semiconductor element in contact with the semiconductor element is prevented from coming closer to the wiring pattern, if the semiconductor element is directly attached to the connection position on the wiring pattern of the substrate in this state, the semiconductor element Even if it is tilted, its peripheral portion does not come into contact with or come too close to the wiring pattern.

At the connection position of the wiring pattern, which is connected to the terminal of the semiconductor element for direct attachment, on the surface of the semiconductor mounting substrate, a solder metal is usually placed to enable automatic soldering. Since the solder metal layer can be simultaneously formed in the step of mounting the solder metal, the metal layer can be formed without increasing the number of manufacturing steps. In addition, since the semiconductor element does not need to be specially modified, there is no fear of increasing the size of the semiconductor element.

Therefore, according to the present invention, when an element such as a flip chip is directly attached to a mounting substrate by soldering or the like, it is possible to prevent an increase in the size of the element and an increase in the number of steps for manufacturing the mounting substrate. At the same time, it is possible to provide a semiconductor element mounting substrate in which the tilt of the mounted element can be suppressed.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) In the present invention, in a semiconductor element mounting substrate on which a semiconductor element such as a flip chip is mounted, the element is mistakenly connected to the electrical wiring of the semiconductor element mounting substrate due to the inclination of the mounted semiconductor element. In order to prevent contact, aside from the electric wiring on the semiconductor element mounting substrate, there is no involvement in electrical and mechanical connection between the semiconductor element and the substrate, and for supporting the semiconductor element. The solder metal is provided so that the semiconductor element is supported by the solder metal so as to prevent the semiconductor element from accidentally coming into contact with the electric wiring due to the inclination of the semiconductor element. The details will be described below. .

FIG. 1 shows a first specific example of the present invention. FIG.
(A) is a side view of a mount substrate (element mounting substrate) 100 according to the present invention, and (b) is the mount substrate 100.
10 is a plan view of the mount substrate portion 101, which is a plate-like member made of a semiconductor material such as Si or an insulating material such as aluminum oxide. Further, the mount substrate portion 101 may have a structure in which an insulating film or the like is formed on the surface thereof. 1
Reference numerals 06a and 106b denote wiring patterns formed on the mount substrate 101, respectively.
On the a and 106b, the solder metal layers 104 and 10 corresponding to the electrode positions of the flip chip element to be mounted at the mount area 107 position of the flip chip element.
5 are formed.

These solder metal layers 104 and 105 are solder metals for electrical and mechanical connection, and may be formed as solder bumps. Mount substrate unit 101
Above, for avoiding the electrode position of the flip chip element to be mounted at the mounting area 107 position of the flip chip element, and for preventing contact for maintaining the posture corresponding to the four corner positions of the flip chip element to be mounted. Solder metal layers 103a, 103d are formed.

In this specific example, the contact preventing solder metal layers 103a, 103d are formed directly on the mount substrate portion 101, as shown in FIG. When the adhesiveness between the solder metal and the mount substrate is poor, for example, the same metal layer as the electrode may be formed as a base, and the solder metal may be formed on the same metal layer.

FIG. 2 shows an electrode pattern of a semiconductor element such as a flip chip mounted on the mount substrate 100 illustrated in FIG. In the figure, 200 is a semiconductor element, 201 is a substrate portion of the semiconductor element 200,
Reference numerals 202 and 203 denote electrodes for electrically and mechanically connecting to the mount substrate 100.
It is formed on the same plane of the substrate portion 201 of 0.

When mounting the semiconductor element 200 shown in FIG. 2 on the mount substrate 100 of FIG. 1, the semiconductor element 200 is set on the mount substrate 100 by a collet or the like. At this time, the mount substrate 100 of the semiconductor element 200 is mounted.
Depending on the condition of pressing against and the imbalance of the shape of the solder metal, the chip to be mounted (semiconductor element 200 to be mounted) may be inclined with respect to the mount substrate 100 as shown in FIG.

However, the tilted chip has a solder metal layer 103 for contact prevention formed on the mount substrate 100.
When it comes into contact with a to 103d, further inclination is suppressed.

At this time, the contact preventing solder metal layers 103a ...
Although 103d is in contact with the semiconductor element 200, since the electrode pattern for connection is not formed on the semiconductor element 200 side, the wettability with respect to the solder metal is extremely small.

Therefore, when the semiconductor element 200 is aligned and heated and then the collet or the like holding the semiconductor element 200 is released, as shown in FIG. 3B, the molten solder of the solder metal layers 103a to 103d is melted. Is repelled from the surface of the semiconductor element 200 by its surface tension.

As a result, in the semiconductor element 200, the wiring approaching end (in the example of FIG. 3A, the approaching end to the wiring 106b) is returned in the direction away from the wiring (the arrow direction in the figure), and the inclination is corrected. The semiconductor element 200 is prevented from coming into contact with the wiring (wiring 106b) which is close to the semiconductor element 200 when the semiconductor element 200 is in the inclined state.

Particularly, in this specific example, the wirings 106a, 10 are provided under the contact-prevention solder metal layers 103a-103d.
Since the metal 6b is not formed, the connection solder metal layers 104 and 105 are connected to the wirings 106a and 106b.
Therefore, when the solder is melted in the heating step, the surface tension of the molten solder causes the solder to be repelled from the surface of the semiconductor element 200, and then the semiconductor element 20.
The solder metal of the solder metal layers 103a and 103d is separated from 0.

Therefore, in the first specific example, the semiconductor element 2
When mounting No. 00, the self-alignment effect due to the surface tension of the connecting solder can also be expected. The effect of this separation is that the solder metal of the solder metal layers 103a and 103d is
If the semiconductor element 200 is formed at a position corresponding to a step lower portion of the semiconductor element 200, the size becomes larger. In that case, when the semiconductor element 200 is set at the mount region 107 position of the mount substrate 100 by the collet, the semiconductor element 200 20
The solder metal layers 103a, 103 are arranged so that the solder metal of the solder metal layers 103a, 103d contacts the semiconductor element 200 before the edge portions of 0 contact the wirings 106a, 106b.
It is necessary to design the raised height of the solder metal (d) (the height of the solder bump).

As described above, this specific example solves the problem by forming electrodes and solder regions for electrical and mechanical connection on the mount substrate and at the same time forming electrodes or solder patterns not involved in the connection. By forming electrodes or solder patterns that do not participate in the above connections that support the semiconductor element so that the semiconductor element does not accidentally touch the wiring due to tilting of the semiconductor element, special processing is performed on the element or substrate. This has the effect of preventing the size and cost of the element from increasing, and also preventing the wiring and element from coming into contact with each other by the electrode or solder pattern not involved in this connection when the semiconductor element is tilted.

Therefore, according to the present invention, when an element such as a flip chip is directly attached to a mounting substrate by soldering or the like, it is possible to prevent the size of the element from increasing and the number of steps for manufacturing the mounting substrate to increase. At the same time, it is possible to provide a semiconductor element mounting substrate in which the tilt of the mounted element can be suppressed.

(Second Specific Example) In the first specific example described above, the solder metal layers 103a, 103d for contact prevention on the mount substrate 101 are mounted on the mount substrate 101 as shown in FIG. It was formed directly on top. However, in order to match the height with the solder metal layers 104 and 105 for electrical connection as much as possible, in the same manner as the solder metal for electrical connection, the wiring metal is left in the lower layer and the metal pattern portion for height adjustment is used. It may be used as. This example will be described as a second specific example.

The height-adjusting metal pattern portion is the wiring 10
The metal film itself used for forming 6a and 106b can be used, and patterned wirings 106a and 10
6b is the one left after being patterned in a state of being electrically separated and divided. In this way, the solder metal layer 1
The lower layer of 03 may have a metal pattern formed simultaneously with the wirings 106a and 106b. These can be obtained without going through an extra step.

That is, in order to form the wirings 106a and 106b, a metal film for wiring is formed on the mount substrate portion 101, and this metal film is patterned to leave a necessary wiring pattern. At the time of the patterning, the metal film is left in the regions where the contact preventing solder metal layers 103a and 103d for maintaining the posture are to be formed. Then, the wiring 106
In the step of forming a, 106b and the connecting solder metal layers 104, 105, these contact preventing solder metal layers 1
03a, 103d, solder metal is also formed on the metal film left in the planned formation region, and the contact preventing solder metal layer 103a,
-10d is obtained.

In this way, in the process of forming the wirings 106a and 106b and the connecting solder metal layers 104 and 105, at the same time, a short circuit preventing (contact preventing) solder metal layer 103a is formed beside the wirings 106a and 106b. -10
3d can be formed.

In this case, the wirings 106a, 106
Since the connecting solder metal layers 104 and 105 of b and the contact preventing solder metal layers 103a and 103d have almost the same height, when the semiconductor element 200 is set on the mount substrate 100 by a collet or the like, Even if there is a pressing condition on the mount substrate 100 or the shape of the solder metal is unbalanced, there is almost no inclination of the chip to be mounted (the semiconductor element 200 to be mounted) with respect to the mount substrate 100.

Therefore, the periphery of the semiconductor element 200 is the wiring 1
No close proximity to or contact with 06a and 106b. (Third specific example) The size of the contact preventing solder metal layers 103a, 103d and the connecting solder metal layers 104, 105 is too small as compared with the size ratio of the mounted chip (the mounted semiconductor element 200). In such cases,
The pressing force at the time of mounting the semiconductor element 200 on the mount substrate 100 is concentrated as a point load on the solder metal layer corresponding portion, and depending on the degree of unbalance of the height of the solder metal layer, the concentration degree becomes stronger. However, there is a concern that the mounted semiconductor element 200 may be damaged.

Therefore, in order to increase the mechanical strength, the mount substrate 100 has solder metal layers 104 and 105 for electrical connection, as shown in FIG.
Electrically adjacent dummy electrodes 304, 305 having a relatively large area are further provided in the vicinity of the installation portion of
A solder metal layer is formed on the dummy electrodes 304 and 305. Further, as shown in FIG. 4B with respect to the configuration of FIG. 2, in the semiconductor element 200, the dummy electrodes 205, 205 are provided at positions facing the dummy electrodes 304, 305 in addition to the anode electrodes, the cathode electrodes 203, 203. 206 is further formed.

In this way, when mounting on the mount substrate 100, the connecting solder metal layers 104 and 105 of the mount substrate 100 and the anode electrodes and cathode electrodes 203 and 203 of the semiconductor element 200 face each other, and the dummy electrodes of the mount substrate 100 are arranged. 304 and 305 are semiconductor elements 2
The dummy electrodes 205 and 206 of No. 00 face each other, and the contact area increases. Therefore, the concentration of the load is reduced, and after the connection by solder, the connection area is large, so that the holding strength is increased and the mechanical strength is increased as a whole.

Further, the four corners of the semiconductor element 200 are in contact with the solder metal layers 103a, 103d for preventing contact, the inclination of the semiconductor element 200 is suppressed, and the peripheral edge of the semiconductor element 200 is connected to the wirings 106a, 106b of the mount substrate 100. It is possible to prevent contact with or too close to.

In particular, in this way, when the dummy electrodes are provided on both the semiconductor element and the mount substrate and the connection is made with the solder metal, the solder metal layers 103a, 103 for contact prevention are used.
It is sufficient that d is provided only on the mount substrate side, and the solder metal layer 1 for contact prevention is provided only on the mount substrate side.
03a, 103d have an effect of preventing a short circuit due to the inclination of the semiconductor element.

As described above, in the first to third specific examples, the contact preventing solder metal layers 103a to 103d are formed so as to be located at the four corners of the mount region 107, but one point is provided at each of the four corners. 2 of them without setting
The number of installation points can be reduced to three or three, and it is possible to effectively prevent the occurrence of a short circuit. An example thereof will be described below as a fourth specific example.

(Fourth Specific Example) In the first to third specific examples, the contact preventing solder metal layers 103a to 103d are formed so as to be located at the four corners of the mount region 107, but it is necessary. When the semiconductor element 200 is mounted on the mount area, the contact prevention solder metal layer is provided at a position where the semiconductor element 200 can be prevented from tilting and the peripheral edge of the semiconductor element 200 coming into contact with or coming too close to the wirings 106a and 106b. It doesn't have to be in each of the four corners.

Therefore, for example, as shown in FIG. 5A, two of the four corners in the mount area, especially the wiring 10
6a, 106b at positions where they do not want to contact, or as shown in FIG. 5B, at three points out of the four corners in the mount region, particularly at positions where they do not want to contact the wirings 106a, 106b, preventing contact as a support. Solder metal layer 103
-A, 103-b, 103-c are formed, and the peripheral portion of the semiconductor element 200 to be mounted has wirings 106a, 106b.
Try to support it so that it does not come near.

In this way, the chip to be mounted (semiconductor element 200 to be mounted) is mounted on the mount substrate 10.
0 for the wirings 106a and 106b, and the contact preventing solder metal layers 103-105.
a and 103-b or 103-a to 103-c, the contact preventing solder metal layers 103-a and 103-b or 103-a to 103 At the stage of collision with -c, further approach of the peripheral portion of the semiconductor device 200 is blocked.

Therefore, according to this embodiment, the number of points for forming the contact-prevention solder metal layer is small and the semiconductor element 20 is small.
The edge of 0 is too close to the wirings 106a and 106b,
The effect that no contact occurs can be obtained.

(Fifth Specific Example) As an application example, an application example to a communication optical semiconductor module will be described. In a communication optical semiconductor module for converting an electric signal to an optical signal and transmitting and receiving an optical signal by connecting to an optical transmission line, as shown in FIG. An optical element 500 (for example, a photodiode or a laser diode) is used. As shown in FIG. 7C, this optical element 500 has a mounting Si
A back-illuminated type (or back-side emission) having a structure in which a light receiving portion (or a light emitting portion (when the optical element 500 is a light emitting element)) 512 and electrode pads 514 and 615 connected to an anode electrode of the element are provided on the mounting surface side to the substrate 600. Type) element is used.

In the optical semiconductor module for communication, such an optical device 500 is mounted on a rectangular plate-shaped Si substrate 600 for mounting as shown in FIG.
An optical fiber 700 having a small diameter for guiding light between the two is attached to the mounting Si substrate 600 as a light guide path.

In order to mount the optical fiber 700 in a fixed position, a V-shaped groove 601 is formed in the Si substrate 600, and the optical fiber 700 is fixed here. In the case of a miniaturized optical semiconductor module for communication in order to reduce the size and space, the light receiving portion (or the light emitting portion (when the light emitting element is the light emitting element 500)) of the optical element 500 is on the same surface as the electrode formation surface. It is a composite module in which the millimeter-sized Philip-chip is formed, and, for example, an optical fiber 700 having a diameter of hair and this optical element 500 are combined. An extending V-shaped groove 601 is formed, an optical fiber 700 is attached in the V-shaped groove 601, and the other end of the V-shaped groove 601, that is, the closed end of the V-shaped groove 601 is formed on a slope, and this is mirror-finished. Finished to be a reflecting mirror, and the optical axis is bent 90 ° above the groove by this reflecting mirror, and the light receiving part (or light emitting part) is positioned on this optical axis. And thus, mounting the optical element 500 in the Si substrate 600 top mount.

Therefore, the optical element 500 should be mounted on the mounting Si substrate 600 so as to partially cover the V groove 601 such that the light receiving portion (or the light emitting portion) is located at the reflecting mirror facing portion of the V groove 601. become.

The details of the configuration will be described. In the flip-chip optical element 500 in this case, a light receiving portion (or a light emitting portion) is formed near the center of the rectangular element, as shown in FIG.
4, 515 are formed, and electrodes 514,
515 is mounted on the mounting Si substrate 600 by soldering.

The optical element 500, as shown in FIG.
An anode electrode 513 is formed so as to surround a light receiving portion (or a light emitting portion) 512 formed in the vicinity of the central position on the semiconductor substrate 511, and an electrode pad 514 is formed for electrical connection between the anode electrode 513 and the outside. The formed anode electrode 513 and the electrode pad 514 are electrically connected. A pair of mechanical connection electrodes 515 is formed on both sides of the electrode pad 514. Further, electrodes are formed on the entire back surface of the semiconductor substrate 511.

The optical element 500 is mounted on the mount substrate 600. Details of the mount substrate 600 are as shown in FIG. 7. FIG. 7A is a plan view of the mount substrate 600, and FIG. 7B is a sectional view taken along the line AA of FIG. In the figure, 601 is a V groove, 602 is a wire, 603 is a solder metal layer for mechanical connection, 605 is a wiring pattern for connecting to the back surface of the optical element 500 with a bonding wire, and 606 is provided at the tip of the wire 602. A solder metal layer for electrical connection, which is a portion used for electrical connection with the electrode 514, and 607 is a Si substrate portion.

The V-shaped groove is for holding the optical fiber, but the shape of the groove is not necessarily V-shaped, and may be a U-shaped or U-shaped groove. . As described above, one end of the groove is an open end and the other end is a closed end, and the closed end is mirror-finished to form a plane reflecting mirror 601a. The optical axis of the optical fiber is defined by the plane reflecting mirror 601a. Form a folding optical path. Plane reflector 6
When the optical element 500 is a photodiode, the optical element 500 is arranged on the optical path bent 90 ° by 01a with its light receiving portion (or light emitting portion) 512 aligned with the optical path. The light guided to the flat reflecting mirror 601a is reflected upward by the flat reflecting mirror surface and is guided to the optical element 500.

Reference numeral 604 denotes a solder metal layer for preventing contact,
The wirings 602 are formed on both sides of the wiring 602, and when the optical element 500 is tilted, the wiring 602 is in contact with the solder metal layer 604 to prevent further tilting. To prevent contact with. The contact preventing solder metal layer 604 is formed at the bottom or side wall of the depression 609 formed at the same time when the V groove 606 is formed on the mount substrate 600 during the forming process. That is, the V-groove 606 has a cross-sectional size of the order of several hundreds of microns and is formed by using the semiconductor integrated circuit manufacturing technique, but is formed simultaneously in the forming process. The depression 609 is formed so that the height of the solder metal layer when the contact-prevention solder metal layer 604 is formed can be adjusted according to the purpose, and the molten solder in the depression 609 is melted when the solder is melted. Optical element 500 that escapes into the recess
This is to keep it away from.

The solder metal layer 60 for contact prevention before melting
The height of 4 is set to be higher than that of the extraction electrode 602. Since the recess 609 is not a target subject to structural restrictions in the mount substrate 600, the depth thereof can be adjusted, that is, the depth can be set to an arbitrary depth. Therefore, the solder metal layer for connection and the solder metal layer for contact prevention can be formed. The step can be controlled, and the optical element 500, which is a semiconductor element, and the solder metal layer 604 can be controlled by the above-mentioned surface tension of the solder metal during melting.
The effect that the solder is separated can be more actively controlled, and the degree of freedom in design is increased.

Although various specific examples have been described above, in the present invention, a semiconductor element for direct attachment having a connection terminal for direct attachment on the element surface is directly connected to the connection position on the wiring pattern of the substrate. In a semiconductor mounting substrate to be attached and connected and mounted, a solder metal layer for supporting the semiconductor element in contact with the semiconductor element is formed near the wiring pattern at the mounting position of the semiconductor element for direct attachment on the substrate surface. Is.

As a semiconductor element for direct attachment having a connection terminal for direct attachment on the element surface, there is, for example, a flip chip, and when the terminal is directly attached to the connection position on the wiring pattern of the substrate, Of the mounting position of the semiconductor element for direct attachment on the surface of the semiconductor mounting substrate,
In the vicinity of the wiring pattern, a solder metal layer having a step higher than that of the wiring pattern and contacting and supporting the semiconductor element is formed, and the semiconductor element in contact with the solder metal layer is prevented from coming closer to the wiring pattern. Therefore, in this state, if the semiconductor element is directly attached to the connection position on the wiring pattern of the substrate by using the terminal, even if the semiconductor element is tilted, its peripheral edge is in contact with the wiring pattern or too close to the wiring pattern. Never.

At the connection position of the wiring pattern for connecting to the terminal of the semiconductor element for direct attachment on the surface of the semiconductor mounting substrate, a solder metal is usually placed on the surface of the semiconductor mounting substrate to enable automatic soldering. Since the solder metal layer can be simultaneously formed in the step of mounting the solder metal, the metal layer can be formed without increasing the number of manufacturing steps. In addition, since the semiconductor element does not need to be specially modified, there is no fear of increasing the size of the semiconductor element.

Therefore, according to the present invention, when an element such as a flip chip is directly attached to a mounting substrate by soldering or the like, it is possible to prevent the size of the element from increasing and the number of steps for manufacturing the mounting substrate to increase. At the same time, it is possible to obtain a semiconductor element mounting substrate capable of suppressing the tilt of the mounted element. It should be noted that the present invention is not limited to the above-mentioned examples, and can be implemented by being modified in various ways.

[0069]

As described above, according to the present invention, an electric wiring or a solder formed on a substrate can be formed by only adding a few patterns without causing an increase in cost due to an increase in the size of a semiconductor element or an increase in a substrate processing step. It is possible to provide a semiconductor element mounting substrate which has an effect that a semiconductor element mounting substrate having a function of preventing a short circuit due to an inclination can be formed at the same time when a metal is formed, and an inexpensive and highly reliable semiconductor module can be manufactured.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the present invention, showing a first specific example of the present invention.

FIG. 2 is a diagram for explaining the present invention and is an explanatory diagram of an element mounted in the first specific example.

FIG. 3 is a diagram for explaining the present invention and a diagram for explaining the effect of the first specific example.

FIG. 4 is a diagram for explaining the present invention, showing a third specific example of the present invention.

FIG. 5 is a diagram for explaining the present invention and showing a fourth specific example of the present invention.

FIG. 6 is a diagram for explaining the present invention and showing a fifth specific example of the present invention.

FIG. 7 is a diagram for explaining the present invention and a diagram for explaining a fifth specific example of the present invention.

FIG. 8 is a diagram for explaining an overview of a general flip chip.

FIG. 9 is a diagram for explaining a conventional example.

FIG. 10 is a diagram for explaining another conventional example.

[Explanation of symbols]

 Reference numeral 101 ... Mount substrate 103-a, 103-d ... Contact prevention solder metal layer 104, 105 ... Electrical and mechanical connection solder metal 106, 106a, 106b, 602 ... Wiring 107 ... Semiconductor element mounting region 200 ... Semiconductor Element 500 ... Optical element 512 ... Light receiving part (or light emitting part) 600 ... Mount substrate 601 ... V groove 601a ... Planar reflecting mirror 604 ... Contact-prevention solder metal layer 609 ... Dimple

Claims (2)

[Claims] 1. A semiconductor mounting board for connecting and mounting a semiconductor element having a connection terminal on the element surface by directly attaching the semiconductor element to the connection position on the wiring pattern of the board using the connection terminal, A substrate for mounting a semiconductor element, characterized in that, in the vicinity of the wiring pattern for direct attachment, a projection having a step higher than the wiring pattern and contacting and supporting the semiconductor element is formed. 2. The substrate for mounting a semiconductor element according to claim 1, wherein the protrusion is formed by forming a concave portion on the substrate and positioning the concave portion in the concave portion.