JPH05145011A - Manufacture of composite semiconductor device - Google Patents
Manufacture of composite semiconductor deviceInfo
- Publication number
- JPH05145011A JPH05145011A JP3360849A JP36084991A JPH05145011A JP H05145011 A JPH05145011 A JP H05145011A JP 3360849 A JP3360849 A JP 3360849A JP 36084991 A JP36084991 A JP 36084991A JP H05145011 A JPH05145011 A JP H05145011A
- Authority
- JP
- Japan
- Prior art keywords
- conductor plate
- cream solder
- plate
- semiconductor device
- inner conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、複数回に亘る半田付け
工程を最小限に省略して製造能率の向上化を図った複合
半導体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a composite semiconductor device in which a plurality of soldering steps are omitted to a minimum and manufacturing efficiency is improved.
【０００２】[0002]
【従来の技術】この種の複合半導体装置の従来の構造を
図７及び図８に示す。図７は複合半導体装置の平面図、
図８は絶縁ケースを外した状態の複合半導体装置の正面
図である。これらの図において、複合半導体装置１は、
その底部に放熱板２を有し、この放熱板２上に、両面に
金属層を設けたセラミック製の絶縁板３が載置されてい
る。この絶縁板３上には、所定の形状のアノード側の外
部導出導体板４及びアノード側の内部導体板５が両者の
先端部を重ね合わせて重合部を形成し、それらの外部導
出導体板４及び内部導体板５上には、それぞれチップ組
立体６が載置されている。このチップ組立体６は、導体
板７上に複数の半導体チップ８、温度補償板９及び内部
リード１０がそれぞれ高温半田で固着された構成となっ
ている。上記の内部リード１０の上端部にはカソード側
の内部導体板１１及びカソード側の外部導出導体板１２
がそれぞれ挿入・半田固着されている。なお、上記の外
部導出導体板４，１２の一端は絶縁ケース１３外へ導出
され、外部端子を構成している。2. Description of the Related Art A conventional structure of a composite semiconductor device of this type is shown in FIGS. FIG. 7 is a plan view of the composite semiconductor device,
FIG. 8 is a front view of the composite semiconductor device with the insulating case removed. In these figures, the composite semiconductor device 1 is
A heat radiating plate 2 is provided on the bottom thereof, and a ceramic insulating plate 3 having metal layers provided on both surfaces is placed on the heat radiating plate 2. On this insulating plate 3, an anode-side outer lead-out conductor plate 4 and an anode-side inner conductor plate 5 having a predetermined shape are superposed on each other to form a superposed portion, and these outer lead-out conductor plate 4 is formed. The chip assemblies 6 are mounted on the inner conductor plate 5 and the inner conductor plate 5, respectively. The chip assembly 6 has a structure in which a plurality of semiconductor chips 8, a temperature compensating plate 9 and internal leads 10 are fixed on a conductor plate 7 by high temperature solder. At the upper end of the inner lead 10, the cathode-side inner conductor plate 11 and the cathode-side outer lead-out conductor plate 12 are provided.
Are respectively inserted and soldered. In addition, one end of each of the external lead-out conductor plates 4 and 12 is led out of the insulating case 13 to form an external terminal.
【０００３】次に、上記の複合半導体装置の製造工程を
図９の組立図及び図１０のブロック図を参照して説明す
る。 （１）放熱板２のａ部及び絶縁板３のｂ部にそれぞれク
リーム半田を塗布する（イ工程）。 （２）絶縁板３を放熱板２上に重ねる（ロ工程）。 （３）外部導出導体板４を絶縁板３上に重ねる（ハ工
程）。 （４）外部導出導体板４の上面ｃ部及びｄ部にクリーム
半田を塗布する（ニ工程）。 （５）内部導体板５を絶縁板３上に重ねる（ホ工程）。 （６）内部導体板５の上面ｅ部にクリーム半田を塗布す
る（ヘ工程）。 （７）外部導出導体板４のｃ部及び内部導体板５のｅ部
に、それぞれチップ組立体６を載置する（ト工程）。 （８）チップ組立体６の内部リード１０の先端部に外部
導出導体板１２を挿通する（チ工程）。 （９）外部導出導体板１２の上面ｆ部にクリーム半田を
塗布する（リ工程）。 （１０）内部導体板１１をチップ組立体６の内部リード
１０に挿通する（ヌ工程）。 （１１）外部導出導体板１２及び内部導体板１１の内部
リード１０の挿通部にそれぞれクリーム半田を塗布する
（ル工程）。 （１２）全体を加熱し、クリーム半田を塗布した箇所を
半田固着させる（オ工程）。 上記の各工程の作業は、一直線状に配置したステージ上
で行なわれている。Next, a manufacturing process of the above composite semiconductor device will be described with reference to the assembly view of FIG. 9 and the block diagram of FIG. (1) Apply cream solder to each of a portion of the heat radiating plate 2 and b portion of the insulating plate 3 (step a). (2) The insulating plate 3 is overlaid on the heat dissipation plate 2 (step B). (3) The externally derived conductor plate 4 is placed on the insulating plate 3 (step C). (4) Apply cream solder to the upper surface c and d of the external lead-out conductor plate 4 (step D). (5) Overlay the inner conductor plate 5 on the insulating plate 3 (e step). (6) Apply cream solder to the upper surface e of the inner conductor plate 5 (step F). (7) The chip assemblies 6 are placed on the c portion of the external lead-out conductor plate 4 and the e portion of the internal conductor plate 5, respectively (step G). (8) The external lead-out conductor plate 12 is inserted into the tips of the internal leads 10 of the chip assembly 6 (H step). (9) Apply cream solder to the upper surface f portion of the external lead-out conductor plate 12 (re-process). (10) The internal conductor plate 11 is inserted into the internal lead 10 of the chip assembly 6 (step S). (11) Cream solder is applied to the external lead-out conductor plate 12 and the insertion parts of the inner leads 10 of the inner conductor plate 11 (step (c)). (12) The whole is heated to fix the solder to the portion where the cream solder is applied (e step). The work of each of the above steps is performed on a stage arranged in a straight line.
【０００４】[0004]
【発明が解決しようとする課題】ところで、上記従来の
複合半導体装置の製造方法では、次のような解決すべき
課題があった。すなわち、上記の製造工程中、クリーム
半田の塗布工程を抽出して見ると、イ工程、ニ工程、ヘ
工程、リ工程、及びル工程の合計５工程に及んでいる。
これらの工程は、直線状に配置された各ステージで実施
されるため、全体として組立ラインが長くなり、かつ、
クリーム半田の塗布装置も５台必要とし、設備費を高く
し、延いては複合半導体装置の製造原価を高くする欠点
を有していた。By the way, the above-mentioned conventional method for manufacturing a composite semiconductor device has the following problems to be solved. That is, in the above manufacturing process, when the cream solder applying process is extracted and viewed, it includes a total of five processes including the a process, the d process, the f process, the re process, and the le process.
Since these steps are performed in each stage arranged in a straight line, the assembly line becomes long as a whole, and
Five solder paste applicators were required, which had the drawback of increasing equipment costs and, in turn, increasing the manufacturing cost of the composite semiconductor device.
【０００５】[0005]
【発明の目的】本発明は、上記のような課題を解決する
ためになされたもので、クリーム半田の塗布ステージを
少なくし、全体の組立ラインを短くするとともに、クリ
ーム半田の塗布装置も最小限に留め、製造コストの低滅
を図った複合半導体装置の製造方法を提供することを目
的とするものである。SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and reduces the number of cream solder application stages, shortens the entire assembly line, and minimizes the cream solder application apparatus. In other words, it is an object of the present invention to provide a method for manufacturing a composite semiconductor device, which is capable of reducing the manufacturing cost.
【０００６】[0006]
【問題点を解決するための手段】本発明の複合半導体装
置の製造方法は、放熱板上に、絶縁板を介して一方の極
性側の外部導出導体板、一方の極性側の内部導体板及び
半導体チップを含むチップ組立体、他方の極性側の外部
導出導体板及び他方の極性側の内部導体板が載置され、
それら外部導出導体板と前記内部導体板との重合部およ
び前記チップ組立体の内部リードが挿通される他方の極
性側の外部導出導体板及び他方の極性側の内部導体板の
挿通部にクリーム半田を塗布して加熱し、上記各部材の
重合部及び前記内部リードの挿通部を半田固着させる複
合半導体装置の製造方法において、上記各部材の重合部
の少なくとも１箇所以上の表面側に位置する部材に透孔
を設け、この透孔にクリーム半田を塗布して加熱し、該
重合部を半田固着させることを特徴とするものである。According to the method of manufacturing a composite semiconductor device of the present invention, an external lead-out conductor plate on one polarity side, an internal conductor plate on one polarity side, and an insulating plate are provided on a heat dissipation plate. A chip assembly including a semiconductor chip, an outer lead conductor plate on the other polarity side and an inner conductor plate on the other polarity side are mounted,
Cream solder on the insertion part of the outer lead-out conductor plate on the other polarity side and the inner lead-out plate on the other polarity side through which the overlapping portion of the outer lead-out conductor plate and the inner conductor plate and the inner lead of the chip assembly are inserted. In the method for manufacturing a composite semiconductor device, wherein the overlapping portion of each member and the insertion portion of the internal lead are soldered and fixed, a member positioned on at least one surface side of the overlapping portion of each member. It is characterized in that a through hole is provided in the through hole and cream solder is applied to the through hole and heated to fix the polymerized portion with solder.
【０００７】[0007]
【作用】本発明の複合半導体装置の製造方法は、各部材
の重合部の一方にクリーム半田塗布用の透孔を設けたの
で、該透孔を利用してクリーム半田を塗布し、加熱する
ことにより溶融半田が毛細管現象で該重合部の隙間に入
り、両部材を半田固着させることができる。このため、
部材重合部の表面のすべてにクリーム半田を塗布する必
要がなくなり、クリーム半田塗布工程の省略により全体
の組立ラインが短縮され、また、クリーム半田の塗布装
置を最小限に留めることができ、設備費も低減され、複
合半導体装置の製造原価を低減することができる。In the method of manufacturing the composite semiconductor device of the present invention, the through hole for applying the cream solder is provided in one of the overlapping portions of each member. Therefore, the cream solder is applied and heated through the through hole. As a result, the molten solder enters the gap of the polymerized portion due to the capillary phenomenon, and the two members can be fixed by soldering. For this reason,
There is no need to apply cream solder to the entire surface of the overlapping parts of the member, the entire assembly line can be shortened by omitting the cream solder application process, and the equipment for applying cream solder can be kept to a minimum. It is also possible to reduce the manufacturing cost of the composite semiconductor device.
【０００８】[0008]
【実施例】以下に、本発明の実施例を図面に基づいて詳
細に説明する。図１は、本発明の製造方法により製造さ
れた複合半導体装置の第１実施例を示す平面図、図２は
上記複合半導体装置の絶縁ケースを外した状態の正面図
である。これらの図において、従来の複合半導体装置と
同一構成部品には同一符号が付してある。本発明の複合
半導体装置１が従来の複合半導体装置１と異なる点は、
アノード側の内部導体板５とカソード側の内部導体板１
１の一方の先端部にそれぞれ半田塗布用の透孔５ａ，１
１ａを設けたことである。これらの半田塗布用の透孔５
ａ，１１ａを設けることにより以下のように、クリーム
半田の塗布工程を１工程省略することができる。この製
造工程を先の図１０、図１１及び図３を参照して説明す
る。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a plan view showing a first embodiment of a composite semiconductor device manufactured by the manufacturing method of the present invention, and FIG. 2 is a front view of the composite semiconductor device with an insulating case removed. In these figures, the same components as those of the conventional composite semiconductor device are designated by the same reference numerals. The difference between the composite semiconductor device 1 of the present invention and the conventional composite semiconductor device 1 is that
Internal conductor plate 5 on the anode side and internal conductor plate 1 on the cathode side
Through holes 5a, 1 for solder application respectively
1a is provided. Through holes 5 for solder application
By providing a and 11a, one step of applying the cream solder can be omitted as follows. This manufacturing process will be described with reference to FIGS. 10, 11 and 3 described above.
【０００９】（１）放熱板２のａ部及び絶縁板３のｂ部
にそれぞれクリーム半田を塗布する（イ工程）。 （２）絶縁板３を放熱板２上に重ねる（ロ工程）。 （３）外部導出導体板４を絶縁板３上に重ねる（ハ工
程）。 （４）外部導出導体板４の上面ｃ部のみにクリーム半田
を塗布する（ニ工程）。 （ｄ部にはクリーム半田を塗布しない。） （５）内部導体板５を絶縁板３上に重ねる（ホ工程）。 （６）内部導体板５の上面ｅ部にクリーム半田を塗布す
る（ヘ工程）。 （７）外部導出導体板４のｃ部及び内部導体板５のｅ部
に、それぞれチップ組立体６を載置する（ト工程）。 （８）チップ組立体６の内部リード１０の先端部に外部
導出導体板１２を挿通する（チ工程）。 （９）内部導体板１１をチップ組立体６の内部リード１
０に挿通する（ヌ工程）。 （１０）外部導出導体板１２及び内部導体板１１の内部
リード１０の挿通部と、アノード側の内部導体板５の透
孔５ａ及びカソード側の内部導体板１１の透孔１１ａに
それぞれクリーム半田を塗布する（ル工程）。 （１１）全体を加熱し、各クリーム半田の塗布箇所部を
半田固着させる（オ工程）。(1) Applying cream solder to the a portion of the heat radiating plate 2 and the b portion of the insulating plate 3 (step a). (2) The insulating plate 3 is overlaid on the heat dissipation plate 2 (step B). (3) The externally derived conductor plate 4 is placed on the insulating plate 3 (step C). (4) Applying cream solder only to the upper surface c portion of the external lead-out conductor plate 4 (d process). (No cream solder is applied to the d portion.) (5) The inner conductor plate 5 is overlaid on the insulating plate 3 (e process). (6) Apply cream solder to the upper surface e of the inner conductor plate 5 (step F). (7) The chip assemblies 6 are placed on the c portion of the external lead-out conductor plate 4 and the e portion of the inner conductor plate 5, respectively (step G). (8) The external lead-out conductor plate 12 is inserted into the tips of the internal leads 10 of the chip assembly 6 (H step). (9) The internal conductor plate 11 is connected to the internal lead 1 of the chip assembly 6.
Insert into 0 (step N). (10) Apply cream solder to the insertion portions of the internal leads 10 of the external lead-out conductor plate 12 and the internal conductor plate 11, the through hole 5a of the anode-side internal conductor plate 5 and the through-hole 11a of the cathode-side internal conductor plate 11, respectively. Apply (le process). (11) The whole is heated to fix the application points of each cream solder by soldering (e step).
【００１０】すなわち、上記のル工程において、透孔５
ａ，１１ａを利用してクリーム半田を塗布するため、外
部導体板４（アノード側）先端部のｄ部へのクリーム半
田の塗布、外部導出導体板１２（カソード側）のｆ部へ
のクリーム半田の塗布が不要となり、従来必要としてい
たリ工程が不要となる。このため、１工程省略すること
が可能となり、全体の組立ラインが短縮される。また、
クリーム半田の塗布装置を１台省くことができ、設備費
の低減により上記複合半導体装置の製造原価を低減する
ことができる。次に、第２実施例を図４、図５及び図６
を参照して説明する。図４は第２実施例による複合半導
体装置の平面図、図５は、その絶縁ケースを外した状態
の正面図、図６はその組立図である。この第２実施例で
は、アノード側の内部導体板５とカソード側の内部導体
板１１の一方の先端部にそれぞれ半田塗布用の透孔５
ａ，１１ａを設けた第１実施例に加えて、チップ組立体
６の導体板７の中央部に透孔７ａを、上記の内部導体板
１１の内部リード１０の挿通孔が設けられている広面積
部に透孔１１ｂを、カソード側の外部導出導体板１２の
内部リード１０の挿通孔が設けられている下端部に透孔
１２ａを、それぞれ設けたことである。これらの透孔７
ａ，１１ｂ，１２ａを設けた複合半導体装置の製造工程
を、図１０及び図１１を参照して説明すれば次のように
なる。That is, in the above process, the through hole 5
Since cream solder is applied using a and 11a, the cream solder is applied to the d portion at the tip of the outer conductor plate 4 (anode side), and the cream solder is applied to the f portion of the outer lead conductor plate 12 (cathode side). Is unnecessary, and the re-process that was necessary in the past is no longer necessary. Therefore, one process can be omitted, and the entire assembly line can be shortened. Also,
One cream solder coating device can be omitted, and the manufacturing cost of the composite semiconductor device can be reduced by reducing the facility cost. Next, a second embodiment will be described with reference to FIGS.
Will be described. FIG. 4 is a plan view of the composite semiconductor device according to the second embodiment, FIG. 5 is a front view with the insulating case removed, and FIG. 6 is an assembly view thereof. In the second embodiment, through holes 5 for solder application are respectively formed at one end of the internal conductor plate 5 on the anode side and the internal conductor plate 11 on the cathode side.
In addition to the first embodiment in which a and 11a are provided, a through hole 7a is formed in the central portion of the conductor plate 7 of the chip assembly 6, and an insertion hole for the inner lead 10 of the inner conductor plate 11 is provided. That is, the through hole 11b is provided in the area portion, and the through hole 12a is provided in the lower end portion of the cathode side outer lead-out conductor plate 12 where the insertion hole for the inner lead 10 is provided. These through holes 7
The manufacturing process of the composite semiconductor device provided with a, 11b, and 12a will be described below with reference to FIGS.
【００１１】（１）放熱板２のａ部及び絶縁板３のｂ部
にそれぞれクリーム半田を塗布する（イ工程）。 （２）絶縁板３を放熱板２上に重ねる（ロ工程）。 （３）外部導出導体板４を絶縁板３上に重ねる（ハ工
程）。 （４）内部導体板５を絶縁板３上に重ねる（ホ工程）。 （５）外部導出導体板４のｃ部及び内部導体板５のｅ部
に、それぞれチップ組立体６を載置する（ト工程）。 （６）チップ組立体６の内部リード１０の先端部に外部
導出導体板１２を挿通する（チ工程）。 （７）内部導体板１１をチップ組立体６の内部リード１
０に挿通する（ヌ工程）。 （８）外部導出導体板１２及び内部導体板１１の内部リ
ード１０の挿通部と、アノード側の内部導体板５の透孔
５ａ及びカソード側の内部導体板１１の透孔１１ａにそ
れぞれクリーム半田を塗布する。さらに、上記内部導体
板１１の透孔１１ｂ及び上記外部導出導体板１２の透孔
１２ａにクリーム半田を塗布する（ル工程）。 （９）全体を加熱し、各クリーム半田の塗布部を半田固
着させる（オ工程）。(1) Cream solder is applied to the a portion of the heat radiating plate 2 and the b portion of the insulating plate 3 (step a). (2) The insulating plate 3 is overlaid on the heat dissipation plate 2 (step B). (3) The externally derived conductor plate 4 is placed on the insulating plate 3 (step C). (4) Overlay the inner conductor plate 5 on the insulating plate 3 (e step). (5) The chip assembly 6 is placed on each of the c portion of the outer lead-out conductor plate 4 and the e portion of the inner conductor plate 5 (step G). (6) The external lead-out conductor plate 12 is inserted into the tips of the internal leads 10 of the chip assembly 6 (H step). (7) The internal conductor plate 11 is connected to the internal lead 1 of the chip assembly 6.
Insert into 0 (step N). (8) Cream solder is inserted into the external lead-out conductor plate 12 and the insertion part of the inner lead 10 of the inner conductor plate 11, through hole 5a of the inner conductor plate 5 on the anode side and through hole 11a of the inner conductor plate 11 on the cathode side, respectively. Apply. Further, cream solder is applied to the through holes 11b of the internal conductor plate 11 and the through holes 12a of the external lead-out conductor plate 12 (step C). (9) The whole is heated so that the cream solder application parts are fixed by soldering (e step).
【００１２】上記第２実施例によれば、外部導出導体板
４の上面ｃ部にクリーム半田を塗布するニ工程、内部導
体板５の上面ｅ部にクリーム半田を塗布するヘ工程及び
外部導出導体板１２の上面ｆ部にクリーム半田を塗布す
るリ工程の合計３工程が省略でき、第１実施例に比較し
てさらに全体の組立ラインが短縮される。また、クリー
ム半田の塗布装置を３台省くことができ、設備費も低減
され、複合半導体装置の製造原価を一層低減することが
できる。なお、上記の第２実施例の場合、チップ組立体
６の導体板７の裏面側、あるいは透孔７ａに対向する外
部導体板４及び内部導体板５の表面側に、適宜に溝を設
けて溶融半田が流れ易くするようにしても良い。上記の
実施例では、ダイオード構造の複合半導体装置を例にし
て説明したが、勿論これに限定されることなく、他の半
導体装置にも容易に適用することができる。According to the second embodiment, the step of applying cream solder to the upper surface portion c of the outer lead conductor plate 4, the step of applying cream solder to the upper surface portion e of the inner conductor plate 5, and the outer lead conductor. It is possible to omit a total of three steps of applying the cream solder to the upper surface f of the plate 12 in total, and further shortening the entire assembly line as compared with the first embodiment. Further, three cream solder applicators can be omitted, the facility cost can be reduced, and the manufacturing cost of the composite semiconductor device can be further reduced. In the case of the second embodiment described above, grooves are appropriately provided on the back surface side of the conductor plate 7 of the chip assembly 6 or on the front surface side of the outer conductor plate 4 and the inner conductor plate 5 facing the through holes 7a. The molten solder may be made to flow easily. In the above-mentioned embodiment, the diode-structured composite semiconductor device has been described as an example, but the present invention is not limited to this and can be easily applied to other semiconductor devices.
【００１３】[0013]
【発明の効果】以上のように、本発明によれば、各部材
の重合部の一方にクリーム半田塗布用の透孔を設けたの
で、該透孔を利用してクリーム半田を塗布し、加熱する
ことにより溶融半田が毛細管現象で該重合部の隙間に入
り、両部材を半田固着させることができる。このため、
部材重合部の表面のすべてにクリーム半田を塗布する必
要がなくなり、かかる塗布工程の省略により全体の組立
ラインが短縮され、また、クリーム半田の塗布装置を最
小限に留めることができ、設備費も低減され、複合半導
体装置の製造原価を低減することができるなどの効果が
ある。As described above, according to the present invention, since the through hole for applying cream solder is provided in one of the overlapping portions of each member, the cream solder is applied using the through hole and the heating is performed. By doing so, the molten solder enters the gap of the polymerized portion due to the capillary phenomenon, and both members can be fixed by soldering. For this reason,
It is not necessary to apply cream solder to the entire surface of the overlapping parts of the member, the entire assembly line can be shortened by omitting the application process, and the cream solder application device can be minimized, and the equipment cost is also reduced. Therefore, there is an effect that the manufacturing cost of the composite semiconductor device can be reduced.
【図１】本発明の第１実施例によって製造された複合半
導体装置の平面図である。FIG. 1 is a plan view of a composite semiconductor device manufactured according to a first embodiment of the present invention.
【図２】絶縁ケースを外した状態を示す上記第１実施例
における複合半導体装置の正面図である。FIG. 2 is a front view of the composite semiconductor device in the first embodiment, showing a state in which an insulating case is removed.
【図３】上記第１実施例における複合半導体装置の組立
図である。FIG. 3 is an assembly diagram of the composite semiconductor device in the first embodiment.
【図４】本発明の第２実施例によって製造された複合半
導体装置の平面図である。FIG. 4 is a plan view of a composite semiconductor device manufactured according to a second embodiment of the present invention.
【図５】絶縁ケースを外した状態を示す上記第２実施例
における複合半導体装置の正面図である。FIG. 5 is a front view of the composite semiconductor device according to the second embodiment with the insulating case removed.
【図６】上記第２実施例における複合半導体装置の組立
図である。FIG. 6 is an assembly diagram of the composite semiconductor device in the second embodiment.
【図７】従来の製造方法によって製造された複合半導体
装置の平面図である。FIG. 7 is a plan view of a composite semiconductor device manufactured by a conventional manufacturing method.
【図８】絶縁ケースを外した状態を示す上記従来方法に
おける複合半導体装置の正面図である。FIG. 8 is a front view of the composite semiconductor device in the conventional method, showing a state in which an insulating case is removed.
【図９】上記従来方法における複合半導体装置の組立図
である。FIG. 9 is an assembly diagram of a composite semiconductor device in the conventional method.
【図１０】本発明及び従来の複合半導体装置の製造方法
における（イ）ないし（ヘ）までの製造工程を示すブロ
ック図である。FIG. 10 is a block diagram showing manufacturing steps (a) to (f) in the manufacturing method of the present invention and the conventional composite semiconductor device.
【図１１】本発明及び従来の複合半導体装置の製造方法
における（ト）ないし（オ）までの製造工程を示すブロ
ック図である。FIG. 11 is a block diagram showing manufacturing steps (G) to (G) in the method of manufacturing a composite semiconductor device according to the present invention and the related art.
１ 複合半導体装置 ２ 放熱板 ３ 絶縁板 ４ 外部導出導体板（アノード側） ５ 内部導体板（アノード側） ６ 半導体チップ組立体 ７ 導体板 ８ 半導体チップ ９ 温度補償板 １０ 内部リード １１ 内部導体板（カソード側） １２ 外部導出導体板（カソード側） ５ａ，７ａ，１１ａ，１１ｂ，１２ａ 透孔 DESCRIPTION OF SYMBOLS 1 Composite semiconductor device 2 Heat sink 3 Insulating plate 4 External lead-out conductor plate (anode side) 5 Inner conductor plate (anode side) 6 Semiconductor chip assembly 7 Conductor plate 8 Semiconductor chip 9 Temperature compensating plate 10 Internal lead 11 Internal conductor plate ( Cathode side) 12 Externally derived conductor plate (cathode side) 5a, 7a, 11a, 11b, 12a Through hole
Claims (2)
側の外部導出導体板、一方の極性側の内部導体板及び半
導体チップを含むチップ組立体、他方の極性側の外部導
出導体板及び他方の極性側の内部導体板が載置され、そ
れら外部導出導体板と前記内部導体板との重合部および
前記チップ組立体の内部リードが挿通される他方の極性
側の外部導出導体板及び他方の極性側の内部導体板の挿
通部にクリーム半田を塗布して加熱し、上記各部材の重
合部及び前記内部リードの挿通部を半田固着させる複合
半導体装置の製造方法において、上記各部材の重合部の
少なくとも１箇所以上の表面側に位置する部材に透孔を
設け、この透孔にクリーム半田を塗布して加熱し、該重
合部を半田固着させることを特徴とする複合半導体装置
の製造方法。1. An outer lead conductor plate on one side of a polarity, a chip assembly including an inner conductor plate on one side of a polarity and a semiconductor chip, and an outer lead conductor on the other side of the polarity on an radiating plate via an insulating plate. Plate and the inner conductor plate on the other polarity side are placed, and the overlapping portion of the outer lead conductor plate and the inner conductor plate and the outer lead conductor plate on the other polarity side through which the inner lead of the chip assembly is inserted And a method of manufacturing a composite semiconductor device in which cream solder is applied to the insertion portion of the inner conductor plate on the other polarity side and heated, and the overlapping portion of each member and the insertion portion of the internal lead are fixed by soldering. A through hole is provided in a member located on at least one surface side of the overlapped portion, and cream solder is applied to the through hole and heated to fix the overlapped portion by soldering. Production method.
透孔を設け、この透孔にもクリーム半田を塗布して加熱
し、半田固着させることを特徴とする請求項１に記載の
複合半導体装置の製造方法。2. The conductor plate of the chip assembly is provided with a through hole at a substantially central portion thereof, and cream solder is applied to the through hole and heated to fix the solder. Manufacturing method of composite semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3360849A JP3021896B2 (en) | 1991-11-15 | 1991-11-15 | Method for manufacturing composite semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3360849A JP3021896B2 (en) | 1991-11-15 | 1991-11-15 | Method for manufacturing composite semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05145011A true JPH05145011A (en) | 1993-06-11 |
| JP3021896B2 JP3021896B2 (en) | 2000-03-15 |
Family
ID=18471179
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3360849A Expired - Fee Related JP3021896B2 (en) | 1991-11-15 | 1991-11-15 | Method for manufacturing composite semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3021896B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011003205A1 (en) | 2010-01-27 | 2011-07-28 | Mitsubishi Electric Corporation | Semiconductor device module |
-
1991
- 1991-11-15 JP JP3360849A patent/JP3021896B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011003205A1 (en) | 2010-01-27 | 2011-07-28 | Mitsubishi Electric Corporation | Semiconductor device module |
| US8610263B2 (en) | 2010-01-27 | 2013-12-17 | Mitsubishi Electric Corporation | Semiconductor device module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3021896B2 (en) | 2000-03-15 |
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