JPH05144853A - Bonding method of semiconductor chip - Google Patents

Bonding method of semiconductor chip

Info

Publication number
JPH05144853A
JPH05144853A JP27440391A JP27440391A JPH05144853A JP H05144853 A JPH05144853 A JP H05144853A JP 27440391 A JP27440391 A JP 27440391A JP 27440391 A JP27440391 A JP 27440391A JP H05144853 A JPH05144853 A JP H05144853A
Authority
JP
Japan
Prior art keywords
chip
conductive adhesive
gap
die
conductor pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP27440391A
Other languages
Japanese (ja)
Inventor
Kengo Otaka
健吾 大鷹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP27440391A priority Critical patent/JPH05144853A/en
Publication of JPH05144853A publication Critical patent/JPH05144853A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/27011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009Pre-treatment of the layer connector or the bonding area
    • H01L2224/83051Forming additional members, e.g. dam structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED

Abstract

PURPOSE:To prevent a conductive adhesive agent from crawling up and getting stuck between LEDs when the LEDs are arranged in array and die-bonded. CONSTITUTION:LED chips 3 are arranged in array on a conductor pattern 2 formed on a board 1 providing a gap between them and die-bonded with conductive adhesive agent 4, where a recess 5 is formed by removing a part of the conductor pattern 2 located under the gap concerned. By this setup, the excessive part of the conductive adhesive agent 4 is made to flow into the recess 5 concerned, so that the adhesive agent is prevented from crawling up and getting stuck between the LED chips.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、LEDチップやCCD
チップなどの複数個の半導体チップを並べてボンディン
グする技術に関するものである。
BACKGROUND OF THE INVENTION The present invention relates to LED chips and CCDs.
The present invention relates to a technique of arranging and bonding a plurality of semiconductor chips such as chips.

【0002】[0002]

【従来の技術】LEDプリントヘッドでは複数個のLE
Dチップを要求される長さに応じてダイボンディングす
る。例えば、100mmの長さが要求される場合、10
mmの長さのチップを10個並べる。これは要求される
長さを1チップで満足できればよいがチップ製造上の歩
留コストと、実装コスト(複数個のチップをボンディン
グする)との兼ね合いにより、生じるものである。実
際、A4版サイズのLEDプリンタに使用するLEDヘ
ッドの場合、長さおよそ5.4mmのチップを40個一
列に一個ずつダイボンディングし、所定の印字幅を確保
する。
2. Description of the Related Art In an LED print head, a plurality of LEs are used.
D-bond the D chip according to the required length. For example, if a length of 100 mm is required, 10
Arrange 10 mm length chips. This only needs to satisfy the required length with one chip, but it occurs due to the balance between the yield cost in chip manufacturing and the mounting cost (bonding a plurality of chips). In fact, in the case of an LED head used for an A4 size LED printer, 40 chips each having a length of about 5.4 mm are die-bonded in a row, one by one, to secure a predetermined print width.

【0003】同様に、CCDイメージセンサではCCD
チップを要求される長さに応じてダイボンディングし、
所定の読取幅を確保する。図2は従来のLEDチップの
ダイボンディング方法を示す側面図で、(a)はダイボ
ンディング前、(b)はダイボンディング後の様子を示
している。図において11はガラスエポキシ樹脂等で形
成された基板、12は基板11上に銅箔等で形成された
導体パターン(共通端子パターン)、13はLEDチッ
プ、14はLEDチップ13を導体パターン12に接着
する銀ペースト等の導電性接着剤である。
Similarly, in the CCD image sensor, the CCD
Die-bond the chip according to the required length,
Secure a predetermined reading width. 2A and 2B are side views showing a conventional LED chip die bonding method. FIG. 2A shows a state before die bonding and FIG. 2B shows a state after die bonding. In the figure, 11 is a substrate formed of glass epoxy resin or the like, 12 is a conductor pattern (common terminal pattern) formed of copper foil or the like on the substrate 11, 13 is an LED chip, and 14 is the LED chip 13 as the conductor pattern 12. It is a conductive adhesive such as a silver paste to be adhered.

【0004】この図に示すように、LEDチップのダイ
ボンディングは、基板11上に形成された導体パターン
12に導電性接着剤14を塗布し、その上にLEDチッ
プ13を載置して加圧することにより行っていた。
As shown in this figure, in die bonding of an LED chip, a conductive adhesive 14 is applied to a conductor pattern 12 formed on a substrate 11, and an LED chip 13 is placed thereon and pressed. I was doing it.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、前記従
来のLEDチップのダイボンディング方法において、図
2のA部を拡大した図3(a),(b)に示すように、
LEDチップ13間の隙間は発光部15のピッチを確保
するため、10μm前後しか設けられていない。そのた
め、ダイボンディング時に導電性接着剤14がLEDチ
ップ13間にはみ出し、溜まり16を生じる(図3
(a))。さらに、チップ端面13aに逆テーパがある
と、毛細管現象により這い上がりを生じ、チップ表面に
まで到達し、LEDチップ13間に詰まる場合がある
(図3(b))。LEDチップ13間に導電性接着剤1
4が詰まると、チップ13の動作時の自己発熱あるいは
環境温度変化により膨張、収縮ストレスを生じ、近傍に
ある発光部15のPN接合部に歪みを与え、PN接合部
の劣化による光量低下を招くという問題点があった。
However, in the conventional LED chip die-bonding method, as shown in FIGS. 3 (a) and 3 (b) in which the portion A of FIG. 2 is enlarged,
The gap between the LED chips 13 is provided only around 10 μm in order to secure the pitch of the light emitting portions 15. Therefore, at the time of die bonding, the conductive adhesive 14 protrudes between the LED chips 13 to form a pool 16 (see FIG. 3).
(A)). Further, if the chip end surface 13a has an inverse taper, it may creep up due to a capillary phenomenon, reach the chip surface, and clog the LED chips 13 (FIG. 3 (b)). Conductive adhesive 1 between the LED chips 13
When 4 is clogged, self-heating during the operation of the chip 13 or expansion / contraction stress is caused by a change in environmental temperature, which causes distortion in the PN junction of the light emitting section 15 in the vicinity, resulting in deterioration of the light amount due to deterioration of the PN junction. There was a problem.

【0006】また、複数個のCCDチップをダイボンデ
ィングした場合にも同様にイメージセンサの受光部が劣
化するという問題点があった。そして、上記問題点を解
決する方法として、導電性接着剤の供給量を必要最低限
に停めるため、スタンプのように一定形状、厚みをもっ
て供給するスタンピング法、導電性接着剤を小径の点状
に分割して供給する多点法などが工夫されているが、チ
ップ裏面全面を導電性接着剤で満たすようにすると導電
性接着剤の余剰分がどうしてもはみだしてしまう。逆
に、チップ裏面全面を満たさないようにすると、LED
チップのごときチップ幅が狭い(500μm前後)のも
のではワイヤボンド等に耐える充分な接着強度を得られ
ず、また、チップの浮き、傾きによりワイヤボンド条件
に影響を与える。また、図4に示すように、チップ下端
部13bを削り込んで導電性接着剤の余剰分の這い上が
りと詰まりを防止をしている例があるが、チップをウェ
ハーより切り出すスクライブを2度行わねばならないと
いう不具合がある。
Further, when a plurality of CCD chips are die-bonded, the light receiving portion of the image sensor is also deteriorated. Then, as a method of solving the above problems, in order to stop the supply amount of the conductive adhesive to a necessary minimum, a stamping method of supplying a constant shape and thickness like a stamp, the conductive adhesive into a small diameter dot shape. Although the multi-point method of supplying by dividing is devised, if the entire back surface of the chip is filled with a conductive adhesive, the surplus of the conductive adhesive will inevitably overflow. Conversely, if you do not fill the entire back surface of the chip, the LED
A chip having a narrow width (about 500 μm) such as a chip cannot obtain sufficient adhesive strength to withstand wire bonding and the like, and the floating and inclination of the chip affect the wire bonding conditions. Further, as shown in FIG. 4, there is an example in which the lower end portion 13b of the chip is cut to prevent the excess creeping up and clogging of the conductive adhesive, but the chip is cut out from the wafer twice. There is a problem that it must be done.

【0007】本発明は、以上述べた導電性接着剤の這い
上がりと詰まりによるストレス発生を防ぐため、導体パ
ターンのレイアウトに工夫を加えることにより、接着剤
の供給量の制約を大幅に緩和し、かつ、チップの構造を
変更することなく接着剤の這い上がりを防止し、結果と
して半導体チップの劣化を防ぐことのできる半導体チッ
プのダイボンディング方法を提供することを目的とす
る。
According to the present invention, in order to prevent the stress caused by the above-mentioned creeping up and clogging of the conductive adhesive, the layout of the conductor pattern is modified so that the restriction on the supply amount of the adhesive is greatly alleviated. Moreover, it is an object of the present invention to provide a die bonding method for a semiconductor chip, which can prevent the adhesive from creeping up without changing the structure of the chip and consequently prevent the deterioration of the semiconductor chip.

【0008】[0008]

【課題を解決するための手段】前記問題点を解決するた
めに、本発明は、基板上に形成された導体パターン上に
複数個の半導体チップを隙間を設けて配列し、導電性接
着剤によりダイボンディングする方法において、隙間の
下部の導体パターンを除去して凹みを形成し、導電性接
着剤の余剰分を該凹みに収容するようにしたものであ
る。
In order to solve the above-mentioned problems, the present invention provides a method in which a plurality of semiconductor chips are arranged on a conductor pattern formed on a substrate with a gap therebetween and a conductive adhesive is used. In the die-bonding method, the conductor pattern under the gap is removed to form a recess, and the surplus conductive adhesive is accommodated in the recess.

【0009】[0009]

【作用】本発明によれば、以上のように半導体チップの
ダイボンディング方法を構成したので、導電性接着剤の
余剰分は隙間の下部に形成された凹みに収容される。し
たがって、導電性接着剤の余剰分はチップ間の隙間を這
い上がらなくなり、チップ間に詰まらなくなる。
According to the present invention, since the semiconductor chip die bonding method is configured as described above, the surplus of the conductive adhesive is accommodated in the recess formed in the lower portion of the gap. Therefore, the surplus of the conductive adhesive does not crawl up the gap between the chips and does not clog the chips.

【0010】[0010]

【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の実施例に係るL
EDチップのダイボンディング方法の説明図で、(a)
はダイボンディング前の側面図、(b)はダイボンディ
ング後の側面図、(c)はダイボンディング後の平面図
である。
Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows an L according to an embodiment of the present invention.
It is an explanatory view of the die-bonding method of an ED chip, (a)
Is a side view before die bonding, (b) is a side view after die bonding, and (c) is a plan view after die bonding.

【0011】図において、1はガラスエポキシ樹脂で形
成された基板、2は基板1上に銅箔で約25μmの厚さ
に形成された導体パターン(共通端子パターン)、3は
LEDチップ、4は10μmの隙間を設けて並べられる
複数個のLEDチップ3を導体パターン2に接着する銀
ペースト等の導電性接着剤である。本実施例において
は、さらに、複数個のLEDチップ3の隙間の下部の導
体パターン2をエッチングして除去し、基板面を露出さ
せている。その結果、LEDチップ3間の隙間の下部に
は導体パターン2を構成する銅箔の厚み分(約25μ
m)の凹み5が形成される。
In the figure, 1 is a substrate formed of glass epoxy resin, 2 is a conductor pattern (common terminal pattern) formed on the substrate 1 with copper foil to a thickness of about 25 μm, 3 is an LED chip, and 4 is It is a conductive adhesive such as a silver paste that adheres a plurality of LED chips 3 arranged with a gap of 10 μm to the conductor pattern 2. In this embodiment, the conductor pattern 2 under the gaps between the plurality of LED chips 3 is further etched and removed to expose the substrate surface. As a result, in the lower part of the gap between the LED chips 3, the thickness of the copper foil forming the conductor pattern 2 (about 25 μm
The depression 5 of m) is formed.

【0012】本実施例においては、LEDチップ3のダ
イボンディングは、基板1上に形成された導体パターン
2に導電性接着剤4を塗布し、その上にLEDチップ3
を10μmの隙間を設けて載置して加圧することにより
行う。この時、図1(b)に示すように、LEDチップ
3の下から隙間にはみだした接着剤4の余剰分は隙間の
下部に形成された凹み5に収容されるので、LEDチッ
プ3間の隙間を這い上がらなくなる。基板1がガラスエ
ポキシ樹脂製の場合、接着剤4自体も流れ(拡がり)に
くいので、効果は大きい。
In the present embodiment, the LED chip 3 is die-bonded by applying a conductive adhesive 4 to the conductor pattern 2 formed on the substrate 1 and then applying the LED chip 3 thereon.
Is placed with a gap of 10 μm and pressed. At this time, as shown in FIG. 1 (b), since the surplus of the adhesive 4 protruding from the bottom of the LED chip 3 into the gap is accommodated in the recess 5 formed in the lower part of the gap, the space between the LED chips 3 is reduced. It will not be able to crawl through the gap. When the substrate 1 is made of glass epoxy resin, the adhesive 4 itself does not easily flow (spread), so that the effect is great.

【0013】また、本実施例においては、隙間の下部に
形成した凹み5のチップ配列方向の長さを隙間の間隔
(10μm前後)よりも長くすることにより、ダイボン
ディング位置精度のバラツキを吸収して這い上がりを防
止するようにした。さらに、このようにすると凹み5の
容量が大きくなるので、確実に導電性接着剤4の這い上
がりを防止することができる。ただし、このようにする
と、LEDチップ3の裏面がパターン2をエッチングし
て除去した部分へ飛び出すが、LEDチップ3の裏面に
形成されたAu系電極によりLEDチップ3と導体パタ
ーン2とのオーミック性は確保されている。
Further, in this embodiment, by making the length of the recesses 5 formed in the lower portion of the gap in the chip arrangement direction longer than the gap interval (around 10 μm), variations in die bonding position accuracy are absorbed. To prevent crawl up. Further, in this way, the capacity of the recess 5 becomes large, so that it is possible to reliably prevent the conductive adhesive 4 from creeping up. However, in this case, the back surface of the LED chip 3 jumps out to a portion where the pattern 2 is removed by etching, but the Au-based electrode formed on the back surface of the LED chip 3 causes ohmic contact between the LED chip 3 and the conductor pattern 2. Is secured.

【0014】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づき種々の変形が可能で
あり、それらを本発明の範囲から排除するものではな
い。また、本発明はCCDチップ等をダイボンディング
する際に適用することもできる。
The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, which are not excluded from the scope of the present invention. The present invention can also be applied when die bonding a CCD chip or the like.

【0015】[0015]

【発明の効果】以上、詳細に説明したように、本発明に
よれば、複数のチップを僅かな隙間を設けて並べ、ダイ
ボンディングする際に、導電性接着剤の余剰分を隙間の
下部に形成した凹みに収容するようにしたので、下記の
効果を奏する。 (1)導電性接着剤のチップ間への這い上がりと詰まり
が防止される。その結果、チップ端部へのストレスの発
生をチップの構造的工夫を要しない簡便な方法で防止す
ることができ、チップと導体パターンの接続部分の信頼
性向上に大きな効果がある。 (2)チップも含め、コストを何らアップすることな
く、ダイボンディングが行える。 (3)接着剤供給量の制約を大幅に緩和することができ
る。 (4)チップ間の隙間の更なる狭小化に容易に対応する
ことができる。
As described above in detail, according to the present invention, when a plurality of chips are arranged with a slight gap and die-bonded, the surplus amount of the conductive adhesive is provided below the gap. Since it is accommodated in the formed recess, the following effects are achieved. (1) The conductive adhesive is prevented from creeping up between the chips and clogging. As a result, it is possible to prevent the occurrence of stress on the end of the chip by a simple method that does not require structural modification of the chip, and it is very effective in improving the reliability of the connection portion between the chip and the conductor pattern. (2) It is possible to perform die bonding including the chip without increasing the cost. (3) The restrictions on the adhesive supply amount can be significantly eased. (4) It is possible to easily cope with further narrowing of the gap between the chips.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例に係る半導体チップのダイボン
ディング方法の説明図である。
FIG. 1 is an explanatory diagram of a die bonding method for a semiconductor chip according to an embodiment of the present invention.

【図2】従来のLEDチップのダイボンディング方法を
示す側面図である。
FIG. 2 is a side view showing a conventional LED chip die bonding method.

【図3】図2のA部拡大図である。FIG. 3 is an enlarged view of part A of FIG.

【図4】従来のLEDチップの加工例の説明図である。FIG. 4 is an explanatory diagram of a processing example of a conventional LED chip.

【符号の説明】[Explanation of symbols]

1 基板 2 導体パターン 3 LEDチップ 4 導電性接着剤 5 凹み 1 substrate 2 conductor pattern 3 LED chip 4 conductive adhesive 5 recess

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 基板上に形成された導体パターン上に複
数個の半導体チップを隙間を設けて配列し、導電性接着
剤によりダイボンディングする方法において、 前記隙間の下部の導体パターンを除去して凹みを形成
し、前記導電性接着剤の余剰分を該凹みに収容すること
を特徴とする半導体チップのダイボンディング方法。
1. A method of arranging a plurality of semiconductor chips on a conductor pattern formed on a substrate with a gap and die-bonding with a conductive adhesive, wherein the conductor pattern under the gap is removed. A method for die-bonding a semiconductor chip, characterized in that a recess is formed and an excess of the conductive adhesive is accommodated in the recess.
【請求項2】 凹みのチップ配列方向の長さを隙間の間
隔よりも長くしたことを特徴とする請求項1記載の半導
体チップのダイボンディング方法。
2. The method of die bonding a semiconductor chip according to claim 1, wherein the length of the recess in the chip arrangement direction is longer than the gap.
【請求項3】 半導体チップがLEDチップである請求
項1又は2記載の半導体チップのダイボンディング方
法。
3. The method of die bonding a semiconductor chip according to claim 1, wherein the semiconductor chip is an LED chip.
JP27440391A 1991-10-23 1991-10-23 Bonding method of semiconductor chip Withdrawn JPH05144853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27440391A JPH05144853A (en) 1991-10-23 1991-10-23 Bonding method of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27440391A JPH05144853A (en) 1991-10-23 1991-10-23 Bonding method of semiconductor chip

Publications (1)

Publication Number Publication Date
JPH05144853A true JPH05144853A (en) 1993-06-11

Family

ID=17541187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27440391A Withdrawn JPH05144853A (en) 1991-10-23 1991-10-23 Bonding method of semiconductor chip

Country Status (1)

Country Link
JP (1) JPH05144853A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7012332B2 (en) 2002-10-11 2006-03-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having sealing structure for wide gap type semiconductor chip

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7012332B2 (en) 2002-10-11 2006-03-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having sealing structure for wide gap type semiconductor chip

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