JPH05143252A - Memory controller - Google Patents

Abstract

PURPOSE:To efficiently utilize a memory. CONSTITUTION:The image data of a one-page portion is divided into the four pieces of blocks and the start and end addresses of each block stored successively in an arbitrary area of a free area of a RAM are set to flip-flops (F/Fs) 611-614 and F/Fs 621-624, respectively. A video transfer address management sequencer 67 selects the start and end addresses latched to the F/Fs 611, 621 by selectors 63, 64 and gives them to an address counter 65 and a comparator 66. From the address counter 65, a RAM address is outputted successively, and read-out RAM data is outputted as a video signal from a shift register 68. When the comparator 66 detects the a coincidence of address values, the sequencer 67 selects the start and end addresses latched to the F/Fs 611, 622 by the selectors 63, 64, and thereafter, the repeat operation is executed in the same way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device for controlling access to a memory for temporarily storing data, and more particularly to image data generated in an image generation circuit of a page printer, a so-called interface control circuit. The present invention relates to a memory control device suitable for access control of a memory for temporarily storing before transferring to a printer unit.

[0002]

2. Description of the Related Art In recent years, page printers have become widespread as printers connected to document creation devices such as word processors and office computers. Such a page printer has an image generation circuit (commonly called an interface (I / F) controller) for exchanging data with a host computer such as a document creation device, a print head (exposure head), and a photosensitive drum. It is composed of a printer unit (printer engine).

That is, this type of page printer is an I / F
In the controller, the character code sent from the host computer is converted into a character pattern (image) composed of dots and expanded in the bitmap memory (image memory), and the image data expanded in this image memory Is printed out on a printing paper by a printer engine.

I / F in such a page printer
Since the image memory of the controller stores image data in a dot pattern, a large capacity is required to secure the image memory for one page, and various attempts have been made to improve the utilization efficiency. There are many attempts, but they are classified into the following three patterns.

A) As shown in FIG. 10A, an image memory for one page is secured in a continuous memory space.

B) As shown in FIG. 10B, the image memory is divided into several blocks, and the next image is drawn in order from the area where the transfer is completed (in the figure, the image memory is divided into three blocks). Is an example divided into).

C) As shown in FIG. 10C, the image memory is divided into memory blocks each having a fixed length and width,
Organize by adding a function to convert the actual memory address and the logical address of the image memory. As a method of allocating (allocating) a memory block to each area, there are methods such as (1) allocating according to a fixed rule, (2) allocating an empty memory block to a required position, and the like.

[0008]

However, in the case of the method in which the image memory of the above a) is taken in the memory space for one page continuous, if the secured memory capacity is one page, all the image data of the previous page Until the image memory is completely cleared and the image memory is completely cleared. Therefore, in order to speed up the printing process, image memories for a plurality of pages are required.

Further, in the method b) in which the image memory is divided into a plurality of blocks and the blocks which become usable by the transfer are rearranged for drawing the next page, even if the memory capacity is one page, Since parallel processing of transfer and drawing is possible, printing can be speeded up, and since memory is managed in block units instead of page units, it can be effectively used even if the memory capacity is less than multiple pages. It has the advantage of The image memory of c) above is divided into memory blocks of a certain amount in the vertical and horizontal directions, and the same advantage can be obtained in the method of rearranging by providing the function of converting the actual memory address and the logical address of the image memory. There is.

However, these methods b) and c) require a function of converting a logical address of the image memory into an actual memory address. Conventionally, such a function is dedicated by installing an image memory separately from the memory managed by the CPU, fixing the area, or the like, and managing the number of manageable pages, the number of blocks, and one page. , Y dots are limited. Therefore, it has been difficult to flexibly deal with changes in resolution and paper size, memory expansion, and the like.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a memory control device capable of flexibly coping with an increase in memory, operating conditions, or an increase / decrease in free memory due to font registration. To aim.

[0012]

In order to achieve the above object, a memory control device for controlling reading / writing of a predetermined amount of data from / into a memory for temporary storage of data according to the present invention comprises a plurality of blocks each having an arbitrary amount. And each block is stored in an arbitrary area of the free area of the temporary storage memory, the predetermined amount of data is stored in the temporary storage memory when being read from the temporary storage memory. Setting means for sequentially setting the start address and the end address of the stored area of each block, and the temporary storage memory is selectively selected sequentially based on the start and end addresses set by the setting means. And a selective reading means for reading the predetermined amount of data from the temporary storage memory in a regular order. That.

[0013]

That is, in the memory control device of the present invention, when storing a predetermined amount of data in the temporary storage memory, the predetermined amount of data is divided into a plurality of blocks of arbitrary amounts, and each block is When the predetermined amount of data is read from the temporary storage memory by storing it in an arbitrary area of the free space of the temporary storage memory, the setting means
A start address and an end address of the stored area of each block are sequentially set according to the order stored in the temporary storage memory, and based on each start and end address set by the setting means by the selective reading means. By sequentially and selectively accessing the temporary storage memory, the predetermined amount of data is read from the temporary storage memory in a regular order.

For example, if the present invention is applied to a page printer, the address range of the image memory is not predetermined such as from where to where in the address space of the MPU, and an arbitrary address space is stored when storing image data. Can be set. Therefore, unlike the conventional case, a dedicated image memory is not required, and a vacant area of the memory which exists discontinuously or an area added by the addition of RAM can be used as the image memory. Further, it is not necessary to individually deal with each operating condition (resolution, paper size, etc.), and it is possible to flexibly deal with the increase or decrease of the free memory that changes during printer operation, such as the presence or absence of font registration.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block configuration diagram of a memory control device of an embodiment, and FIG. 2 is a block configuration diagram of an interface (I / F) controller of a page printer to which the memory control device of the embodiment is applied.

In FIG. 2, reference numeral 10 is a host computer as a host device, and 20 is a page printer. The page printer 20 includes an I / F controller 30, a printer engine 40, and these I / Fs.
A printer (PR) interface 50 that connects the controller 30 and the printer engine 40 is configured.

The I / F controller 30 includes a host interface 31, a microprocessor (MPU) 32,
It has a ROM 33, a RAM 34, a DMAC (direct memory access controller) 35, a reception buffer 36, an image data generator 37, and a memory controller 38.

The host interface 31 is composed of an 8-bit parallel interface (based on Centronics) and a serial interface (based on RS-232C), and transmits / receives data to / from the host computer 10 having an interface of the same standard.

The MPU 32 executes I / O according to the command analysis and system management programs stored in the ROM 33.
It controls each part in the F controller 30. in this case,
The MPU 32 includes a bus controller, an address latch and the like. In other words, it is an MPU block capable of outputting an address and a read / write signal to read / write data. Also, this MPU3
2 divides one page of image data into a plurality of blocks and draws them in the RAM 34.

The RAM 34 is used as a work area for the MPU 32. It is also used as an image memory.

The DMAC 35 accesses the memory in a system different from that of the MPU 32. A counter is provided inside the DMAC 35, and once the operation is started, the memory is automatically accessed by the designated count number.

The receive buffer 36 temporarily stores commands and data received from the host interface 31 from the host computer 10.

The image data generator 37 is a character generator (CG) ROM in which a character pattern (image data) corresponding to a character code sent from the host computer 10 is stored, or a character pattern (external character) designed by the user. Is stored in a CGRAM for generating image data corresponding to an input code.

The memory control device 38 designates addresses in the video transfer order, that is, in the written order, for each block drawn by the MPU 32 into the RAM 34 by dividing one page of image data into a plurality of blocks. Read out, converted into a video signal and transmitted to the printer engine 40 via the PR interface 50.

The PR interface 50 sends a status signal for monitoring the state of the printer engine 40 from the printer engine 40 to the I / F controller 30.

The printer engine 40 includes a printer unit 41 having various loads such as a printer controller, a print head, various sensors, and a photosensitive drum, which are not shown. The printer section 41 is not directly related to the gist of the present invention, and thus detailed description thereof is omitted.

Next, the characteristic part of the present invention will be described.
FIG. 1 is a diagram in which a characteristic part of the present invention, that is, a memory control device 38 is extracted and shown. However, this figure shows a case where the MPU 32 divides the image data for one page into a plurality of blocks in the RAM 34 and the number of blocks drawn is four.

As shown in the figure, this memory controller 3
8, the flip-flop _{(F / F) 61 1 ~61} 4, 6
2 _{1-62 4,} selectors 63 and 64, the address counter 65, and a comparator 66, a video transfer address management sequencer 67 and the shift register 68,.

[0029] F / F61 ₁ ~61 ₄ respectively, MPU
32 latches the start address of each block drawn in RAM34 is set from, F / F62 ₁ ~62 ₄ respectively latch the end address of each block drawn in RAM34 is set from MPU 32.

The selectors 63 and 64 respectively correspond to F
/ F is selected and the data latched by the selected F / F is output to the subsequent stage.

The address counter 65 uses the address value output from the selector 63 as an initial value, and the DMAC 35
The address value is incremented by the transfer end signal sent every time the transfer of the data of one address is completed.

The comparator 66 compares the address value output from the selector 64 with the count value of the address counter 65, and when both match, sends a match signal to the video transfer address management sequencer 67.

Sequencer 67 for managing video transfer address
Causes the F / F 61 ₁ and 62 ₁ to be selected in response to the start command from the MPU 32, and causes the next F / F to be sequentially selected each time a match signal is sent from the comparator 66.
It controls the selectors 63 and 64.

The shift register 68 outputs the read data as a video signal by loading the data read from the RAM 34 and sequentially bit-shifting and outputting the data.

Next, the memory control device 3 having such a configuration.
The operation of No. 8 will be described. For example, if the data to be transferred is arranged as shown on the left side of FIG. 3A, the MPU 32 divides this into a plurality of blocks, for example, four blocks, and the data is shown on the right side of FIG. Then, the data is sequentially stored in the empty area of the RAM 34.

Assuming that it is stored in the RAM 34 in this way, at the start of video transfer, the address E which is the start address of the first block is set in the F / F 61 ₁ as the first transfer start address, and the first transfer end address is set. And the address F which is the end address of the first block is F /
It is set to F62 ₁ . Similarly, the start addresses C, G, and A of the second, third, and fourth blocks are F / F61 ₂ , 61.
₃ , 61 ₄ and the end addresses D, H, B of the second, third, and fourth blocks are set in F / Fs 62 ₂ , 62 ₃ , and 62 ₄ .

At the time of video transfer, the video transfer address management sequencer 67 selects the first transfer start address and the first transfer end address latched by the F / Fs 61 ₁ and 62 ₁ by the selectors 63 and 64, respectively. To the address counter 65 and the comparator 66. As a result, the address counter 65 starts RA
The M address is output, the read RAM data is loaded into the shift register 68, and is PR as a video signal.
It is transferred to the printer engine 40 via the interface 50. When the comparator 66 detects that the address values match, the video transfer address management sequencer 67
Selects the second transfer start address and the second transfer end address latched in the F / Fs 61 ₂ and 62 ₂ by the selectors 63 and 64, and the same operation is repeated thereafter.

That is, RAM data is sequentially transferred to the printer engine 40 as a video signal from the address E designated as the first transfer start address, and when the address F is detected, the next data is designated as the second transfer start address. Transfer from the designated address C. Similarly, the data of the address B is transferred and the processing is terminated.

Therefore, if there is a free memory space in the RAM 34, it can be used anywhere for an image, so that a dedicated memory area is not required and a capacity of about 1.5 pages can be used efficiently.

In the above embodiment, the number of F / Fs 61 and 62 is four in order to explain the case where the image data for one page is divided into four blocks. The F / Fs 61 and 62 may be set to the maximum number of dividable blocks, or the addresses of the blocks that have completed the transfer are reset to the addresses of the blocks to be newly transferred without increasing the number. You may do it.

Further, instead of using the end address for determining the end of transfer of each block as in the above embodiment, the number of lines in each block can be used. Such a case will be described below as a second embodiment.

In the case of this embodiment, the memory controller 38
Are configured as shown in FIGS. In the figure, 71 ₁ to 71 ₄ are F / F for latching the block start address, 72 _{1-72 4} is F / F for latching the number of Y-direction line of the block. Reference numeral 73 is an F / F that latches an unused block as data indicating that the number of lines in the Y direction of the block is “0”.

[0043] 74 selects one of the F / F71 ₁ -71 _4, a selector for outputting an address value that is latched in the F / F as a count initial value, 75 F
/ F 72 ₁ to 72 ₄ of the select one, a selector for outputting an address value that is latched in the F / F as the count initial value.

Reference numeral 76 is a Y-direction sequencer (Y-SQ) for controlling the selection states of the selectors 74 and 75.

Reference numeral 77 is a transfer address counter which starts counting from the count initial value output from the selector 74, and 78 is a Y line counter which counts from the count initial value output from the selector 75.

The count value of the transfer address counter 77 is given to the bus arbiter / address selector 35A formed in the DMAC 35. The bus arbiter / address selector 35A selectively supplies one of the address from the MPU 32 and the address from the transfer address counter 77 to the RAM 34 to read the RAM data.

Reference numeral 79 is a bidirectional buffer such as LS245. The bus arbiter / address selector 35A is an MPU.
This bidirectional buffer 79 is enabled when 32 initiates a RAM access. That is, the MPU address is selected and given to the RAM 34, the control signal is given to the RAM 34 and the bidirectional buffer 79, the MPU data is written into the RAM 34 via the bidirectional buffer 79, or the data is read from the RAM 34 and read into the bidirectional buffer 79. To the MPU 32 via. In this case, if the RAM 34 is being accessed for video transfer, the bidirectional buffer 79 is enabled after waiting the access. Meanwhile, during that time, the MPU 32 is kept waiting (the READY signal is not output).

Reference numeral 80 is an F / F for latching the data read from the RAM for video transfer, and 81 is this F / F.
It is a shift register that loads the latched data into F80 and outputs video data.

82 is the number of X-direction video transfer words (X _T ).
The latching F / F 83 is a counter that performs a counting operation with the number of X-direction video transfer words (X _T ) latched by the F / F 82 as an initial value. Reference numeral 84 internally has a counter 84A for counting one word, and an X-direction video transfer word number management sequencer (for controlling the transfer address counter 77, bus arbiter / address selector 35A, F / F 80, counter 83, etc.) it is an X _T -SQ).

Reference numeral 85 is an F / F for latching the actual number of X-direction printed dots (X _i ), and reference numeral 86 is a count operation with the number of actual-direction printed dots (X _i ) latched by this F / F 85 as an initial value. It is a counter to do. 87 is this counter 8
6 is an X-direction print area management sequencer (X _i -SQ) for controlling the counting operation of No. 6.

Numeral 88 is a mask circuit for masking the video signal output from the shift register 81 so as to pass only the actual print area under the control of the X _i -SQ 87. For example, the mask circuit 88 can be configured by an AND gate or the like.

[0052] It is to be noted that the Y-SQ76, X _T -SQ8
4, the X _i -SQ87 given vertical synchronization (VSYNC) signal and a horizontal synchronization (HSYNC) signal,. These synchronization signals are signals as shown in FIGS. 6A and 6B. That is, the VSYNC signal is the printer engine 4
A signal sent from 0 indicates that transfer of image data for one page is permitted during this signal output period.
When the VSYNC signal becomes "L", the HSYNC signal indicating the data transfer period for each line is repeatedly output and 1
When the output of the HSYNC signal is repeated for the number of lines corresponding to the pages, the VSYNC signal returns to "H".
Therefore, the duration of "L" varies depending on the size of the printing paper.

The HSYNC signal is a signal sent from the printer engine 40 and indicates that the transfer of image data forming one line is permitted during the signal output period. A predetermined time after the VSINC signal becomes "L", the signal level becomes "L" every fixed period (for example, 1.5 msec). When the time for receiving the video data for one line has passed, it returns to "H". Book HSYN
The “L” duration of the C signal is constant (based on the maximum size) regardless of the paper size.

The bit number of the video data transferred during the HSYNC signal period has a constant value regardless of the paper size. However, in the data, the left margin / right part is adjusted so as to match the paper size. The non-printed part data including the margin is included as white data. That is, the I / F controller 30 transfers 1-line data including the white data.

In addition, the clock (CL
The K) signal is a reference pulse signal for synchronizing the data transfer control, is combined on the I / F controller side, and is sent to the printer engine side. The VSYNC signal and H
All SYNC signals are generated with reference to this CLK signal.

In the video (VIDEO) signal output from the shift register 81 (via the mask circuit 88), the "L" level is a black dot image and the "H" level is a white dot image signal. .. (The I / F controller side synchronizes with this VIDE in synchronization with the falling edge of the CLK signal.
The O signal is output, and the printer engine side inputs the VIDEO signal in synchronization with the rising edge of the CLK signal. ) Hereinafter, the operation in such a circuit configuration will be described. Now, in the image data for one page, the number of X-direction video transfer words is X _T and the number of X-direction actual print dots is X _T.
i , the number of lines of the first block in the Y direction is Y _T1 , the number of lines in the Y direction is the second
If the number of lines of the block is Y _T2 , the number of lines of the third block in the Y direction is Y _T3 , and the number of lines of the fourth block in the Y direction is Y _T4 , the respective values will be MPU before the start of transfer.
F / F 82, 85, 72 ₁ , 72 by 32 write commands
It is latched by ₂ , 72 ₃ , and 72 ₄ . Also, Y _T1 = 0,
The designation of Y _T2 = 0, Y _T3 = 0, Y _T4 = 0 is latched in the F / F 73. Also, the start address of the first block portion of the image data is "A1", the start address of the second block portion is "A2", the start address of the third block portion is "A3", and the start address of the fourth block portion is "A1". A
4 ”, the respective address values are F / F71 ₁ ~
Latched at 71 ₄ .

In this case, the start address and the number of lines in the Y direction of each block latched by the F / F are the RAM 34.
When the image data for one page is divided into a plurality of (for example, four) blocks and stored, the image data is stored in a transfer table provided in a predetermined area of the RAM 34. Therefore, at the time of transfer, the MPU 32 is used. Can easily know at what address of the RAM 34 the block to be transferred is stored, and those values can be set in each F / F. An example of the transfer table is shown in FIG.

Here, one page of image data is formed of two blocks as shown in FIG. 7A, and as shown in FIG. 7B on the memory map. , The data of the first block A is the address "A1"
From the address "A1 + (Y _T1 ) × (X _T )" to the second
If the data of the block B is from the address "A2" to the address "A2 + (Y _T2 ) × (X _T )", the initial value set in the circuit is F / F71 ₁
"A1", F / F71 ₂ "A2", F / F73 Y
Set the bits indicating _T3 = 0 and Y _T4 = 0. Also,
The values of X _T , X _i , Y _T1 and Y _T2 shown in FIG.
F82, 85, 72 ₁ and 72 ₂ respectively.

Then, when the video transfer is started, the Y-SQ 76 first causes the selector 74 to send the latch data of the F / F 71 ₁ when the data transfer VSYNC signal sent from the printer engine side becomes active. To select the address "A1", which is loaded into the transfer address counter 77 as a count initial value. In addition, F is set to the selector 75.
Instruct to select the latch data of / F72 ₁ ,
As a result, the number of lines "Y _T1 " is selected and loaded in the Y line counter 78 as a count initial value.

[0060] On the other hand, X _T -SQ84 is, the bus arbiter,
It outputs a video data request signal to the address selector 35A and waits for the data to be ready.

Bus arbiter / address selector 35A
Arbitrates between read requests MPU access or refresh the like and video data, to select the output of the transfer address counter 77, when equipped with one word of data, and outputs a signal informing it to X _T -SQ84 ..

[0062] X _T -SQ84 Upon receiving this signal,
The data read from the RAM 34 is latched in the F / F 80 and waits until the data transfer HSYNC signal sent from the printer engine side becomes active. And
When the HSYNC signal becomes active, X _T -SQ84
Loads the data latched by the F / F 80 into the shift register 81.

At the same time, the X _i -SQ 87 releases the mask of the mask circuit 88. As a result, the shift register 81 outputs the video data (VIDEO signal) in synchronization with the video transfer clock (CLK signal).
The transfer starts.

[0064] Then, X _T -SQ84, after incrementing the transfer address counter 77 by the address counter enable request (RQ) signal again, and outputs the request signal of the video data to the bus arbiter address selector 35A. After that, when receiving a signal from the bus arbiter / address selector 35A indicating that one word of data has been collected, the signal is latched in the F / F 80 and waits for the transfer of the shift register 81 to end.

[0065] If the transfer of the shift register 81 has been completed, to load the data of F / F80 to the shift register 81, hereinafter, until the count of X _T by counting and the counter 83 of the X _i by the counter 86 is completed, similarly Repeat the operation of.

When the counting of X _i by the counter 86 is completed, the X _i -SQ 87 turns the mask circuit 8 on.
The video data is masked by 8 and waits for the activation of the next HSYNC signal.

[0067] Further, if the count of the X _T by the counter 83 is completed, X _T -SQ84 outputs a signal informing it to Y-SQ76, Y-SQ76 On receiving the signal, Y line counter 78 Is incremented. Then, X _T -SQ84 interrupts the operation at the time of latching the data of the RAM34 to F / F80, the next HS
Wait for the YNC signal to become active.

[0068] After that, if the HSYNC signal of the next line is active, X _T -SQ84 is, F / F8
0 data is loaded into the shift register 81, and X _i
-SQ 87 releases the mask of mask circuit 88 and performs the same transfer as in the previous line.

This operation is performed by the Y line counter 78.
Repeat until counting of Y line by.

[0070] Thus, if Y _T1 line of the video transfer is completed, the (Y _T1 line of transfer X _T -SQ84
(Waiting for the end of), the Y-SQ 76 selects the number of lines "Y _T2 " latched in the F / F 72 ₂ by the selector 75 and loads it into the Y line counter 78. At the same time, the selector 74 selects the address “A2” latched in the F / F 71 ₂ and loads it into the transfer address counter 77.

[0071] On the other hand, X _T -SQ84 is, the bus arbiter,
A video data request signal is output to the address selector 35A, and when the data is complete, it is latched in the F / F 80.

Thereafter, the same transfer as in the first block is performed by VSY.
This is performed until the NC signal becomes inactive.

FIG. 8 is an operation flowchart of Y-SQ76. This Y-SQ76 is, as described above, RA
A signal for selecting an address to be output to M34 is output, and the address is loaded to the transfer address counter (A counter) 77. The initial value of the signal to select is
From Y _{T1 to} Y _T4 , select the smallest number that is not designated by 0 dot (by F / F73). That is, as shown in FIG. 8, if the VSYNC signal becomes active, the value selected from Y _{T1 to} Y _T4 is first set to Y as the initial value.
A Y line counter (Y counter) 78 for counting the number of lines in the direction is loaded. Whenever the HSYNC signal becomes active, the Y line counter 78 is enabled, that is, incremented, and when the loaded count number has been counted (TTL, 163, etc., RCO).
Detection), and the select signal is incremented (up to the value of Y _Tn (n = 1, 2, 3, 4) in which 0 dots are not designated).

[0074] shown in FIG. 9 (A) and (B), X _T -S for counting up an address to be output to the RAM34
It is a flowchart of the operation | movement processed in parallel of Q84.
That is, H (after VSYNC signal becomes active)
When the SYNC signal becomes active, the transfer address counter (A counter) 77 is incremented for each bit number of one word. The number of X-direction video transfer words X
The value of _T is counted by X _T counter 83.

FIG. 9C is an operation flowchart of the X _i -SQ 87. Since the width in the X direction is not limited to the word unit, the X _i -SQ 87 manages the X direction dot number X _i separately from the X direction video transfer word number X _T so as to transfer only an appropriate number of bits. (Count) HS
When the YNC signal is active and when the X _i counter 86 finishes counting, the mask circuit 88 masks the video data and outputs white data.

As described above, in the page printer,
When transferring one page of image data created in the I / F controller 30 to the printer engine side, 1
~ By having a method of sequentially designating a plurality of memory areas, one page is divided into areas of arbitrary capacity and drawn at arbitrary addresses in the memory space of the MPU 32 for image formation. It is possible to have multiple pages.

Although the above embodiment has been described for the case where it is applied to a page printer, it goes without saying that the present invention can be applied to other data processing devices as well. Further, although the above embodiment has been described with respect to the case of image data, the present invention can be similarly applied to data other than image data.

[0078]

As described in detail above, according to the present invention,
It is possible to provide a memory control device capable of flexibly coping with an increase in memory, operating conditions, and an increase / decrease in free memory due to font registration.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a memory control device according to a first embodiment.

FIG. 2 is a block diagram of a page printer to which the memory control device according to the first embodiment is applied.

FIG. 3A is a diagram showing how image data for one page is divided into four blocks and stored.
(B) is a diagram showing a transfer table.

FIG. 4 is a diagram showing the left half of the block diagram of the memory control device according to the second embodiment.

FIG. 5 is a diagram showing the right half of the block diagram of the memory control device according to the second embodiment.

FIG. 6A is a timing chart showing timings of a vertical synchronizing signal and a horizontal synchronizing signal, and FIG. 6B is a timing chart showing timings of a horizontal synchronizing signal, a clock signal, and a video signal.

7A is a diagram showing the relationship between one page of image data and vertical and horizontal synchronizing signals, and FIG. 7B shows a storage arrangement on a memory map of two blocks in FIG. 7A. It is a figure.

8 is an operation flowchart of the Y-direction sequencer in FIG.

9 (A) and 9 (B) are diagrams showing operation flowcharts for parallel processing of the X-direction transfer word number management sequencer in FIG. 5, and FIG. 9 (C) is an X-direction print area management in FIG. It is an operation | movement flowchart of a sequencer.

FIG. 10A to FIG. 10C are diagrams each showing a storage arrangement of image data in a conventional image memory.

[Explanation of symbols]

32 ... MPU, 34 ... RAM, 35 ... Direct memory access controller (DMAC), 38 ... memory controller, 61 _{1-61 4} 62 _{1-62 4} ... flip-flop (F / F), 63,64 ... selector, 65 ... Address counter, 66 ... Comparator, 67 ... Video transfer address management sequencer, 68 ... Shift register.

Claims (1)

[Claims] 1. A memory control device for controlling the reading and writing of a predetermined amount of data from and to a memory for temporary storage of data, wherein each block is divided into a plurality of blocks of an arbitrary amount, and each block is free in the memory for temporary storage. When the predetermined amount of data stored in an arbitrary area of the area is read from the temporary storage memory, the start address of the stored area of each block according to the order stored in the temporary storage memory And an end address are sequentially set, and the temporary storage memory is sequentially and selectively accessed based on each of the start and end addresses set by the setting means, so that the temporary storage memory is used to selectively access the temporary storage memory. A memory control device comprising: a selective reading unit for reading quantitative data in a regular order.