JPH04299439A - Memory access control circuit - Google Patents

Abstract

PURPOSE:To assure the operation of a CPU as long as no bus collision occurs while a DMAC is having an access to a frame memory. CONSTITUTION:When a CPU 32 tries to have an access to a ROM 33 while a DMC 35 is having an access to a RAM 38, a CPU stop signal is outputted from a CPU stop circuit 61 and however no output is produced from a decorder 62 owing to no collision of buses. Thus the CPU stop conditions are not satisfied at a stop condition circuit 64. Therefore the CPU stop condition signal is not outputted from the circuit 64 and then never outputted to the CPU 32 from an AND gate 65. As a result, the operation of the CPU 32 is not stopped and therefore the access given to the ROM 33 from the CPU 32 is carried out in parallel with the access given to an FRAM 38 from the DMAC 35.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is applicable to, for example, ROM and RA.
The present invention relates to a data processing device such as a page printer having a CPU and a DMAC (direct memory access controller) that access M, and particularly to a memory access control circuit that controls access operations of a ROM and RAM by the CPU and DMAC.

0002

2. Description of the Related Art In recent years, page printers have become popular as printers connected to document creation devices such as word processors and office computers. Such a page printer has an image generation control unit (commonly known as an interface (I/F) controller) for exchanging data with a host computer such as a document creation device, and a print head (
It consists of a printer engine that has an exposure head (exposure head) and a photoreceptor drum.

[0003] That is, this type of page printer has an I/F
In the controller, the character code sent from the host computer is converted into a character pattern (image) made up of dots and expanded onto a bitmap memory (frame memory), and the image data expanded into this frame memory. A printer engine prints out the information on printing paper.

[0004] I/F in such a page printer
As shown in FIG. 6, the controller includes CPU100, D
MAC (Direct Memory Access Controller) 10
2. ROM 104 as system memory, RAM 106 as the above frame memory, CPU stop circuit 108
, and buffers 110 and 112.

That is, in response to character code data input from a host computer (not shown), a CG (not shown)
Pattern data generated from a character generator (character generator) is written to a predetermined address of a RAM (frame memory) 106 under the control of a CPU 100. Then, the image data for one page of paper is stored in RAM10.
6, the CPU 100 sets the read start and end addresses of the RAM 106 in the DMAC 102. As a result, the DMAC 102 starts a read operation, and executes image data transfer processing to a printer engine (not shown). During this time, read processing is performed by DMAC1.
02 is in charge, and the CPU 100 can perform other processing.

[0006]

[Problem to be solved by the invention] By the way, CPU10
0 and DMAC102 operate individually, so the DMA
The CPU 100 does not know whether the C 102 is currently accessing the RAM 106 or not. Therefore, RAM10
In order to prevent the CPU bus and DMAC bus from colliding on the CPU 6, a CPU stop circuit 108 completely stops the operation of the CPU 100 while the DMAC 102 is accessing the RAM 106.

Therefore, while the DMAC 102 is transferring image data from the RAM 106, the CPU 1
00 should be able to perform other processing such as accessing the ROM 104, but in reality, C
Since the PU stop circuit 108 operates to stop the operation of the CPU 100 and prevent the CPU bus from colliding with the DMAC bus, the CPU 100 cannot operate effectively.

That is, while the DMAC 102 is operating,
Since the CPU 100 is completely stopped, for example, DM
ROM 10 of CPU 100 while AC 102 is operating
4 access was impossible even though no bus collision occurred. Therefore, the efficiency of the CPU 100 is extremely low, which is a big problem, especially in page printers that require high-speed processing.

The present invention has been made in view of the above points, and an object of the present invention is to provide a memory access control circuit that enables a CPU to operate as long as a bus collision does not occur and allows the CPU to operate efficiently. shall be.

0010

[Means for Solving the Problems] That is, the memory access control circuit of the present invention provides access to first and second memories, and at least a portion of these first and second memories via a common bus. and a stop signal that generates a signal for always stopping the operation of the second memory access means while the first memory access means is accessing the first memory. a first operating signal generating means for generating a signal indicating that the first memory accessing means accesses the first memory; and a first operating signal generating means for generating a signal indicating that the first memory access means accesses the first memory; Only when a second in-operation signal generation means generates a signal indicating that the access means accesses the first memory, and the first and second in-operation signal generation means generate their respective signals simultaneously. The first memory access means is accessing by supplying a signal generated from the stop signal generation means to the second memory access means to prohibit the access operation of the second memory access means. and operation control means that enables the second memory access means to access a memory other than the memory.

[0011]

[Operation] In the memory access control circuit of the present invention, at the same time that the first in-operation signal generation means generates a signal indicating that the first memory access means, for example, DMAC accesses the first memory, for example, RAM, the second When the second in-operation signal generation means generates a signal indicating that the CPU accesses the first memory, the operation control means transmits the signal generated from the stop signal generation means to the second in-operation signal generation means. The data is supplied to the second memory access means to inhibit the access operation of the second memory access means. Further, at other times, the operation control means does not supply the signal generated from the stop signal generation means to the second memory access means, so that the memory accessed by the first memory access means is Memory other than ROM
This enables the second memory access means to perform an access operation to a second memory such as the following. Therefore, as long as a bus collision does not occur, the CPU can operate, and the CPU can operate efficiently.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a memory access control circuit according to an embodiment, and FIG. 2 is a block diagram of an interface (I/F) controller of a page printer to which the memory access control circuit according to an embodiment is applied.

In FIG. 2, reference numeral 10 is a host computer as a host device, and 20 is a page printer. This page printer 20 includes an I/F controller 30, a printer engine 40, and these I/Fs.
The printer (PR) interface 50 connects the controller 30 and the printer engine 40.

The I/F controller 30 includes a host interface 31, a CPU 32, a ROM 33, and a RAM 34.
, DMAC (Direct Memory Access Controller)
35, reception buffer 36, image data generation section 37,
It has a frame memory (FRAM) 38.

The host interface 31 is composed of an 8-bit parallel interface (based on Centronics) and a serial interface (based on RS-232C), and sends and receives data to and from the host computer 10 having an interface of the same standard.

[0016] The CPU 32 performs I/O processing according to command analysis and system management programs stored in the ROM 33.
Controls each part within the F controller 30. in this case,
The CPU 32 includes a bus controller, address latch, and the like. In other words, it is a CPU block that can output addresses and read/write signals and read/write data. Further, the RAM 34 is used as a work area for the CPU 32.

The DMAC 35 accesses memory in a separate system from the CPU 32. A counter is configured inside the DMAC 35, and once it starts operating, it automatically accesses the memory by the specified count number. Furthermore, while accessing the FRAM 38, it outputs an "in operation" signal indicating that the RAM is being accessed.

The reception buffer 36 temporarily stores commands and data received from the host computer 10 by the host interface 31. The image data generation unit 37 generates a character pattern (image data) corresponding to the character code sent from the host computer 10.
The computer is comprised of a character generator (CG) ROM that stores characters, and a CGRAM that stores character patterns (external characters) designed by the user.

The frame memory 38 is a bitmap memory for developing an image for one page, and is a bitmap memory for developing an image for one page, excluding a predetermined margin width on the top, bottom, left and right of the largest printable paper (for example, B4 size). It has a storage capacity of

The PR interface 50 converts the image data developed from the I/F controller 30 into the FRAM 38 into a video signal and sends it to the printer engine 40, and also allows the printer engine 40 to monitor the status of the printer engine 40. Status signal I/F
It is sent to the controller 30.

The printer engine 40 includes a printer section 41 having various loads such as a printer controller (not shown), a print head, various sensors, and a photosensitive drum. Since this printer section 41 is not directly related to the gist of the present invention, detailed explanation will be omitted.

Next, the features of the present invention will be explained. FIG. 1 is a diagram showing a characteristic part of the present invention, that is, a memory access control circuit, and the same parts as in FIG. 2 are given the same reference numerals. This memory access control circuit is
Above CPU32, ROM33, DMAC35, FRAM
38, a CPU stop circuit 61, decoders 62, 6
3, a stop condition circuit 64, an AND gate 65, a plurality of buffers, and a plurality of data buses, address buses, signal lines, etc.

[0023] Here, the CPU stop circuit 61
While the CPU 35 is accessing the memory, it always outputs a "CPU stop signal". That is, since the DMAC 35 operates automatically, the CPU 32 cannot confirm whether or not the DMAC 35 is operating.
In order to prevent bus collision on FRAM38, DM
While the AC 35 is in operation, it outputs a "CPU stop signal" to completely stop the operation of the CPU 32.

However, if the CPU 32 is suddenly stopped in the middle of a bus cycle of the CPU 32, the operation will become erratic, so this CPU stop circuit receives an "HRQ (hold request)" as an operation start inquiry signal from the DMAC 35.
Depending on the signal, refer to the bus status and set the CP
DM the "HLDA (hold acknowledge) signal" as an operation start permission signal at the break of the U32 bus cycle.
By sending the data back to AC35, DMAC35 always sends C
The operation is started at a break in the bus cycle of the PU 32.

The decoder 62 outputs the CPU-side conditions required by the stop condition circuit 64. In this embodiment, when the CPU 32 is reading/writing the FRAM 38 (the ROM 33 is read/written by the address) (Whether accessing FRAM 38 or FRAM 38 is known) is output. This decoder also determines the output of the condition signal based on the above-mentioned "bus status".

In other words, "bus status" means the current C
This signal indicates the state of the PU bus, and is output a little earlier than the "read/write signal" output from the CPU 32. Therefore, with this "bus status", the CP
It becomes possible to know the operating state of U32. Furthermore, if a stop signal is sent to the CPU 32 immediately after this signal is output, it becomes possible to control the stop from the beginning of memory read/write.

[0027] In the decoder 63, the CPU 32 is connected to the ROM 33.
This is used to create control signals for reading and reading/writing the FRAM38. When the operation of the CPU 32 is stopped by the "CPU conditional stop signal" as described later, the "CPU conditional stop signal" is also input to this decoder 63 at the same time.
Stop the AM38 read/write signal (actually, make it wait).

The stop condition circuit 64 is a circuit that outputs a "CPU stop condition signal", and in this embodiment, the DMAC
35 “operating signal” and the CPU 32 from the decoder 62
When the read/write signal of
Outputs the PU stop condition signal. This stop condition circuit 64
can be constructed with a simple AND gate 64a, as shown in FIG.

The AND gate 65 is connected to the CPU stop circuit 61.
``CPU stop signal'' from ``CPU stop signal'' and ``from stop condition circuit 64''
This function performs a logical product with the CPU stop condition signal.
When both the "U stop signal" and the "CPU stop condition signal" are supplied, the "CPU conditional stop signal" is sent to the CPU 32.
Output. In other words, the "CPU stop signal" is supplied to the CPU 32 as the "CPU conditional stop signal" only when the "CPU stop condition signal" is supplied.

FIG. 4 is a diagram showing the operation timing of the memory access control circuit having such a configuration, and the operation will be explained below with reference to this diagram. That is, DMAC35
If the CPU 32 tries to access the FRAM 38 while the CPU 32 is accessing the FRAM 38, the decoder 62
detects this based on the “bus status” and the CPU 32
An output indicating that the FRAM 38 has started accessing the FRAM 38 is supplied to the stop condition circuit 64. On the other hand, at this time, the stop condition circuit 64 receives the FRA of the DMAC 35 from the DMAC 35.
An "active" signal is provided indicating that the M38 is being accessed. Therefore, this stop condition circuit 64 outputs a "CPU stop condition signal" to the AND gate 65. At the same time, a "CPU stop signal" is input to the AND gate 65 from the CPU stop circuit 61. When these two signal conditions are met, the AND gate 65 outputs “C”.
A PU conditional stop signal is output, and the operation of the CPU 32 is stopped. That is, the CPU 32 uses the FRA of the DMAC 35.
The WAIT state is maintained until the M38 access is completed.

[0031] Furthermore, the above-mentioned "CPU conditional stop signal" is
It is also supplied to the decoder 63. In response to the supply of this signal, the decoder 63 blocks the supply of the "read/write" signal to the FRAM 38, and after this signal disappears, the FRAM 38 receives the "read/write" signal.
Gives a "read/write" signal to RAM38.

In this way, the read/write of the FRAM 38 is delayed by the "CPU conditional stop signal" to prevent bus collision.

Furthermore, when the CPU 32 attempts to access the ROM 33 while the DMAC 35 is accessing the FRAM 38, a "CPU stop signal" is sent from the CPU stop circuit 61.
is output, but since the bus does not collide, the CPU stop condition is not satisfied and the "CPU stop condition signal" is not output, so the AND gate 65 outputs the "CPU conditional stop signal". It never happens. Therefore, the CPU
32 is never stopped, and the ROM of the CPU 32
33 and the DMAC 35 access to the FRAM 38 can be executed in parallel.

In FIG. 1, in order to simplify the explanation, it is assumed that only the ROM 33 and FRAM 38 are connected to the CPU bus, but in reality, various circuits such as input/output ports are connected to the CPU bus. or device is connected, and the DMAC35
During access to FRAM38 of CPU32, FRAM38 of CPU32 is accessed.
All operations except 8 access, that is, control operations of various circuits and devices connected to the CPU bus, are possible.
PU efficiency can be greatly improved.

Note that in the above embodiment, the ROM/FRAM
Although it has a simple configuration, in reality, RAM/FRAM,
The same implementation is possible with other configurations such as RAM/IO. Furthermore, if the circuit scale becomes large, for example, if there are many RAM blocks, the stop condition circuit 64 may be replaced with the one shown in FIG.
As shown in FIG.
8a and an OR gate 64b which takes the logical sum of their outputs.
It should be composed of

[0036] Furthermore, the accessing side also has CPU/DM
Not only AC, but also CPU/CPU and DMAC/DMAC
etc. are also possible.

Furthermore, although the above embodiment has been described with reference to the case where it is applied to a page printer, it goes without saying that the present invention can be similarly applied to other data processing apparatuses.

[0038]

[Effects of the Invention] As detailed above, according to the present invention,
As long as bus collision does not occur, it is possible to provide a memory access control circuit that enables the CPU to operate and efficiently operates the CPU.

Such a memory access circuit is particularly effective when applied to a data processing device that requires high-speed processing, such as a page printer. That is, page printers are required to perform high-speed processing in the process of developing image data to be printed into a frame memory, reading out the image data for one completed page, and outputting it to the print head.
Any inefficient operation needs to be reduced. In this regard, whereas conventionally the CPU was stopped for a period when it did not need to be stopped, according to the present invention, even if the DMAC is accessing the frame memory, the CPU is enabled in the part where there is no bus conflict. Since the page printer can be operated as quickly and efficiently as possible, it is possible to improve the high-speed processing as a page printer.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a memory access circuit according to an embodiment.

FIG. 2 is a block configuration diagram of a page printer to which the memory access circuit of the embodiment is applied.

FIG. 3 is a circuit configuration diagram showing an example of a stop condition circuit.

FIG. 4 is a timing chart for explaining the operation of the embodiment.

FIG. 5 is a circuit configuration diagram showing another example of a stop condition circuit.

FIG. 6 is a block diagram of a conventional memory access circuit.

[Explanation of symbols]

32...CPU (second memory access means), 33...R
OM, 35...DMAC (first memory access means),
38... Frame memory (FRAM), 61... CPU stop circuit, 62, 63... Decoder, 64... Stop condition circuit, 6
5...AND gate.

Claims (1)

[Claims] 1. First and second memories; first and second memory access means for accessing the first and second memories via a bus at least partially common to the first and second memories; and a stop signal generating means for generating a signal to always stop the operation of the second memory access means while the memory access means accesses the first memory. a first in-operation signal generation means for generating a signal indicating that the memory access means accesses the first memory; and a signal indicating that the second memory access means accesses the first memory. The signal generated from the stop signal generating means is transmitted to the second in-operation signal generating means only when the first and second in-operating signal generating means generate their respective signals at the same time. By supplying the second memory access means to a memory access means and prohibiting the access operation of the second memory access means, the second memory access means may access a memory other than the memory accessed by the first memory access means.
1. A memory access control circuit comprising: operation control means for enabling access operations by the memory access means.