JPH05136265A - Lsi arrangement treatment - Google Patents

Abstract

PURPOSE:To reduce wirings which pass through blocks difficult for wiring to pass through by making longer a virtual wiring length of the nets passing the wire-passing difficulty blocks and not selecting the position which brings about the passing nets as the arrangement position of blocks. CONSTITUTION:Blocks 101 to 103 and a wire-passing difficulty block 301 are arranged and the blocks 101 to 104 are connected with nets 201. A block 104 has arrangement candidate positions 401, 402 is a state that the block 104 is not arranged. For example, in the case of arranging the block 104, a virtual wiring length of the net 201 when the block 104 is arranged in the arrangement candidate positions 401, 402 is obtained in order to get the values 100, 1025, respectively. When the block 104 is arranged in the arrangement candidate position 401, the net 201 passes the wire-passing difficulty block 301. Therefore, the virtual wiring length becomes 230 by adding a semi-periodical length 130 of the wire-passing difficulty block 301. Therefore, the virtual wiring length of the arrangement candidate position 402 becomes short and the block 104 is arranged in the position 402.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI layout processing method.

[0002]

2. Description of the Related Art R is used in the layout design of an LSI.
Blocks such as AM that are difficult to pass through the wiring are arranged manually in advance before the other blocks are arranged.

In the conventional placement processing method, the virtual wiring length of the net is used as an index indicating the goodness of the placement position of the block, and the position where the virtual wiring length becomes short is the placement position of the block. However, the virtual wiring length is calculated. In doing so, no consideration was given to whether or not the net would pass through the wiring difficult block (reference: “VLSI Design 1” Makoto Watanabe et al. 3 Iwanami Shoten).

That is, since the conventional placement processing method does not consider the case where the net 201 passes through the wiring passage difficult block 301 as shown in FIG. 3, the placement candidate position (see 401 in FIG. 2B) is not considered. The virtual wiring length becomes shorter, the block 104 is placed at the placement candidate position, and the net 201 passes through the wiring passage difficult block 301.

[0005]

However, in a conventional LSI layout design, it is very difficult to route a net having a large number of internal wirings such as a RAM, so that a detour wiring is performed. And cause unwiring.

That is, in the above-mentioned conventional arrangement processing method,
Since the passing net is not considered in the calculation process of the virtual wiring length, which is an indicator of the goodness of placement, the block is placed so that the net passes through the block where wiring is difficult to pass, and the bypass wiring or There is a drawback that wiring is generated.

In view of the above-mentioned drawbacks, a technical object of the present invention is to provide a wiring processing method for an LSI which reduces the number of wirings passing through a block having many internal wirings such as a RAM.

[0008]

According to the present invention, an LSI
In the layout processing method of the LSI used for the layout design, first storage means for storing layout design information, and second storage means for storing the layout position of a wiring passage difficulty block having internal wiring of a predetermined value or more, Means for extracting a placement candidate position for an unplaced block from the background,
A calculation means for calculating a virtual wiring length of a net connected to a block when a predetermined block is placed with respect to the placement candidate position, in consideration of whether or not the net passes through the wiring passage difficult block. , Among the placement candidate positions,
According to another aspect of the present invention, there is provided an LSI layout processing method, characterized in that the LSI layout processing system includes a determining unit that determines a layout position based on the virtual wiring length.

According to the present invention, in the exclusive control method for customer data according to claim 1, the calculating means calculates a virtual wiring length by adding a half circumference length of the wiring passage difficult block. An LSI layout processing method can be obtained.

Further, according to the present invention, in the customer data exclusive control method according to claim 1, the deciding means has a virtual wiring length different from a virtual wiring length of a net passing through the wiring passage difficult block. A layout processing method for an LSI is obtained, which is characterized in that the layout position corresponding to is determined.

That is, according to the present invention, in the layout design of an LSI, a means for inputting and storing layout design information, a means for inputting and storing an arrangement position of a wiring passage difficulty block, and an arrangement candidate position for an unarranged block. With respect to the arrangement candidate position,
The virtual wiring length of the net connected to the block when the block is placed is calculated from the means for calculating whether or not the net passes through the wiring passage difficult block and the placement candidate position. It has a means for deciding and arranging the arrangement position based on.

[0012]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows a flow chart of an arrangement processing method which is an embodiment of the present invention.

In the processing box 1-1, LSI layout design information is input and stored.

In the processing box 1-2, the arrangement position of the wiring passage difficult block is input and stored.

In the processing box 1-3, one unplaced block is extracted and set as an arrangement target block.

In the processing box 1-4, one placement candidate position of the placement target block is extracted from the background.

In the processing box 1-5, one net connected to the arrangement target block is extracted.

In the processing box 1-6, the virtual wiring length of the net extracted in the processing box 1-5 when the placement target block is placed at the placement candidate position extracted in the processing box 1-4, that is, the minimum surrounding the net. Find the half perimeter of a rectangle.

In the judgment box 1-7, the processing box 1
It is checked whether or not the net extracted in -5 passes the wiring passage difficult block, that is, whether the wiring passage difficult block exists in the minimum rectangle surrounding the net, and if it exists, the processing box 1- Go to 8 and if not,
Go to decision box 1-9.

In the processing box 1-8, the judgment box 1
The half perimeter of the wiring difficult block that is determined to pass in -7 is added to the virtual wiring length obtained in processing box 1-6.

In the judgment box 1-9, if all the nets connected to the placement target block have been processed, the processing advances to the judgment box 1-10, and if there are unprocessed nets, the processing box 1-5 follows. ..

In the judgment box 1-10, if all the layout candidate positions for the layout target block have been processed, the process proceeds to the processing box 1-11. If there are unprocessed layout candidate positions, the processing box 1-4 is executed. Go to

In the processing box 1-11, the placement target block is placed at the placement candidate position where the virtual wiring length obtained in the above process is the shortest.

In the judgment box 1-12, if there is an unplaced block, the process goes to the process box 1-3, and if all blocks are arranged, the process is terminated.

FIG. 2 shows an embodiment of the processing procedure of the present invention shown above.

FIG. 2A shows an example of logical connection between blocks, showing that blocks 101 to 104 are connected by a net 201.

At present, as shown in FIG. 2B, blocks 101 to 103 are arranged and a wiring passage difficulty block 301 is arranged.

Further, the block 104 is in a non-arranged state, and 401 and 402 indicate the arrangement candidate positions of the block 104.

Here, when arranging the block 104, the block 104 is arranged at the candidate positions 401 and 402.
The virtual wiring lengths of the net 201 when arranged in the above are obtained, and the values of 100 and 1025 are obtained.

In the present embodiment, when the net 201 is placed at the placement candidate position 401, the net 201 blocks the wiring passage block 301.
Therefore, the virtual wiring length at this time becomes 230 (= 100 + 130) by adding the half perimeter 130 of the wiring passage difficult block 301.

Therefore, between the placement candidate positions 401 and 402, the virtual wiring length of 402 is shorter, and the block 10
4 is arranged at the wiring candidate position 402 as shown in FIG.

As a result, the net 201 does not pass through the wiring difficult block 301.

[0034]

As described above, according to the present invention, by setting the virtual wiring length of a net that passes through a block through which wiring cannot pass easily, a position that causes the above-mentioned passing net is set as a block layout position. Since the selection is not made, the number of wirings passing through the wiring passage difficult block is reduced, and it is possible to prevent the detour wiring and the non-wiring.

[Brief description of drawings]

FIG. 1 is a flow chart of a wiring processing method according to an embodiment of the present invention.

FIG. 2 is an example of a wiring result of a block according to the present invention.

FIG. 3 is an example of a block placement result according to a conventional placement processing method.

[Explanation of symbols]

 1-1 to 12 According to the description in the figure. 101-104 block 201 net 301 wiring difficult block 401, 402 wiring candidate position of block 104

Claims (3)

[Claims] 1. An L used in a layout design of an LSI.
In the SI layout processing method, a first storage means for storing layout design information, a second storage means for storing a layout position of a wiring passage difficulty block having internal wiring of a predetermined value or more, and a layout candidate for an unplaced block A means for extracting a position from the base, and a virtual wiring length of a net connected to a block when a predetermined block is placed with respect to the placement candidate position, whether the net passes through the wiring difficult block. In consideration of the above, there is provided a calculating means for calculating, and a deciding means for deciding an arrangement position from the arrangement candidate positions based on the virtual wiring length, an LSI arrangement processing method. 2. The exclusive layout control method for customer data according to claim 1, wherein the calculating means calculates a virtual wiring length by adding a half circumference of the wiring passage difficult block. 3. The exclusive control method for customer data according to claim 1, wherein the determining unit determines an arrangement position corresponding to a virtual wiring length different from a virtual wiring length of a net that passes through the wiring passage difficult block. An LSI placement processing method characterized by making a decision.