JPH05135548A - Digital recorder - Google Patents

Abstract

PURPOSE:To provide a digital recorder which can apply the fade-out/fade-in processing to the joint parts of the sound data. CONSTITUTION:For instance, sound data stored in the hard disks 12a and 12b are read out as the event information under the control of a DMA controller 10. Then these event information are transferred to the buffers 9-1-9-3. Under such conditions, the fade-out/fade-in operation can be dynamicarry carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recorder capable of digitally recording, reproducing and further editing a voice signal, and more particularly, fade-in / fade-out with respect to an edit point of audio data or an arbitrary position. The present invention relates to a digital recorder adapted to be processed.

[0002]

2. Description of the Related Art Conventionally, as a method of recording (recording), reproducing, and editing an audio signal, an analog audio signal is magnetically recorded on a magnetic tape and then reproduced and edited. However, in such a conventional technique, since the analog recording / reproduction is used, the deterioration of the sound quality is unavoidable, and particularly when the audio signal once recorded is dubbed, the deterioration becomes remarkable.

Further, since the magnetic tape is used as a recording medium, it takes a long time to reach a target editing point, and the recording portion of the magnetic tape is physically cut and pasted, or the editing portion is changed. There is also a problem that editing work can only be done after copying once to the location.

Although the problem of sound quality deterioration can be dealt with by digitizing the recording method on the magnetic tape,
The drawbacks regarding the cueing and the degree of editing freedom that occur due to the use of the recording medium of sequential access cannot be eliminated by simple digitization.

Therefore, in recent years, a proposal has been made to solve the conventional problems by performing disk recording using a Winchester type hard disk as a recording medium (for example, JAS Journal '89 April issue, page 16). Through page 22 "Digital Audio
Trends in Workstations (DAW) ~ From AES Japan Chapter January Meeting ~ "). Furthermore, the present applicant also filed an invention disclosing disk recording in Japanese Patent Application No. 2-1237.
No. 88 (filed on May 14, 1990), Japanese Patent Application No. 3-655
No. 22 (filed on March 6, 1991) and so on.

[0006]

Then, it is considered that random access editing is performed by forming event information from the audio data stored in the above-mentioned hard disk and program-controlling the reproduction order of this event information. Has been.

However, in such a case, when it is desired to suppress the abnormal noise generated at the boundary of the event information when reproducing the data subjected to the random access editing, the data for that purpose should be prepared in advance in the disk or the memory. The problem of having to do so can occur.

Although it is conceivable to perform signal processing with an expensive DSP or the like, when outputting sound, the DSP is used.
The signal processing by means of becomes complicated in the start of the processing depending on time. This is the same not only when the boundaries of the event information are desired, but also when it is desired to obtain an effect such as fade-in / out for a specified arbitrary point.

Therefore, in order to solve the above-mentioned problems, the present invention requires a data section to be faded after transferring a data block at the beginning or the end of event information or an arbitrary designated edit point during reproduction. Another object of the present invention is to provide a digital recorder capable of performing a fade process.

[0010]

According to the digital recorder of claim 1, which has been made to solve the above-mentioned problems, a voice input / output device 8 as a voice input / output means for inputting / outputting voice data. -1 to 8-3, hard disks 12a and 12b as audio data storage means for storing audio data supplied from the audio input / output means (this may be a disk medium such as a magneto-optical disk), and audio data storage A plurality of event information is formed from the audio data stored in the means, and the CPU 1 as the control means for performing random access editing by controlling the reproduction order of the event information, and the boundary of the event information edited by the control means. For the fade data setting means for setting the fade data, the CPU 1 (step on the program And -6,5-9), the data immediately before or immediately after the data block of the boundary of the event information,
There is provided a digital recorder including a CPU 1 (step 4-2 on the program) as a data changing unit that performs a fade process and changes with the fade data set by the fade data setting unit.

According to another aspect of the present invention, there is provided a digital recorder according to claim 2, wherein the voice input / output devices 8-1 to 8 as voice input / output means for inputting / outputting voice data. -3, hard disks 12a, 12b, etc. (which can be a disk medium such as a magneto-optical disk) as audio data storage means for storing digital audio data supplied from the audio input / output means, and stored in the audio data storage means CPU 1 as a control means for performing random access editing by forming a plurality of event information from the generated audio data and controlling the reproduction order of the event information, and an arbitrary position of the audio data random access edited by the control means. CPU1 as a fade data setting means for setting fade data for Step on the Lam 5-6,5-9)
And the CPU 1 (on the program) as a data changing means for changing the data of the data block immediately before or after an arbitrary position of the random access edited audio data by the fade data set by the fade data setting means. Steps 6-4, 6-
5) A digital recorder including the above is provided.

[0012]

In the digital recorder according to the first aspect of the invention, the audio data of the data block immediately before or after the boundary of the event information is changed to preset fade data. As a result, fade-out and fade-in processing is performed at the event boundary, and abnormal noise generated at the event boundary can be effectively suppressed.

In the digital recorder according to the second aspect, the audio data of the data block immediately before or after the arbitrary position of the event information is changed to preset fade data. As a result, effects such as fade-in / fade-out can be applied to specified points, and noise that occurs in a short time, such as pop noise recorded during recording, can be effectively suppressed. You can

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the digital recorder of the present invention will be described below with reference to the drawings.

<Overall Structure> FIG. 1 shows the overall structure of an embodiment of a digital recorder of the present invention. In this embodiment, recording and reproducing operations of up to three tracks can be simultaneously performed. .. The whole is CP as shown
It is divided into a U section (left side portion in the figure) and a DMA unit (voice recording / reproducing processing device) (right side portion in the figure).

The CPU unit includes a CPU 1, a program ROM 2 storing a program (details will be described later) defining the operation of the CPU 1, an area for storing various data, and 3
An area for storing a disk access pointer of a track, identification information (event name) of each delimited audio data (event) when audio data stored in the hard disks 12a and 12b is manually or automatically divided into a plurality of pieces, and Event table (ET) including storage locations (disk ID, start data address, event length)
RAM3 including an area for storing an event sequence table (EST) in which event identification information included in the event table is arranged in an event reproduction order for each track, and a work area.
And a keyboard 4 including various function keys and data input keys, which are peripheral devices connected to the I / O port of the CPU 1, and a display device 5 including a CRT or LCD and its driver and performing various displays.

As will be described later, the CPU 1 sets the D unit, if necessary, in the idle time of the address bus and the data bus of the DMA unit during a real time operation (recording / reproducing, etc.).
The components of the MA unit are controlled, and during editing, data blocks are rearranged and disk access pointers are manipulated. From the keyboard 4, as described later, recording / recording of each track (hereinafter, referred to as Tr) /
You can set the playback mode, start, stop, locate, and specify edit points. Program ROM2, R
To the address terminal of AM3, CP via the address bus
An address signal is sent from U1, and its output terminal is connected to the CPU 1 or the transceiver 7 via the data bus.

That is, in order to connect the CPU unit and the DMA unit, the buffer 6 and the transceiver 7 are DMA-connected.
It is provided in the unit. The buffer 6 is connected to the CPU 1 via an address bus, and is further connected to the address bus in the DMA unit. Transceiver 7 is CPU
1 and a data bus in the DMA unit.

In the DMA unit, a voice input / output device 8-1 for Tr1 and a voice input / output device 8-for Tr2 are provided.
2, an audio input / output device 8-3 for Tr3 is provided, and an analog audio signal can be independently input / output to / from each.

Inside each of the audio input / output devices 8-1 to 8-3, in addition to a converter that selectively executes A / D conversion and D / A conversion, a low-pass filter for removing sampling noise and further sampling It includes a clock circuit that generates a clock at a cycle. These voice input / output devices 8
In -1 to 8-3, if the track is set to the record state, the analog audio signal from the outside is appropriately filtered every sampling cycle, and then A
/ D conversion is performed to obtain digital audio data. On the contrary, if the track is set to the play state, the digital audio data read in advance is reproduced at every sampling cycle.
After A / A conversion and appropriate filtering, it is output as an analog audio signal.

Each voice input / output device 8-1 of Tr1 to Tr3
8-3 are corresponding buffers 9-through the data bus
1 (BUF1), the buffer 9-2 (BUF2), and the buffer 9-3 (BUF3), respectively, and exchanges digital audio data.

The buffers 9-1 to 9-3 are Tr1 to T, respectively.
r3 and voice input / output devices 8-1 to 8-
Data transfer to and from the control unit 3, D
Direct memory access (DM
A) method is used.

The respective voice input / output devices 8-1 to 8-3 are
For the DMA controller 10, at the time of recording, the audio input / output devices 8-1 to 8-3 are used at a sampling cycle.
DMA transfer of digital data from sampling to buffers 9-1 to 9-3 in one direction (single transfer)
Request (request) and send DRQ signal (Tr1
DRQ1, Tr2 DRQ2, Tr3 DRQ
3 is given to the DMA controller 10)), D
Answer from MA controller 10 (acknowledge
The actual data transfer is executed by receiving DAK1 in Tr1, DAK2 in Tr2, and DAK3 in Tr3 as DAK3). At the time of play, a request for DMA transfer (single transfer) of digital data for one sampling from the buffers 9-1 to 9-3 toward the audio input / output devices 8-1 to 8-3 at the sampling cycle is received by the audio input. Data is transferred from the output devices 8-1 to 8-3 by the DMA controller 10 as in the case described above.

The buffers 9-1 to 9-3 have a capacity capable of storing digital audio data once or a plurality of times. For example, the RAM is divided into Tr1 to Tr3 and divided into ring buffers (final address and start address). FIF is used as a buffer that is virtually connected to
It is configured to function as an O buffer.

Addressing for the buffers 9-1 to 9-3 is performed by the DMA controller 10 or the like via the address bus. That is, during the DMA transfer, the DMA controller 10 occupies the address bus, the data bus, and the control signal line in the DMA unit.

The buffers 9-1 to 9-3 are connected via a data bus to a hard disk controller (hereinafter referred to as H
Data is exchanged with the hard disks 12a and 12b under the control of the D controller 11). The hard disks 12a, 12b and the HD controller 11 are connected via a data bus and a control signal line, and the HD controller 11 performs all read / write access to the hard disks 12a, 12b. The hard disks 12a and 12b have storage areas divided into three tracks of Tr1 to Tr3, and data transfer with the buffers 9-1 to 9-3 is performed by the DMA controller 1
Made by 0. This is the HD controller 11
When the transfer of one data block is completed, an interrupt (INT) is issued to the CPU 1 and the transfer instruction of the next data block is sent to CP.
This is done by doing for U1. CPU1 is HD
When the interrupt signal INT comes from the controller 11, the DMA controller 10 and the HD controller 11
Is set to a desired state or programmed, and then DMA transfer is performed. The details of this operation will be described later.

At the time of play, the DMA controller 10 reads out a predetermined amount (a plurality of sampling periods) of digital audio data from the hard disks 12a and 12b, and then specifies one of the buffers 9-1 to 9-3. Of the hard disk 12a, 1 by reading a predetermined amount (a plurality of sampling periods) of digital audio data from the designated buffer at the time of recording.
It operates so as to perform DMA transfer (block transfer) to the designated position of 2b.

At the time of data transfer between the hard disks 12a and 12b and the buffers 9-1 to 9-3, the HD controller 11 outputs a request signal DREQ to the DMA controller 10 (on the DMA controller 10 side, as DRQ4). On the contrary, when the transfer becomes possible, the reply signal DACK is received (D on the DMA controller 10 side).
By outputting as AK4), the actual transfer state is achieved.

In this way, the DMA controller 10
Three channels between the voice input / output devices 8-1 to 8-3 of Tr1 to Tr3 and the buffers 9-1 to 9-3 (see C described later).
H1 to CH3) data transfer, and any of the buffers 9-1 to 9-3 and the hard disk 12 selected in order.
The time division data transfer operation of a total of 4 channels is performed with the data transfer of 1 channel (CH4 described later) between a and 12b.

The CPU 1 gives an address signal to the buffer 6 via the address bus in order to manage the function and action of each constituent element in the DMA unit, and sends a designation signal of each constituent element to the decoder 13 via the buffer 6. Supply
The respective designation signals CS are sent to the respective voice input / output devices 8-1 to 8-
3, buffers 9-1 to 9-3, DMA controller 1
0, which is given to the HD controller 11. At the same time, various kinds of data are exchanged with the CPU 1 via the transceiver 7 and the data bus.

Further, from the CPU 1 to each voice input / output device 8-
A designation signal WR for designating a record state (write state) or a play state (read state) is applied to the IOWR terminals 1 to 8-3 via the buffer 6.

Further, each of the buffers 9-1 to 9-3 and the DMA
This designation signal (write signal) WR and another designation signal (read signal) RD are also given to the controller 10 and the HD controller 11 from the CPU 1 via the buffer 6, and data is read from each component. On the contrary, data will be written. The DMA controller 10 also outputs these designation signals RD and WR in the DMA transfer state. The relationship between these signals and the function and operation of each component will be described later.

The DMA controller 10 sets the DMA enable (enabling) signal DMAENB to "1" and outputs it when the DMA transfer is being performed between the respective constituent elements. As a result, the output of the AND gate 14 to which this signal DMAENB is given via the inverter 16 becomes "0",
The enabling signal E is supplied to the buffer 6 and the transceiver 7.
Is given as "0", so that it becomes impossible to exchange data and address between the CPU unit and the DMA unit. At this time, if the "1" signal is given to the AND gate 15 from the decoder 13, the output of the AND gate 15 becomes "1" and the wait signal WAIT is supplied to the CPU 1.

That is, when the CPU 1 gives a predetermined signal to the decoder 13 to open the buffer 6 and the transceiver 7 in order to manage the DMA unit, that is, the decoder 13 outputs "1" to one input terminal of the AND gate 14. ”
When a signal is being supplied (CPU 1 has buffers 9-1 to 9-1
9-3, DMA controller 10, HD controller 1
1. When an address signal for accessing any one of the voice input / output devices 8-1 to 8-3 is output, the decoder 13
Output becomes active and the output to the respective one input terminals of the AND gates 14 and 15 becomes "1"), and when DMA transfer is started, a wait (WAIT) is applied to the CPU 1 and the DMA transfer is preferentially executed. After that, the operation of the CPU 1 is restarted when the wait is released.

On the contrary, the DMA controller 10
When executing the MA transfer, the CPU 1 sends the DM
Even if an attempt is made to access the A controller 10, the wait signal WAIT is given from the AND gate 15 and the CPU
One execution cycle is extended midway, and the buffer 6 and the transceiver 7 are closed during that time.

After all, the CPU 1 can access each component of the DMA unit as follows. CPU1 issued an address for accessing each component of the DMA unit. 2. The signal DMAENB is inactive (“0”), that is, the data bus of the DMA unit is empty. When the two conditions are satisfied, the CPU 1 operates as described above when the D
The processing can be proceeded without considering whether to access the MA unit.

Further, when the CPU 1 wants to immediately change the operating state of the DMA unit in response to a key input or a trigger of control data, the CPU 1 can be in any state with respect to the DMA controller 10. A command DMAEND for interrupting the DMA transfer can be output (this is given to the DMA controller 10 as the END signal).

<Main Configuration of DMA Controller 10> Next, a configuration example of the DMA controller 10 will be described. D
The MA controller 10 has a transfer capability in which one bus cycle is several hundred nanoseconds. Therefore, the time for transferring the sampling data for three tracks is 1 to 2 microseconds.

When the sampling frequency fs is 48 KHz, the interval of one sampling time is about 21 microseconds, and most of the sampling time intervals are the buffers 9-1 to 9-3, the HD controller 11, and the hard disks 12a and 12b. It becomes possible to devote to the data transfer between them and the programming time of each component from the CPU 1.

Now, the main structure of the specific example is shown in FIG. The DMA controller 10 includes an input side (IN) address buffer 10 connected to an address bus.
1 and an output side (OUT) address buffer 102. The specified content of the register selector 103 is changed by the address signal given to the address buffer 101 on the input side, and a desired register existing in the address register 104 and the control register 105 is specified.

The address register 104 and the control register 105 have areas of four channels CH1 to CH4, and the channels CH1 to CH3 are buffer 9
-1 to 9-3 and the voice input / output devices 8-1 to 8-3 are registers for performing DMA transfer between the channels C and
H4 is a register for performing DMA transfer between the designated buffer among the buffers 9-1 to 9-3 and the hard disks 12a and 12b.

The registers of the respective channels CH1 to CH4 in the address register 104 are corresponding buffers 9-1.
9-3 and an area for storing at least the current address and start address of the designated buffer, the CH4 register is further provided with a transfer counter, and the number of data set to this counter is DM.
After the A transfer, even if the DMA request from the HD controller 11 continues, the DMA operation is stopped until a new counter is set (by 8-8 in FIG. 8 described later). In addition, each channel CH1 to C of the control register 105
In the area H4, for example, control data designating the direction of DMA transfer is stored.

The contents of the address register 104 and the control register 105 can be input to and output from the data bus via the data buffer 106. The timing control logic 107, the service controller 108, and the channel selector 109 control each of these components.

The service controller 108 has a hard logic or micro program control configuration, and signals from the timing control logic 107, voice input / output devices 8-1 to 8-3, and DMA request signals DRQ1 to DRQ1 from the HD controller 11 are provided. DRQ4 and CP
A DMA interrupt command END (DMAEND) from U1 is received, reply (acknowledge) signals DAK1 to DAK4 to the above-mentioned respective components, and DM indicating that DMA transfer is in progress.
In addition to outputting the A enable (enabling) signal DMAENB, it outputs various commands to the timing control logic 107 and outputs a channel select signal to the channel selector 109. The channel selector 109 includes channels CH1 to CH4 in the address register 104 and the control register 105.
Select the register corresponding to.

Timing control logic 107
Receives the designation signal CS from the decoder 13, the control signal from the control register 105, and the control signal from the service controller 108, controls input / output of the address buffer 102 and the data buffer 106, and operates the address incrementer 110. Then, the current address register of the designated channel in the address register 104 is incremented, and when the end address of the buffer assigned to the channel is reached, it is reset to the start address of the buffer assigned to the channel. ..

<Overall Operation of CPU 1> The operation of this embodiment will be described below. Flow charts showing the operation of the CPU 1 are shown in FIGS. This is a program (software) stored in the program ROM2
3 shows the main routine, and FIG. 4 shows HD.
The interrupt routine executed in response to the arrival of the interrupt signal INT from the controller 11 is shown. 5 shows in more detail some steps 4-4 of the interrupt routine shown in FIG. 4, and FIG. 6 shows some steps 5-4 in FIG. 5 of setting fade data at arbitrary edit points. -12 is shown in more detail.

First, in FIG. 3, the CPU 1 starts the main routine in response to the power-on, and proceeds to step 3-0.
Various initial states are set in (hereinafter, simply referred to as 3-0). Then, the key input is received in 3-1 and 3-
In 2, it is determined which mode is set.

When the CPU 1 judges that it is currently in the play / record mode, it proceeds from 3-2 to 3-3 to sequentially select and designate three tracks, and further proceeds to 3-4 to set the operation mode of each track to the keyboard 4. Is set in accordance with the input instruction of the above, and in 3-5, which of the A / D conversion and the D / A conversion is to be performed by each of the audio input / output devices 8-1 to 8-3, the buffer 6 and the decoder 13 Then, IOWR is given and set while sequentially sending the designation signal CS. Now, for example, Tr1 is in a play state (hence, D / A conversion operation state), and Tr2 and Tr3 are in a record state (hence, A / D conversion operation state). Figure 1
FIG. 0 shows a conceptual diagram of a schematic operation when such a mode is set.

Then, in 3-5, the DMA controller 1
0 to the buffer 9-1 for each Tr1 to Tr3
Initialize addresses 9-3. That is, the channels CH1 to C are selected by the address buffer 101, the register selector 103, the channel selector 109, etc. of FIG.
The initial setting data is input and set via the data buffer 106 while designating each register of H3 (address register 104, control register 105).

Here, the buffers 9-1 to 9-3 are cyclically used as ring buffers. In the initial state, the start addresses and currents of the buffers 9-1 to 9-3 are set. It is set to match the address (in FIG. 10, the start address and the current address of each of the buffers 9-1 to 9-3 are CH1 to CH
3 schematically shows the state of being stored and controlled in the address register 104 of No. 3).

Subsequently, the CPU 1 executes the processing of 3-6,
Each track Tr1 to Tr of the hard disks 12a and 12b existing in the work memory area in the RAM 3
A disk access pointer corresponding to No. 3 is initialized (FIG. 10 shows the relationship between the storage areas of the hard disks 12a and 12b and the disk access pointer).

Next, the CPU 1 controls each voice input / output device 8-1.
8-3 starts the A / D conversion operation or D / A conversion operation (3-7). Subsequently, in 3-8, a software interrupt is issued to cause the HD controller 11 to request a program for data transfer between the hard disks 12a and 12b and one of the buffers 9-1 to 9-3 (the HD controller 11 sends the CPU 1 to the CPU 1). The same processing as that performed when (interrupt INT is applied) is performed (described later) is executed.

Specifically, the operation according to the flow charts shown in FIGS. 4 to 6 is executed in 3-8.
Here, before entering the description of the flowcharts shown in FIGS. 4 to 6, the configuration of each table stored in the RAM 3 of FIG. 1 will be described. The RAM 3 shown in FIG.
2 to 15, an event table (ET) and an event sequence table (EST) for controlling the reproduction schedule are defined, and a memory area for current data, which is intermediate data between them, is taken. There is.

That is, FIG. 12 shows an example of registration of the above-mentioned event table, and the event data stored in this table includes an event name (name), a disk ID (id) (hard disks 12a (00) and 12b).
(Specify any of (01)), start data address (sample (word) data address) (adrs),
And the event length (sample data number) (vol). In the event table shown in FIG. 12, original recording data "1" to "4" are automatically created by securing an area during recording.

Further, FIG. 13 shows an example of the EST of the original recording data, and the EST index (EST Index) from "0" to "2" in the horizontal direction.
However, each track number is arranged in the vertical direction, and the event number is stored corresponding to each. In FIG.
For example, the data of track 2 are the discs "00" and "0".
1 shows the state recorded over 1 ", and the event number" 0 "is for indicating the end of the sequence element.

In addition, FIG. 14 shows an edited work 1 in which the user defines the event by himself and arranges them on the track to be output.
13 shows an example of the EST of FIG. 13, the EST indexes of “0” to “8” are arranged in the horizontal direction, the track numbers are arranged in the vertical direction, and the event numbers are stored correspondingly. .. Therefore, as described above, a plurality of ESTs can exist corresponding to edited works.

Furthermore, FIG. 15 shows the current data when the DMA transfer is actually performed, and shows the index number of the EST to be the next transfer target of each track and how much the event is transferred. The already-transferred amount shown is stored.

The fade processing operation of the CPU 1 when the user-defined event sequence shown in FIG. 14 is reproduced will be described below with reference to the flow charts shown in FIGS. 4 and 5. Particularly, FIGS. 4 and 5 are shown with emphasis on the reproducing operation.

First, the CPU 1 determines whether or not there is a fade request (this request is stored in 4-10 as described later) (4-1). If there is a fade request, the process proceeds to step 4-2, and according to the fade data set in steps 5-6 and 5-9 of FIG. 5 described later, the process of changing the buffer data, that is, the fade-in process or Performs fade-out processing. If it is judged in step 4-1 that there is no fade request, the process of step 4-2 is omitted.
Next, the CPU 1 determines the transfer track in step 4-3. That is, for example, for Tr1,
In order to DMA transfer the digital signal data from the hard disks 12a and 12b to the buffer 9-1, the channel CH1 corresponding to Tr1 is determined as the channel of the DMA controller 10.

Subsequently, the step 4-4 is performed in which the disk ID, the word address, and the transfer address are obtained from the track number and the free capacity (transferable capacity) of the channel buffer, or the boundary of the event is detected to set the fade data. Run. The flow of these steps 4-4 is shown in more detail in FIG. The free space of the buffer is assumed to be rounded down in units of sectors.

That is, in step 5-1 the EST index is obtained from the current data (FIG. 15) of the corresponding track (Tr1 in this case), and E
The event number corresponding to the EST index is obtained from ST (FIG. 14). Then, in step 5-2, a disk ID corresponding to the event number is obtained from the event table shown in FIG. 12, and then "event start address + current data transfer amount = word address" is calculated to obtain the word address. Ask for. The start address of the event is a in the event table shown in FIG.
drs, and the already transferred amount of the current data is obtained from the current data shown in FIG.

In step 5-3, the CPU 1 obtains an offset from the word address (the word address is composed of a portion indicating a sector and an offset portion indicating the position within the sector), and then "event capacity-existing". Transfer amount = untransferred amount ”is calculated to obtain the untransferred amount. The event capacity is obtained from the vol of the event table in FIG. 12, and the transferred amount is obtained from the current data in FIG.

Here, in 5-4, it is judged whether or not "free space> untransferred amount". NO in 5-4
If it is judged that the event end has not been reached, it is next determined whether or not the transferred amount = 0 (5-5). If this is judged as YES, it is the beginning of the event and the fade-in data is set (5-
6). With this setting, for example what kind of envelope,
It is determined how much time (how many samples) is changed. If NO in 5-5, the process in 5-6 is omitted. Then, in 5-7, the already-transferred amount is set by the calculation of "already-transferred amount = currently-transferred amount of current data + free space-offset", and further, in 5-8, "transfer word number = free space-offset" is set. In this manner, the sector-by-sector transfer enables transfer from any position in the sector. The free space is rounded down to the size of a sector unit.

Further, YES in step 5-4.
If you judge, it is judged that the end of the event has been reached,
In 5-9, the fade-out data is set. With this setting, for example, what envelope and how much time (how many samples) is changed are determined. Then, in 5-10, the EST of the current data
The index of 1 is incremented by 1, and the transferred amount is set to 0. Next, in 5-11, "the number of transfer words = the untransferred amount" is set.

After the steps 5-8 and 5-11, as indicated by a broken line, step 5-12 is entered as necessary. In steps 5-12, the fade processing is performed not only at the boundary of the event but at an arbitrary point designated during editing. That is, at which position (for which the event reproduction arrangement has been completed) the fade processing is to be specified in advance during editing. This is specified by the sample number after the start of playback. Further, the fade-in process or the fade-out process is designated for the position.

The step 5-12 shows the processing added at the time of reproduction, and the details of the step 5-12 are shown in FIG. That is, in 6-1 of FIG. 6, the number of transfer words is added to the accumulated transfer amount. The accumulated transfer amount is reset to "0" each time the reproducing operation is started, and represents the total number of data transfer words up to that point. Then, next, it is judged (6-2) whether or not the transfer amount obtained by the processing of 6-1 coincides with the point designated as the editing point. If YES is judged at this time, the process proceeds to 6-3, and it is judged whether the operation instruction is fade-in or fade-out. If the operation instruction is fade-in, the fade-in data is set (6-4), and if the operation instruction is fade-out, the fade-out data is set (6-5). The setting in this case is also step 5-6,5-
The same is done as in 9. Further, in the case of being judged as NO in the above 6-2, the above 6-3 to 6
The judgment and processing of -5 are omitted.

Returning to FIG. 4, in 4-5, the word address is corrected to the disk address and the offset, and the number of transfer sectors is obtained from the number of transfer words. Further, in 4-6, the HD controller 11 is programmed by the disk address, the number of transfer sectors, and the track mode. Here, in 4-7, it is judged whether or not “offset = 0”, and the position of the beginning of the event does not coincide with the boundary of the sector. Therefore, when judged as NO, the position of the beginning of the event is odd. It is a sector that contains various data.
And if there is such a half, 4-11 and 4-
At 12, the CH4 start address of the address register 104 in the DMA controller 10 is set in the image (actually does not exist) area, the offset value is set in the transfer counter, and the odd data, that is, the offset value is set. Dummy transfer data.

If it is determined in 4-12 that the dummy transfer is completed, or if it is judged YES in 4-7 (when "offset = 0"), 4-8
Then, the start address of the CH (in this case, CH1) of the address register 104 is copied to the start address of CH4. Then, the value of the transfer counter is set to the value of “number of sectors × sector length−offset value”. Further, in 4-9, the start address of the CH is updated from the number of transfer words. Then, in 4-10, if the fade process is necessary, the fade process request is stored, and the process returns to the main routine (FIG. 3). That is, since the CPU 1 can detect the transfer end only by the transfer end interrupt, the fade process request is stored, and the fade process request is stored later (step 4-1).
Perform the fade process (at 4-2).

As described above, when the event boundary is detected and the fade data is set in 4-4, the target processing is performed after the transfer processing up to 4-9. For example, in FIG.
As shown in (A), the last block D of an event
Of the block D, the shaded block E is faded out. That is, FIG. 11 (C)
As shown in (1), the head part to be faded is multiplied by 1 (0d
B), the last data of the event is 0 times (-∞d
The multiplication as shown in B) is performed on each data.

Further, as shown in FIG. 11B, when the block F at the beginning of the event is transferred,
Fade-in processing is performed after the hatched portion G at the beginning of F shown in (B) is transferred. That is, as shown in FIG. 11C, multiplication is performed so that the start data of the event is 0 times and the end of the fade-in area is 1 time.

If the multiplication process performed by the CPU 1 takes too much time, the current address (current tone generation data) reaches the block currently being processed during the repetition of the multiplication process, and the data transfer cannot be completed in time. There is a thing. However, the processing of fade-in / out to prevent abnormal noise is at most several tens to several hundreds of samples, and the processing of μS to 1 mS is required from the CPU performance for the disk access time of several tens mS. It is fully possible and does not significantly affect the disc transfer sequence. Further, the calculation for the fade process may be performed by the CPU using hardware instead of the CPU.

By the way, step 4-11 in FIG.
In this case, dummy transfer is performed in the image area (address area that does not actually exist). This is the same effect even if the data is transferred to an area other than the unvoiced data in the buffer instead of the image area, but in this case, the start address is set from the register 104 of the DMA controller 10 each time. I have to get it. However, in the case of the image area, the start address is set to a fixed value indicating the beginning of the image area, and only the transfer counter of the address register 104 needs to be programmed, which is slightly efficient.

Next, returning to FIG. As will be apparent from the description below, once the first interrupt routine (FIG. 4) is activated and the HD controller 11 is moved once, the HD controller 11 then moves to the HD controller 11 each time the data block transfer is completed. Since an interrupt is made from 11 (INT signal is given to CPU1), CPU1
Is performed only to determine whether the recording / playback operation has ended, whether there has been a key input, or whether the trigger specified in the control data has occurred.

That is, the CPU 1 refers to the disk access pointer (RAM 3) at 3-9 and judges whether or not the memory area is over, that is, whether or not the memory area is over (3-10). Output device 8-
Stop A / D conversion and D / A conversion operations of 1-8-3 (3-
11) Then, return to 3-1. In the case of NO, the key input state is referred to (3-12). If there is no change, the process returns to 3-9 to check the disk access pointer, and the steps 3-9 to 3-13 are repeated.

If there is any change in 3-13, the process proceeds from 3-13 to 3-14, and the CPU 1 sends DM
In order to temporarily suspend the A transfer and make a new setting, a DMA stop command (DMAEN) is issued to the DMA controller 10.
D) is output. Then, follow the new input instructions, etc.
DMA controller 10, voice input / output devices 8-1 to 8-
3 is programmed (3-15), the process proceeds to 3-16 to restart the DMA operation again, the interrupt routine of FIG. 4 is executed similarly to 3-8 described above, and then the process returns to 3-9.

As described above, the CPU 1 makes 3-9, 3-10, 3-12, 3-13, and 3 after the initialization of 3-4 to 3-8 at the time of play / record. -1
4 to 3-16 are repeatedly executed, and a change instruction on the keyboard 4 (for example, pause (A / D,
D / A interruption) or punch in / out (A / D,
In response to a change in the D / A operation)) or a change in the control data obtained during editing, the DMA transfer control is immediately interrupted, the program is changed, and the same processing is executed again. Operate.

In 3-2, when the CPU 1 judges that it is currently in the event processing mode, 3-2 to 3-17.
Then, the sound data stored in the hard disks 12a and 12b is converted into an event. Eventification refers to an event name, a disc ID, and a segmented section for segmenting continuous audio data on the time axis into a plurality of pieces by a manual designation operation and identifying each segmented audio data (event). It means creating data (start point and its length (volume)). An event table (FIG. 12) is created in 3-18 corresponding to the event conversion. Event names, disk IDs, start points, and volumes are registered in this event table (ET). The disk ID, the start point and the volume correspond to the start address and the event length of the hard disks 12a and 12b in which the event is stored.

Then, in 3-19, based on the event table, the event sequence table EST
(FIG. 14) is created. This event process 3-17 ~
3-19 will be repeated, but if the end of the creation of the EST is detected in 3-20 by the instruction of the operator, C
PU1 checks the key input again in 3-1.

In 3-2, when the CPU 1 judges that it is currently in the edit (EDIT) mode, 3-2 to 3-3
Proceed to -21 to edit the track or point to be edited and what kind of editing is to be performed (for example, the timing of the sound recorded at a specified point for a certain time can be shifted back and forth, corrected,
The CPU 1 judges that it should be deleted) and executes various editing work (3-22). Although this editing work is not described in detail, a program of read access points from the hard disks 12a and 12b to the HD controller 11 and the DMA controller 10, transfer to the RAM3, various edits using the RAM3, and post-editing CPU 1 performs re-storing work of the digital audio data of the above into the hard disks 12a and 12b, designation of an access point, etc.
Run under the control of. When the end of the editing work is detected in 3-23, the CPU 1 checks the key input again in 3-1.

<Operations of the voice input / output devices 8-1 to 8-3>
Next, with reference to FIG. 7, operation states of the voice input / output devices 8-1 to 8-3 will be described. This flow chart may be based on microprogram control or hard logic control, and various function realizing means can be selected.

Now, in 7-1, it is judged whether or not the designation signal CS of the voice input / output device has come from the CPU 1 (is active), and if YES, 7-
In 2, the operating state (record, play, stop, etc.) is set by the CPU 1. This is the CPU1 of FIG.
This is done in response to 3-5 and 3-15 in the main routine of.

When NO is determined in 7-1, the voice input / output devices 8-1 to 8-8 are referred to in 7-3.
-3 is in a record state or a play state, and when it is determined to be a record state, 7-3 to 7-4
~ It progresses to the processing of 7-9, and when it is judged that it is a play state, 7-
The process proceeds to 10 to 7-15.

First, the operation of the voice input / output device set in the record state (in this case, the voice input / output devices 8-2 and 8-3) will be described. In 7-4, it is judged whether or not the sampling time has come, and this 7-4 is repeated until the sampling time comes. The determination of the sampling time may be performed by outputting a hard timer in each of the voice input / output devices 8-1 to 8-3, or a common hard timer may be provided and each voice input / output device may operate in accordance with the output. You may make it operate. As will be understood from the description below, the voice input / output devices 8-1 to 8-
It is also possible to make the sampling frequencies of 3 different.

If YES is determined in 7-4, the applied analog audio signal is sampled and held (S / H) and A / D converted. Then, 7-
At 6, the DMA transfer request DRQ is activated and output to the DMA controller 10.

The DMA controller 10 receives the request signal DRQ and outputs a response signal DAK for performing the DMA transfer. Therefore, the voice input / output devices 8-1 to 8-1
8-3 (in this case, the voice input / output device 8-2 or 8-3 in the record state), if the judgment of 7-7 is YES, the process proceeds to 7-8, and the digital signal obtained by A / D conversion is obtained. Outputs audio data to the data bus, and corresponding buffers 9-1 to 9-1
9-3 (buffer 9-2 or 9-3 in this case). Then, in 7-9, the DMA transfer request DRQ is made inactive. Therefore, in the present case, in the voice input / output devices 8-2 and 8-3,
An analog audio signal given from the outside is converted into a digital audio signal and transferred to the current addresses of the buffers 9-2 and 9-3 designated by the DMA controller 10 as described later (see FIG. 10).

When it is judged in the play state in 7-3, the process proceeds to 7-10, activates the DMA transfer request DRQ to the DMA controller 10, and waits for the arrival of the reply signal DAK from the DMA controller 10 (7 −
11), the digital voice data on the data bus is taken in (7-12), and the request DRQ is made inactive (7-13). The operation of the DMA controller 10 at this time will be described later, but in the present case, as shown in FIG.
The contents of the current address of the buffer 9-1 corresponding to 1 (this is already Tr1 of the hard disks 12a, 12b).
The contents of the area (1) are transferred and recorded), and are input and set in the voice input / output device 8-1 by the above operation.
Then, it is determined whether or not the sampling time has come (7
-14). The detection of the arrival of this sampling time is 7-
Same as described in 4.

Then, if YES in 7-14, 7-1
In step 5, D / A conversion and low-pass filtering are performed, and then the analog audio signal is output to the outside.

The operation at one sampling time in the case of the record state and the case of the play state has been described above. Return to 7-1 after the completion of each processing of 7-9 and 7-15, and so on. The processing for the sampling time is executed one after another.

<Operation of DMA Controller 10> Next,
The operation of the DMA controller 10 will be described with reference to FIG. The flowchart of FIG. 8 may represent that the service controller 108 of FIG. 2 operates under microprogram control, or the DMA controller 10 may implement the function by hard logic.

First, in 8-1, the designation signal CS from the CPU 1 arrives (becomes active).
If YES, it is determined which of the read signal RD and the write signal WR is given from the CPU 1 (8-2). If the read signal RD, the process proceeds to 8-3, and the address bus is used. The contents of the registers 104 and 105 designated by the given address signal are output via the data bus so that the CPU 1 can read it. On the contrary, if the write signal WR, the process proceeds to 8-4, and the designated register receives the data bus. The desired data is input and set via. The processing of 8-3 and 8-4 corresponds to the processing of 3-5 and 3-15 of the main routine of the CPU 1. Therefore, the registers 104, 1 of FIG.
Desired data is set in 05.

Then, the DMA from the CPU 1
When the access to the controller 10 or the program is completed, the designation signal CS becomes inactive, and 8-1 to 8
The process proceeds to -5.

In 8-5, each of the voice input / output devices 8-1 to 8-8
-3 from the DMA transfer requests DRQ1 to DRQ3, or the HD controller 11 sends the DMA transfer request DREQ.
(DRQ4) is judged, and if there is a request from any one, the process proceeds to 8-6, and the DMA enable signal DMA
ENB is set to "1" (active), and the address bus and data bus in the DMA unit are set to the DMA controller 1
0 is exclusively used, and access from the CPU 1 is not accepted.

Then, when a plurality of requests are made, the channels are selected in accordance with the priority order of the channels CH1 to CH4 (8-7).

Next, CH4 of the address register 104
Is selected and whether the value of the transfer counter provided in CH4 is "0" or not is determined (8-8). Here, CH4 is selected and the value of the transfer counter is "0".
If so, that is, after the transfer of the amount of data to be transferred is completed by CH4, even if there is a transfer request, the process returns to 8-5 without transferring, and 8-5 to 8-8 Repeat the routine. If CH4 is not selected, or if CH4 is selected but the value of the transfer counter is not "0", the current address (address register 10) of the selected channel (for example, CH2) is selected.
The contents of the current address register of CH2 of 4) are output to the address bus (8-9). And the control register 1 of the selected channel (for example, CH2 now)
The direction of the DMA transfer is determined by referring to the contents of 05 (8-10). If the transfer is from the buffers 9-1 to 9-3 to another element (I / O), the process is started from 8-11. 8-1
2, the read signal RD is given to the selected buffer among the buffers 9-1 to 9-3, and conversely from the other element (I / O) to the buffers 9-1 to 9-3. If it is a transfer, proceed to 8-13 and write signal W to the buffer.
Give R.

Thereafter, the response signal DAK is activated (8-14). As a result, in this case, the audio input / output device 8-2 of Tr2 sends the sampled audio data to the data bus by the processing of 7-7 and 7-8 (FIG. 7), and outputs the current of the buffer 9-2. The DMA controller 10 will write in the address area (see FIG. 1).
0).

At 8-15, since the data transfer is completed, the read signal RD or write signal WR and the reply signal DAK are made inactive, and at 8-16, the current address of the channel (now CH2) (address of FIG. 2). The content of (in register 104) is set to +1 and after reaching the end address of the buffer, it is reset to the buffer start address. By the operation of 8-16, the buffers 9-1 to 9-9
-3 each time new sampling voice data is written, or each time new voice data is read,
It will be reset to the upcount or buffer start address. Then, after the processing of 8-16, 8-
Return to 1.

In the previous state, the data transfer request is transmitted from the voice input / output devices 8-2 and 8-3 of Tr2 and Tr3 by DMA.
This is done for the controller 10, and so far T
Since the data transfer is executed only for r2, YES is determined in the following 8-5. Below T
Regarding r3, the voice input / output device 8-3 to the buffer 9-
Data transfer in the direction of 3 is 8-7 to 8-11, 8-1
This is performed in the same manner as in the above case by executing steps 3 to 8-16.

When such data transfer is completed, 8-
From 5 to 8-17, the DMA enable signal is set to "0" (inactive), the data bus in the DMA unit,
The exclusive use of the address bus by the DMA controller 10 is stopped so that the access from the CPU 1 can be accepted.

As for Tr2 and Tr3, the buffers 9-2 corresponding to the voice input / output devices 8-2 and 8-3, respectively, have been described above.
Although the data transfer to 9-3 has been described, conversely for Tr1, the buffer 9-1 to the voice input / output device 8-
Data transfer to 1 is performed by the DMA controller 10.

The CPU 1 includes the buffers 9-1 to 9-3 and the hard disks 12a, 12 corresponding to the track in operation.
Data transfer to and from b is sequentially performed for each track, and data transfer is performed for each track following the previous data transfer (block transfer). In the example of FIG. 10, for example, for Tr1, the hard disk 12
From a and 12b, the data amount corresponding to the blank portion between the start address (CH1) and the current address (CH1) shown in the figure will be transferred from now on (the other data transfer direction is also opposite). However, it is clear that similar control is performed). In the play mode buffer (corresponding to 9-1) and the record mode buffer (corresponding to 9-2 and 9-3), the shaded portion corresponds to the data portion to which voice is input.

When the DMA controller 10 detects that there is a transfer request from the HD controller 11 at 8-5, it performs the steps 8-6 to 8-1 in the same manner as the above case.
After executing 0, a request for data transfer from the buffers 9-1 to 9-3 to the hard disks 12a and 12b, or from the hard disks 12a and 12b to the buffers 9-1 to 9-.
In 8-11, it is judged whether the request is for data transfer in three directions. In the former case, the process proceeds to 8-12, and in the latter case, the process proceeds to 8-13, and then each process of 8-14 to 8-16 is executed. At this time, for example, one sample of digital audio data is transferred by one transfer operation.
The operation of 6 is repeatedly executed a plurality of times to perform block transfer.

When the DMA transfer is completed, the request signals DRQ1 to DRQ4 do not arrive, and 8-5 to 8-17
Then, the process proceeds to and the DMA enable signal DMAENB is set to "0" (inactive).

<Operation of HD Controller 11> Next, the operation of the HD controller 11 will be described with reference to FIG.
The HD controller 11 may be implemented by hardware logic or microprogram control, and in any case, realizes the function of the operation flow of FIG.

First, it is judged whether the designation signal CS is given from the CPU 1 (9-1). This is given in the interrupt routine of the CPU 1. If NO, the process returns to the original state, but if YES, the process proceeds to 9-2, where the read signal RD is given from the CPU 1 or the write signal WR.
Is read, the designated data (contents of the address register, etc.) inside the HD controller 11 is output to the CPU 1 via the data bus at the time of reading.

Further, when the write signal WR is given, the process proceeds from 9-2 to 9-4 to set the data transfer direction between the buffer for DMA transfer on the channel CH4 of the DMA controller 10 and the hard disks 12a, 12b this time. Then, at 9-5, the hard disk 12 to be accessed
Set access points a and 12b. This is C
According to the disk access pointer of the track that PU1 has obtained from RAM3.

Subsequently, at 9-6, the number of transfer data (the number of digital audio data) is set in the internal counter of the HD controller 11. This transfer data number is obtained in the interrupt routine of the CPU 1.

As described above, by executing 9-4 to 9-6, the HD controller 1 is controlled under the control of the CPU 1.
1 is programmed, then HD controller 11 is D
A request for data transfer is issued to the MA controller 10 (9-7). As you can see from this, CPU
1 is an interrupt signal IN from the HD controller 11
When T is received, it corresponds to the next track (that is, assuming that Tr1 to Tr3 are all in operation now, Tr1, Tr3
The setting and control of the DMA transfer are executed for the DMA controller 10 (in the order of 2, Tr3, Tr1 ...), and the HD controller 11 is programmed. After that, CPU1 is HD
The actual DMA transfer is executed by mutual interaction apart from the controller 11 and the DMA controller 10.

The HD controller 11 displays 9-9 after 9-7.
Go to -8, and reply signal DA from DMA controller 10.
Repeat steps 9-8 until CK (DAK4) is received (see FIG. 8, 8-14).

If the judgment at 9-8 is YES, the program proceeds to 9-9, at which CH4 operation of the DMA controller 10 causes
One sample of digital audio data is transferred, and 9-
The transfer counter set in 6 is decremented by 1 (9-10). In the following 9-11, it is judged according to the contents of the above-mentioned transfer counter whether the data transfer for the preset number of transfer data is completed, and if NO, the process returns to 9-8 again. Therefore, the DMA controller 10 transfers the transfer request DRQ until the transfer of the number of data set by the HD controller 11 (block transfer) is completed.
4 will be continuously received, the processes 8-5 to 8-16 (FIG. 8) will be executed according to this transfer request, and in response to this, the HD controller 11 side will have 9-8 to 9-11.
The process of is executed.

When the transfer end is judged in 9-11, the process proceeds to 9-12, in which the HD controller 11 sends DM.
Data transfer request DRE to the A controller 10
Q (DRQ4) is set to "0" (inactive). Then, regarding the next track, the hard disks 12a, 1
2b and one of the buffers 9-1 to 9-3, the HD controller 11 uses the CPU 1 to transfer data.
An interrupt signal INT is applied to (9-13). In response to this, the CPU 1 executes the interrupt routine as described above.

[0111]

According to the first aspect of the invention, since the data of the data block immediately before or after the event boundary is changed by the fade data, when reproducing the data subjected to the random access editing, It is possible to reliably suppress the abnormal noise generated at the joint portion of the event. In addition, the fade action has the advantage that the data area can be used effectively because it does not change the recorded data or has the changed data in another area and dynamically changes it during playback. Can be performed at the time of data pre-reading, so that control regarding the timing of signal processing becomes easy.

According to the second aspect of the invention, the data of the data block immediately before or after the arbitrary position of the designated audio data is changed by the fade data. Therefore, the digital recorder according to the first aspect. In addition to the above-mentioned effect, fade-in or fade-out can be set at a position desired by the user, and short-time noise such as pop noise recorded during recording can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of a digital recorder of the present invention.

FIG. 2 is a block diagram showing a specific example of a main part of a DMA controller 10 shown in FIG.

FIG. 3 is a flowchart showing a main routine of CPU 1 in FIG.

FIG. 4 is a flowchart showing an interrupt routine of CPU 1 in FIG.

5 is a flowchart for explaining the operation of step 4-4 in the interrupt routine shown in FIG.

FIG. 6 is a flowchart for explaining the operation of step 5-12 in the flowchart shown in FIG.

7 is a flowchart showing the operation of the voice input / output devices 8-1 to 8-3 of FIG.

FIG. 8 is a flowchart showing an operation of the DMA controller 10 of FIG.

9 is a flowchart showing the operation of the HD controller 11 of FIG.

10 is a conceptual diagram showing the overall operation of the digital recorder of FIG.

11 is a conceptual diagram showing a fade-in / fade-out operation in the digital recorder of FIG.

12 is an explanatory diagram showing an example of an event table in the embodiment of FIG.

13 is an explanatory diagram showing an example of an event sequence table of original recording data in the embodiment of FIG.

FIG. 14 is an explanatory diagram showing an example of a user-defined event sequence table.

FIG. 15 is an explanatory diagram showing an example of current data.

[Explanation of symbols]

 1 CPU 2 ROM 3 RAM 8-1, 8-2, 8-3 Audio input / output device 9-1, 9-2, 9-3 Buffer 10 DMA controller 11 HD controller 12a, 12b Hard disk 13 Decoder 14, 15 AND gate 16 inverter

Claims (2)

[Claims] 1. An audio input / output unit for performing an input / output operation of audio data, an audio data storage unit for storing audio data supplied from the audio input / output unit, and an audio data stored in the audio data storage unit. A plurality of pieces of event information, and control means for performing random access editing by program-controlling the reproduction order of the event information; and a fade for setting fade data to the boundary of the event information edited by the control means. A digital recorder comprising: a data setting unit; and a data changing unit that changes the data of the data block immediately before or after the boundary of the event information by performing the fade process with the fade data set by the fade data setting unit. 2. An audio input / output unit for performing an input / output operation of audio data, an audio data storage unit for storing the audio data supplied from the audio input / output unit, and an audio data stored in the audio data storage unit. A plurality of pieces of event information, and control means for performing random access editing by program-controlling the reproduction order of the event information; and fade data for any position of the audio data that is random access edited by the control means. And a fade data setting unit that sets the data in the data block immediately before or after an arbitrary position of the random access edited audio data, and performs a fade process with the fade data set by the fade data setting unit to change the data. Digital equipped with data changing means Coder.