JP3028667B2 - Digital recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recorder capable of digitally recording and reproducing an audio signal and the like, and further, capable of editing.

[0002]

2. Description of the Related Art It has been proposed to use an external recording device such as a large-capacity hard disk or a magneto-optical disk for recording an audio signal or the like (for example, Japanese Patent Application No. 2-123788 by the present applicant). ). In this case, the audio signal is
The signal is converted from an analog signal to a digital signal by the A / D converter, and is temporarily stored in the buffer memory. The digital data stored in the buffer memory is transferred and recorded on a hard disk at a predetermined timing. On the other hand, even at the time of reading, digital data read from the hard disk is temporarily stored in the buffer memory, read from the buffer memory at a predetermined timing, and input to the D / A converter. The audio signal converted from a digital signal to an analog signal by the D / A converter is supplied to a speaker or the like. By controlling the access address of the hard disk, an apparatus having an advanced and flexible editing function can be realized.

[0003]

In order to realize such an apparatus at low cost, it is necessary to make the RAM as a buffer memory for absorbing the overhead of disk access at least a small capacity. On the other hand, during editing, for example, if a large number of looping playbacks are specified at extremely short time intervals, disk access is frequently performed, so a buffer memory with a very small capacity cannot absorb the disk access overhead. However, there has been a problem that data transfer cannot be made in time, causing inconveniences such as skipping of sound during reproduction.

[0004] In particular, when different media such as a hard disk and a magneto-optical disk are used as the external storage device (the hard disk is faster and the magneto-optical disk is slower), transfer to each disk is performed. There is a problem that it is difficult to efficiently use the capacity of the buffer memory due to the difference in the rates.

[0005] The present invention has been made in view of such a situation, and it is an object of the present invention to efficiently use the capacity of a buffer memory.

[0006]

A digital recorder according to the present invention has a hard disk 12-1 as first external recording means for recording a digital signal, and a digital signal is recorded and is slower than the hard disk 12-1. Magneto-optical disk 12-2 as second external recording means having access time, and temporary storage having a plurality of areas for temporarily storing digital signals reproduced from hard disk 12-1 and magneto-optical disk 12-2 Buffers 9-1 to 9-3 as means, information reproduced from a hard disk 12-1 as first external recording means, and information reproduced from a magneto-optical disk 12-2 as second external recording means CPU 4-1 as a calculating means for calculating the ratio of the program and step 4-1 on the program, and the step of the CPU 1 as the calculating means. A CPU 1 as setting means for setting the ratio of the areas of the buffers 9-1 to 9-3 as temporary storage means according to the calculation result of 4-1 and steps 4-3 and 4-4 on the program. It is characterized by the following.

The setting means, that is, step 4 of the CPU 1
Buffer 9-1 as temporary storage means by 3, 4-4
The setting of the ratio of the areas 9 to 9-3 can be performed at predetermined time intervals.

[0008]

In the digital recorder according to the first aspect, information reproduced from the hard disk 12-1 which is the first external recording means having a fast access time and light which is the second external recording means having a slow access time are provided. Magnetic disk 12
-2, the ratio of the information to be reproduced is calculated, and the ratio of the areas of the buffers 9-1 to 9-3 as the temporary storage means is set in accordance with the calculation result. Therefore, the buffers 9-1 to 9-3 as temporary storage means can be used efficiently.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the digital recorder according to the present invention will be described below with reference to the drawings.

<Overall Configuration> FIG. 1 shows the overall configuration of an embodiment of a digital recorder according to the present invention. In this embodiment, recording and playback operations for up to three tracks can be performed simultaneously. . The whole is CP as shown
It is divided into a U part (left part in the figure) and a DMA unit (audio recording / reproducing processing device) (right part in the figure).

The CPU section includes a CPU 1, a program ROM 2 for storing a program (described later in detail) for defining the operation of the CPU 1, an area for storing various data,
A RAM 3 including an area for storing a current pointer of a track, a work area, and the like;
It has a keyboard 4 including various function keys and data input keys as peripheral devices connected to the port, a display device 5 including a CRT or LCD and its driver and performing various displays.

As will be described later, during real-time operation (recording / reproducing, etc.), the CPU 1 sets the D / A bus in the idle time of the address bus and the data bus of the DMA unit as necessary.
The components of the MA unit are controlled, and during editing, rearrangement of data blocks, manipulation of a disk access pointer, and the like are performed. Recording / recording of each track (hereinafter referred to as Tr) is performed from the keyboard 4 as described later.
You can set playback mode, start, stop, locate, and specify edit points. Program ROM2, RAM
3 is connected to an address terminal of the CPU 1 via an address bus.
And an output terminal thereof is connected to the CPU 1 or the transceiver 7 via the data bus.

That is, in order to connect the CPU unit and the DMA unit, the buffer 6 and the transceiver 7
It is provided in the unit. The buffer 6 is connected to the CPU 1 via an address bus, and further connected to an address bus in the DMA unit. The transceiver 7 is a CPU
1 and a data bus, and further connected to a data bus in the DMA unit. In the DMA unit,
Audio input / output device 8-1 for Tr1, audio input / output device 8-2 for Tr2, audio input / output device 8-3 for Tr3
Are provided, and analog audio signals can be input and output independently of each other.

Inside each of the audio input / output devices 8-1 to 8-3, in addition to a converter for selectively performing A / D conversion and D / A conversion, a low-pass filter for removing sampling noise, and a sampling device A clock circuit that generates a clock with a period is included. These audio input / output devices 8
In -1 to 8-3, if the track is set to the record state, an external analog audio signal is appropriately filtered for each sampling period, and
/ D conversion to obtain digital audio data. Conversely, if the track is set to the play (playback) state, the digital audio data read in advance is
After being subjected to / A conversion and appropriately filtered, it is output as an analog audio signal.

Each audio input / output device 8-1 of Tr1 to Tr3
8-3 correspond to the corresponding buffers 9- via the data bus.
1 (BUF1), a buffer 9-2 (BUF2), and a buffer 9-3 (BUF3), respectively, for exchanging digital audio data. The buffers 9-1 to 9-3 correspond to Tr1 to Tr3, respectively.
Data transfer between -1 to 8-3 is performed by direct memory access (DM
A) The method is performed.

Each of the audio input / output devices 8-1 to 8-3 includes:
At the time of recording, the audio input / output devices 8-1 to 8-3 are transmitted to the DMA controller 10 at a sampling period.
Transfer (single transfer) of digital data related to one sampling in the direction from the buffer to the buffers 9-1 to 9-3
Request (request) and send a DRQ signal (Tr1
DRQ1, DRQ2 for Tr2, DRQ for Tr3
3) to the DMA controller 10)), D
Answer from MA controller 10 (Acknowledge is
Tr1 receives DAK1, Tr2 receives DAK2, and Tr3 receives DAK3 as DAK3), and the actual data transfer is executed. At the time of play, a request for DMA transfer (single transfer) of digital data relating to one sampling from the buffers 9-1 to 9-3 in the direction of the audio input / output devices 8-1 to 8-3 in the sampling cycle is issued when audio input Data is transferred from the output devices 8-1 to 8-3 by the DMA controller 10 in the same manner as described above.

Each of the buffers 9-1 to 9-3 has a capacity capable of storing digital audio data once or a plurality of times. For example, the RAM is divided into three parts Tr1 to Tr3, and each of the buffers is divided into a ring buffer (last address and first address). Is used as a buffer that is virtually connected to the
It is configured to function as an O buffer. The addresses for the buffers 9-1 to 9-3 are specified by the DMA controller 10 or the like via an address bus. That is, when the DMA transfer is performed, the DMA controller 10 occupies the address bus, the data bus, and the control signal line in the DMA unit.

The buffers 9-1 to 9-3 are connected to disks such as a hard disk 12-1 and a magneto-optical disk 12-2 (hereinafter simply referred to as a disk 12) under the control of the device controller 11 via a data bus. To give and receive. Disk 12 and device controller 1
1 is connected via a data bus and a control signal line, and all read / write accesses to the disk 12 are performed by the device controller 11. Each disk has a storage area divided into three tracks of Tr1 to Tr3, and data transfer with the buffers 9-1 to 9-3 is performed by the DMA controller 10.
This is done by the device controller 11 issuing an interrupt (INT) to the CPU 1 when the transfer of one data block is completed, and instructing the CPU 1 to transfer the next data block. When an interrupt signal INT is received from the device controller 11, the CPU 1
After setting the MA controller 10 and the device controller 11 to desired states or programming,
DMA transfer is performed. Details of this operation will be described later.

When playing, the DMA controller 10 reads out a predetermined amount (a plurality of sampling periods) of digital audio data from the disk 12 and then
It operates to perform DMA transfer (block transfer) to a designated buffer among the buffers 9-1 to 9-3, and at the time of recording, a predetermined amount (for a plurality of sampling periods) from the designated buffer. It operates to read digital audio data and perform DMA transfer (block transfer) to a designated position on the disk 12.

This disk 12 and buffers 9-1 to 9-
When transferring data to / from the device controller 1,
1 to the DMA controller 10 by request signal DREQ
Is output (received as DRQ4 on the DMA controller 10 side), and when the transfer becomes possible, the answer signal DACK is received (outputted as DAK4 on the DMA controller 10 side), whereby the actual transfer state is set.

As described above, the DMA controller 10
3 channels between audio input / output devices 8-1 to 8-3 of Tr1 to Tr3 and buffers 9-1 to 9-3 (C to be described later)
H1 to CH3) data transfer and one-channel (CH4) data transfer between one of the buffers 9-1 to 9-3 selected in order and the disk, for a total of four channels in time division. Perform data transfer operation.

The CPU 1 supplies an address signal to the buffer 6 via an address bus and manages a designation signal of each component to the decoder 13 via the buffer 6 in order to manage the function and operation of each component in the DMA unit. Supply,
Each of the designation signals CS is transmitted to each of the audio input / output devices 8-1 to 8-
3, buffers 9-1 to 9-3, DMA controller 1
0, given to the device controller 11. At the same time, various data are exchanged with the CPU 1 via the transceiver 7 and the data bus.

Further, each of the voice input / output devices 8-
A designation signal WR for designating a record state (write state) or a play state (read state) is supplied to the IOWR terminals 1 to 8-3 via the buffer 6.

Each of the buffers 9-1 to 9-3, DMA
The designation signal (write signal) WR and another designation signal (read signal) RD are also supplied from the CPU 1 to the controller 10 and the device controller 11 via the buffer 6 to read data from the respective constituent elements. Conversely, data is written. Also, DMA
The controller 10 outputs these designation signals RD and WR in the DMA transfer state. The relationship between these signals and the function and operation of each component will be described later.

The DMA controller 10 outputs a DMA enable (enabling) signal DMAENB to "1" when a DMA transfer is being performed between the constituent elements. As a result, the output of the AND gate 14 to which the signal DMAENB is applied via the inverter 16 becomes “0”,
The enabling signal E is supplied to the buffer 6 and the transceiver 7.
Is given as "0", so that data and addresses cannot be transferred between the CPU unit and the DMA unit. At this time, if a "1" signal is given to the AND gate 15 from the decoder 13, the output of the AND gate 15 becomes "1" and the wait signal WAIT is supplied to the CPU 1.

That is, when the CPU 1 supplies a predetermined signal to the decoder 13 in order to open the buffer 6 and the transceiver 7 in order to manage the DMA unit, that is, the decoder 13 outputs "1" to one input terminal of the AND gate 14. 1 ”signal is supplied (the CPU 1
-1 to 9-3, the DMA controller 10, the device controller 11, and the address signal for accessing any of the audio input / output devices 8-1 to 8-3, the output of the decoder 13 becomes active and the AND gate 1
The output to one input terminal of each of 4 and 15 is "1"),
When the DMA transfer starts, the CPU 1 waits (WAI
T), and after the DMA transfer is executed with priority, the operation of the CPU 1 is restarted with the release of the wait.

On the contrary, the DMA controller 10
When executing the A transfer, the CPU 1
Even if an attempt is made to access controller 10, wait signal WAIT is supplied from AND gate 15 and CPU 1
Execution cycle is extended halfway, buffer 6,
Transceiver 7 will be closed during that time.

After all, the reason why the CPU 1 can access each component of the DMA unit is that the CPU 1 has issued an address for accessing each component of the DMA unit. The signal DMAENB is inactive ("0"), that is, the data bus of the DMA unit is free. Is satisfied when the two conditions are satisfied, but as described above, the CPU 1
Processing can be advanced without considering whether to access the A unit.

When the CPU 1 wants to immediately change the operation state of the DMA unit in response to a key input or a trigger of control data, the CPU 1 is not limited to the DMA controller 10 regardless of the state of the DMA controller 10. A command DMAEND for interrupting the DMA transfer can be output (this is given to the DMA controller 10 as an END signal).

<Main Configuration of DMA Controller 10> Next, an example of the configuration of the DMA controller 10 will be described. D
The MA controller 10 has a transfer capability in which one bus cycle is several hundred nanoseconds. Therefore, the time for transferring the sampling data for three tracks is 1 to 2 microseconds.

When the sampling frequency fs is 48 KHz, the interval of one sampling time is about 21 microseconds, and most of the sampling time interval is between the buffers 9-1 to 9-3, the device controller 11, and the disk 12. The time for data transfer and the programming time of each component from the CPU 1 can be allocated.

FIG. 2 shows the main configuration of the specific example. The DMA controller 10 has an input (IN) address buffer 1 connected to an address bus.
01 and an output side (OUT) address buffer 102. The contents specified by the register selector 103 change according to the address signal applied to the input side address buffer 101, and the desired registers existing in the address register 104 and the control register 105 are specified.

The address register 104 and the control register 105 have areas for four channels CH1 to CH4.
-1 to 9-3 and a register for performing DMA transfer between the audio input / output devices 8-1 to 8-3.
H4 indicates the designated buffer among the buffers 9-1 to 9-3 and the hard disk 12-1 or the magneto-optical disk 1.
This is a register for performing a DMA transfer with the 2-2.

The registers of the channels CH1 to CH4 in the address register 104 are stored in the corresponding buffers 9-1.
9-3 and an area for storing at least the current address and the start address of the designated buffer. The register of CH4 is further provided with a transfer counter, and the number of data set in this counter is DM.
When the A transfer is performed, even if the DMA request from the device controller 11 continues, the D
The MA operation is stopped (according to 8-8 in FIG. 8 described later). In the area of each of the channels CH1 to CH4 of the control register 105, for example, control data designating the direction of the DMA transfer is stored.

The contents of the address register 104 and the control register 105 can be input / output to / from a data bus via a data buffer 106. These components are controlled by the timing control logic 107, the service controller 108, and the channel selector 109.

The service controller 108 has a hardware logic or microprogram control structure, and receives signals from the timing control logic 107, audio input devices 8-1 to 8-3, and DMA request signals DRQ1 to DRQ4 from the device controller 11. And C
Upon receiving a DMA suspend command END (DMAEND) from PU1, answer (acknowledge) signals DAK1 to DAK4 for the above-described components, and a DM indicating that DMA transfer is in progress
In addition to outputting the A enable (enabling) signal DMAENB, it also issues various commands to the timing controller 107 and outputs a channel select signal to the channel selector 109. The channel selector 109 selectively designates a register corresponding to each of the channels CH1 to CH4 in the address register 104 and the control register 105.

Timing control logic 107
Receives the designation signal CS from the decoder 13, the control signal from the control register 105, and the control signal from the service controller 108, controls the input / output of the address buffer 102 and the data buffer 106, and operates the address incrementer 110. Then, the current address register of the designated channel in the address register 104 is incremented. When the current address register reaches the final address of the buffer assigned to the channel, the current address register is reset to the start address of the buffer assigned to the channel.

An area data register 111 as monitoring means for managing and controlling buffer area information.
And the area data buffer 112 are used.

In the area data register 111 and the area data buffer 112, the top (head) and tail (end) addresses of the buffer area allocated to the channel are stored. Each time the address incrementer 110 increments the current address, the address incrementer 110 refers to the area data register 111 of the channel currently being serviced, and if the increment result of the address reaches the tail address, the address is incremented to the top address to circulate the buffer. Reset. Alternatively, the change from the tail address to the top address may be performed by a program control process of the DMA controller 10 as described later (see FIGS. 8 and 16).

<Overall Operation of CPU 1> The operation of this embodiment will be described below. Flow charts showing the operation of the CPU 1 are shown in FIGS. This is the program (software) stored in the program ROM 2
FIG. 3 shows a main routine, and FIG. 4 shows a flowchart showing more detailed processing of step 3-20 in FIG. FIG. 5 shows an interrupt routine executed in response to an interrupt signal INT from the device controller 11, and FIG. 6 shows some steps (5-2) of the interrupt routine shown in FIG. 5 in more detail. ing.

First, in FIG. 3, the CPU 1 starts a main routine in response to power-on, and proceeds to step 3-
Various initial states are set at 0 (hereinafter simply referred to as 3-0). Then, a key input is received in 3-1.
In -2, it is determined what mode has been set.

When the CPU 1 judges that the current mode is the play / record mode, the program proceeds from 3-2 to 3-3 to sequentially select and designate three tracks, and further proceeds to 3-4 to change the operation mode of each track to the keyboard 4 mode. Via the buffer 6 and the decoder 13 at 3-5, which of the A / D conversion and the D / A conversion is performed by each of the audio input / output devices 8-1 to 8-3 in 3-5. The IOWR is set while sequentially transmitting the designation signal CS. Now, for example, Tr1 is in a play state (accordingly, a D / A conversion operation state), and Tr2 and Tr3 are each in a record state (accordingly, an A / D conversion operation state). FIG.
FIG. 0 shows a conceptual diagram of a schematic operation when such a mode is set.

In step 3-5, the buffer 9 for each of the Tr1 to Tr3 is sent to the DMA controller 10.
The addresses 1 to 9-3 are initialized. That is, the channels CH1 to CH1 are controlled by the address buffer 101, the register selector 103, and the channel selector 109 in FIG.
Initial setting data is input and set via the data buffer 106 while designating each register (the address register 104 and the control register 105) of CH3.

Here, the buffers 9-1 to 9-3 are cyclically used as ring buffers. Initially, the buffers 9-1 to 9-3 are initialized with the start addresses of the buffers 9-1 to 9-3. The addresses are set so as to match (in FIG. 10, the start addresses and the current addresses of the buffers 9-1 to 9-3 are CH1 to CH3).
3 schematically shows the state stored and controlled in the address register 104).

Subsequently, the CPU 1 executes the processing of 3-6,
Initialize the disk access pointers corresponding to the tracks Tr1 to Tr3 of the hard disk 12-1 and the magneto-optical disk 12-2 existing in the work (work) memory area in the RAM 3 (FIG. 10 shows the hard disk 12-1).
Shows the relationship between the storage area and the disk access pointer.

Next, the CPU 1 controls each audio input / output device 8-1.
The A / D conversion operation or D / A conversion operation of 8-3 is started (3-7). Subsequently, in 3-8, a software interrupt is issued, and the device controller 11 issues a program request for data transfer between the hard disk 12-1 or the magneto-optical disk 12-2 and any of the buffers 9-1 to 9-3. (The device controller 11 is the CPU 1
Perform the same processing as described below (interrupt INT).

More specifically, the operation according to the flowcharts shown in FIGS. 5 and 6 is executed in 3-8.
Before starting the description of the flowcharts shown in FIGS. 5 and 6, the configuration of each table stored in the RAM 3 of FIG. 1 will be described. The RAM 3 of FIG.
As shown in FIGS. 1 to 14, an event table (referred to as ET) and an event sequence table (referred to as EST) for controlling the reproduction schedule are defined, and a memory area for the current data which is intermediate data between them is taken. I have.

FIG. 11 shows an example of registration of the above-mentioned event table. The event data stored in this table includes an event name (name), a disk ID (id) (the hard disk 12-1 (00) and One of the magneto-optical disks 12-2 (01)),
It is composed of a head data address (sample (word) data address) (adrs) and an event length (sample data number) (vol). In the event table shown in FIG. 11, the original recording data "1" to "4" are automatically created by securing an area at the time of recording.

FIG. 12 shows an example of the EST of the original recording data. The EST index (ESTindex) from "0" to "2" is set in the horizontal direction.
Each track number is arranged in the vertical direction, and an event number is stored corresponding to each track number. In FIG. 12, for example, the data (2 and 3) of track 2 shows a state where the data is recorded over disks “00” and “01”, and an event number “0” indicates the end of a sequence element. Things.

FIG. 13 shows an example of an EST of the edited work 1 in which events are defined by the user himself and arranged on tracks to be output. As in FIG. 12, "0" to "8" are displayed in the horizontal direction. The EST index of "" is arranged in the track direction in the vertical direction, and an event number is stored corresponding to each track number. Therefore, as described above, there can be a plurality of ESTs corresponding to the edited works.

FIG. 14 shows the current data when DMA transfer is actually performed. The index number of the EST to be transferred next for each track and the amount of the event transferred are shown. The indicated transfer amount is stored.

The operation of the CPU 1 when reproducing a user-defined event sequence as shown in FIG. 13 will be described below with reference to the flowcharts shown in FIGS. First, with regard to Tr1, in order to transfer digital signal data from the hard disk 12 to the buffer 9-1 by DMA, the channel of the DMA controller 10 is set to T1.
The channel CH1 corresponding to r1 is determined (5-
1).

Subsequently, a step 5-2 for obtaining a disk ID, a word address, and a transfer address from the track number and the free space (transferable capacity) of the channel buffer is executed. FIG. 6 shows the flow of the step 5-2 in more detail. It is assumed that the free space of the buffer has been calculated by rounding down in sectors.

That is, in the step 6-1, an EST index is obtained from the corresponding track current data, and an event number is obtained. Then, in step 6-2, the ID of the event is obtained from the event table shown in FIG. Next, in 6-3, “the start address of the event + the transferred amount of the current data =
The word address is calculated according to the expression of "word address". The head address of the event is obtained from the event table shown in FIG. 11, and the transferred amount of the current data is obtained from the current data shown in FIG.

Then, in step 6-4, the CPU 1 obtains an offset (word) from the word address (disk address indicating a sector (1 sector = 100h)). Next, in 6-5, the untransferred amount is calculated in accordance with the formula of “event capacity−transferred amount = untransferred amount”. The capacity of the event is vo of the event table in FIG.
1 and the transferred amount is obtained from the current data in FIG. Here, in 6-6, it is determined whether or not “free space> untransferred amount”. NO at 6-6
If the judgment is made that the end of the event has not been reached, the calculation of “the transferred amount of the current data + the free space−the offset = the transferred amount” is performed in 6-7, and 6-8.
It is assumed that “the number of transfer words = the free space−the offset”. In the second and subsequent transfers, the free space is rounded down to the size of a sector unit, so that the data transfer is performed in sector units as described later. If the judgment is YES in the step 6-6, the end of the event has been reached. In step 6-9, the processing of "the index of the EST of the current data is +1 and the transferred amount = 0" is performed.
In 10, it is assumed that “number of transferred words = untransferred amount”.

Returning to FIG. 5, in 5-3, the word address is converted into the disk address and the offset, and the number of transfer sectors is obtained from the number of transfer words. In determining the number of transfer sectors, data smaller than a sector cannot be transferred (transfer is performed on a sector basis), and is therefore truncated on a sector basis. Further, in 5-4, the device controller 1 is controlled by the disk address, the number of transfer sectors, and the track mode.
Program one. Further, the transfer direction of CH4 (recording, buffer 9
From -1 to 9-3, the direction of the disk 12 and the reverse direction during reproduction) are programmed. Here, it is judged whether or not “offset = 0” in 5-5, and NO is determined.
Is judged, the event start position is in the sector containing odd data. If there is such a half, CH4 of the address register 104 in the DMA controller 10 is used in 5-6 and 5-7.
The start address of the image (it does not actually exist)
The area is set, an offset value is set in the transfer counter, and dummy transfer is performed.

If it is determined in 5-7 that the dummy transfer has been completed, or if a judgment of YES is made in 5-5, steps 5-8 to 5-10 are executed. In this case, the transfer setting of the area other than the first dummy transfer is performed. That is, in 5-8, the address register 1
The start address of the corresponding channel 04 (in this case, CH1) is copied to the start address of CH4. Then, in 5-9, the value of the transfer counter is set to the value of "number of sectors × sector length-offset value". Further, 5-1
In the case of 0, the C is calculated from the number of transfer words obtained in 5-8.
Update the start address of H. Then, the process returns to the main routine (FIG. 3). In this way, the next access address matches the sector boundary.

In step 5-6 in FIG. 5, dummy transfer is performed to an image area (an address area that does not actually exist). This has the same effect even if the data is transferred not to the image area but to an area other than the unvoiced data in the buffer, but in this case, the start address is set every time the D
It must be obtained from the register 104 of the MA controller 10. However, in the case of an image area, the start address is set to a fixed value indicating the start of the image area, and only the transfer counter of the address register 104 needs to be programmed.

Conversely, the invalid data at the end of the event is
There is no need to perform processing for transferring data to the image area, and there is no problem because the start address can be updated from the number of words to be transferred to a position that does not include invalid data. This is 5-10
This is because the untransferred amount is the number of words to be transferred.

Next, returning to FIG. As will be apparent from the following description, once the first interrupt routine (FIG. 5) is activated and the device controller 11 is operated once, every time the transfer of the data block designated by the CPU 1 is completed, the device controller 11 is activated. 11 (the INT signal is given to the CPU 1).
The PU1 only determines whether the recording / playback operation has ended, whether a key input has been made, or whether a trigger instructed to the control data has been applied.

That is, the CPU 1 refers to the disk access pointer (RAM3) in 3-9 and judges whether or not the memory area is over, that is, whether or not to end (3-10). Output device 8-
Stop A / D conversion and D / A conversion operation of 1-8-3 (3-
11) Then return to 3-1. In the case of NO, the key input state is referred to (3-12). If there is no change, the process returns to the step 3-9 to check the disk access pointer, and the following steps 3-9 to 3-13 are repeated.

If there is any change in 3-13, the process proceeds from 3-13 to 3-14, where the CPU 1
In order to temporarily suspend the A transfer and make a new setting, a DMA stop command (DMAEN
D) is output. Then, according to new input instructions, etc.,
DMA controller 10, audio input / output devices 8-1 to 8-
3 (3-15), proceed to 3-16 to restart the DMA operation again, execute the interrupt routine of FIG. 5 similarly to 3-8 described above, and then return to 3-9.

As described above, at the time of play / recording, the CPU 1 performs the initial setting of 3-4 to 3-8, and then sets 3-9, 3-10, 3-12, 3-13 and 3-3. -1
4 to 3-16 are repeatedly executed, and a change instruction using the keyboard 4 (for example, pause (A / D,
D / A interruption) or punch in / out (A / D,
In response to a change in the control data obtained at the time of editing, the DMA transfer control is immediately interrupted, the program is changed, and the same processing is executed again. Operate.

In 3-2, when the CPU 1 determines that the CPU 1 is currently in the event processing mode, 3-2 to 3-17
Then, the audio data stored in the disk 12 is converted into an event. The eventing means that continuous audio data on the time axis is divided into a plurality of parts by a manual designation operation or the like, and an event name for identifying each divided audio data (event), a disc ID, and data indicating a divided section. (Start point and its length (volume)). In response to the event,
At 18, an event table (FIG. 11) is created. This event table (ET) contains event names,
The disk ID, start point, and volume are registered. The disk ID, start point, and volume correspond to the start address and event length of the disk 12 where the event is stored.

Next, at 3-19, an event sequence table EST is created based on the event table.
(FIG. 13) is created. Next, in 3-20, after an area data setting subroutine (the details of which will be described later) is executed and the end of EST creation is detected in 3-21, the CPU 1 again inputs a key in 3-1. Find out.

In 3-2, when the CPU 1 determines that the mode is currently in the edit (EDIT) mode, 3-2 to 3
Go to -22, and edit the track or point, and what kind of editing (for example, shift the timing of the sound recorded at the specified point for a certain time,
The CPU 1 judges that the data is to be deleted, and executes various editing operations (3-23). Although this editing work is not particularly described in detail, a program of an access point for reading out from the disk 12 to the device controller 11 and the DMA controller 10, transfer to the RAM 3, RA
Under the control of the CPU 1, various edits using the M3, work of restoring the edited digital audio data to the disk 12, designation of an access point, and the like are executed. 3-24
When the end of the editing work is detected in, the CPU 1
The key input is checked again at 3-1.

Next, the details of the area data setting subroutine of step 3-20 in FIG. 3 will be described with reference to FIG. First, in step 4-1, the event ratio of the magneto-optical disk 12-2 for each track is determined. For example, in the case of the track 1 shown in the EST of FIG. 13, the event table (FIG. 11) indicated by each event number of the EST indexes 0 to 8 is inspected. ES
Since the event number for which the T index is 0 is 21,
If the ID of this event number 21 is determined from FIG.
It is. That is, the event of the event number 21 is recorded on the hard disk 12-1 instead of the magneto-optical disk 12-2. The event number of the next EST index 1 is 9, and when the disc on which this event number is recorded is determined from FIG. Therefore, the capacity (length) of the event number 9 is obtained from vol of the event table in FIG. That is, the capacity in this case is 9675h.

In the same manner, the capacity of the event recorded on the magneto-optical disk 12-2 among the events recorded on the track 1 is obtained. In the case of this embodiment, the events shown with circles in FIG. 13 (that is, event numbers 9 and 10) are recorded on the magneto-optical disk 12-2.
It is recorded in. The capacity of event number 10 is shown in FIG.
Since it is 10,000 h, the total capacity of the events recorded on the magneto-optical disk 12-2 among the events of the track 1 is as follows. 9675h × 3 + 10000h = 2345Fh

It is assumed that each of tracks 1 to 3
Total volume (total number of samples) is the same,
Assuming that the speed is 78BE, the ratio Me of the data recorded on the magneto-optical disk 12-2 on the track 1 is expressed by the following equation. Me = 2345Fh / 478BEh = 0.5

As shown in FIG. 13, all events of track 2 are recorded on the hard disk 12-1.
In track 3, only the event of event number 10 is recorded on the magneto-optical disk 12-2, and all other events are recorded on the hard disk 12-1.
e ₂ and Me ₃ are as follows. Me ₂ = 0 / 478BEh = 0 Me ₃ = 10000h / 478BEh = 0.22

As described above, each of the tracks Tr1 to Tr
After 3 of the magneto-optical event ratio Me ₁ to Me ₃ has been determined, a buffer ratio of each track is determined as follows in 4-2. That is, when the average data transfer bandwidth (which will be described later) of the magneto-optical disk 12-2 under a certain condition is B, the access load of each track is obtained from the following equation. Access load = 1 / (1 × (1-Me) + B × Me)

Assuming that Me = 0.5 in track 1 and B is, for example, 0.44 as described later, the access load is obtained as follows. 1 / (0.5 + 0.44 × 0.5) = 1.44

This number means that in order to have the same access overhead absorbing capacity as when reproducing data on the hard disk 12-1, when accessing the magneto-optical disk 12-2, This means that it must have a capacity 1.44 times that of accessing 12-1. Similarly, the access load on track 2 and track 3 is 1 or 1.14. These access loads become the ratio of the buffer capacity as it is.

Here, the average data transfer bandwidth will be described. This means the data transfer capability in consideration of the access overhead, and therefore has a different value depending on the access occurrence condition. Now, the hard disk 12-1
And the maximum transfer bandwidth of the data transfer of the magneto-optical disk 12-2 (the transfer width after the access is completed) is 1.5M.
Byte / S, the average access time of the hard disk 12-1 is 15 ms, and the average access time of the magneto-optical disk 12-2 is 50 ms. This access condition is 20
Assuming that access is made in units of data blocks for each Kbyte, the time required to complete the transfer of the data block is 15 ms for access in the case of the hard disk 12-1, and 20K / 1.5M =
Since 13.3 ms is required, a total time of 28 ms is required. Therefore, the actual transfer bandwidth is 20 Kbytes.
e / 28 ms = 714 Kbyte / S. This is the average data transfer bandwidth of the hard disk 12-1 under the conditions described above.

Similarly, the average data transfer bandwidth of the magneto-optical disk 12-2 is 20 Kbytes / 63 ms.
= 317 Kbytes / S. As a result, the bandwidth ratio of the magneto-optical disk 12-2 to the hard disk 12-1 is 317/714 = 0.44. The smaller the average access unit to the disk 12, the more noticeable the difference in device access overhead becomes. Therefore, it is preferable to estimate the average access unit according to the performance of each component of the realized system, the control method, and the like. . The access overhead is C
If the PU1 determines the data setting for transfer in consideration of the setting, the accuracy becomes more accurate.

When the buffer ratio is obtained as described above, area data is generated in step 4-3. That is, the area data of the buffers 9-1 to 9-3 is determined from the ratio calculated by 4-2 and the addresses allocated to the buffers 9-1 to 9-3. Further, in 4-4, the area data register 111 of the DMA controller 10 is set. Then, the process returns to the main routine.

<Operation of Audio Input / Output Devices 8-1 to 8-3>
Next, an operation state of the audio input / output devices 8-1 to 8-3 will be described with reference to FIG. This flowchart may be based on microprogram control or hard logic control, and various means for implementing functions can be selected.

In the step 7-1, it is judged whether or not the designation signal CS of the voice input / output device has arrived from the CPU 1 (it is active).
In -2, the operation state (record, play, stop, etc.) is set by the CPU 1. This is the CPU 1 in FIG.
In response to 3-5 and 3-15 in the main routine.

Then, if NO is determined in 7-1, in 7-3, the voice input / output devices 8-1 to 8-1
It is determined whether 8-3 is in the record state or the play state.
Proceed to the processing of 4 to 7-9, and if it is determined that
The process proceeds to -10 to 7-15.

First, the operation of the audio input / output devices set in the record state (the audio input / output devices 8-2 and 8-3 in this case) will be described. At 7-4, it is determined whether or not the sampling time has come, and this 7-4 is repeated until the sampling time comes. The determination of the sampling time may be performed by using a hard timer in each of the audio input / output devices 8-1 to 8-3 and outputting the same, or a common hard timer may be provided and each audio input / output device may operate in accordance with the output. It may be operated. As will be understood from the following description, each of the audio input / output devices 8-1 to 8-
It is also possible to make the sampling frequencies of 3 different.

When the determination of YES is made in 7-4, the applied analog audio signal is sampled and held (S / H) and A / D converted. Then, 7
-6, the DMA controller 10
Activate and output the transfer request DRQ.

The DMA controller 10 receives the request signal DRQ and outputs an answer signal DAK for performing the DMA transfer. Therefore, the audio input / output devices 8-1
8-3 (the audio input / output device 8-2 or 8-3 which is in the record state in this case) proceeds to 7-8 if the judgment of 7-7 is YES, and proceeds to A / D conversion to obtain a digital signal obtained by A / D conversion. The audio data is output to the data bus, and the corresponding buffers 9-1 to 9-1 are output.
9-3 (in this case, the buffer 9-2 or 9-3). Then, in step 7-9, the DMA transfer request DRQ is made inactive. Therefore, in this case, in the audio input / output devices 8-2 and 8-3, each sampling period
An analog audio signal supplied from the outside is converted into a digital audio signal, and transferred to the current addresses of the buffers 9-2 and 9-3 specified by the DMA controller 10 as described later (see FIG. 10).

If it is determined in step 7-3 that the player is in the play state, the process proceeds to step 7-10, in which the DMA controller 10 activates the DMA transfer request DRQ and waits for an answer signal DAK from the DMA controller 10 (step 7-7). −
11), fetch digital audio data on the data bus (7-12), and inactivate the request DRQ (7-13). The operation of the DMA controller 10 at this time will be described later, but in this case, as shown in FIG.
The contents of the current address of the buffer 9-1 corresponding to 1 (the contents of the Tr1 area of the disk 12 have already been transferred and recorded) are input and set to the audio input / output device 8-1 by the above operation. Will be. Then, it is determined whether or not the sampling time has come (714). The detection of the arrival of the sampling time is the same as that described in 7-4.

If the answer is YES in 7-14, 7-1
Proceed to 5 to execute the D / A conversion and the low-pass filtering, and then output the analog audio signal to the outside.

The operation at one sampling time in the record state and the play state has been described above. However, the operation returns to 7-1 after the completion of each processing of 7-9 and 7-15, and so on. The processing for the sampling time is executed one after another.

<Operation of DMA Controller 10>
The operation of the DMA controller 10 will be described with reference to FIG. The flowchart of FIG. 8 may represent that the service controller 108 of FIG. 2 operates under microprogram control, or the function of the DMA controller 10 may be realized by hard logic.

First, at 8-1, it is determined whether or not the designation signal CS from the CPU 1 has arrived (is active). If YES, either the read signal RD or the write signal WR is given from the CPU 1. It is determined (8-2) whether or not the contents of the registers 104 and 105 specified by the address signal given via the address bus are output via the data bus. Then, the CPU 1 can read the data, and if the write signal WR, on the other hand, the process proceeds to 8-4 to input and set desired data to the designated register via the data bus. The processes of 8-3 and 8-4 correspond to processes of 3-5 and 3-15 of the main routine of the CPU 1. Therefore, by the processing of 8-4, each register 104, 1 in FIG.
In 05, desired data is set.

The DMA from the CPU 1
When the access to the controller 10 or the program is completed, the designation signal CS is made inactive, and 8-1 to 8
The process proceeds to -5.

In 8-5, each of the audio input / output devices 8-1 to 8-8
-3, the DMA transfer requests DRQ1 to DRQ3 have been received, or the device controller 11
It is determined whether the EQ (DRQ4) has arrived. If a request has been received from any of them, the process proceeds to 8-6, and the DMA enable signal D
MAENB is set to “1” (active), so that the DMA controller 10 occupies the address bus and the data bus in the DMA unit, and does not accept access from the CPU 1.

Subsequently, for a plurality of requests, a channel is selected according to the priority order of channels CH1 to CH4 (8-7).

Next, it is determined whether or not CH4 of the address register 104 is selected and the value of the transfer counter provided for CH4 is "0" (8-8). Here, if CH4 is selected and the value of the transfer counter is "0", that is, after the transfer of only the amount of data to be transferred by CH4 has been completed, even if there is a transfer request, the transfer is stopped. Return to 8-5 without performing, and repeat the routine of 8-5 to 8-8. If CH4 is not selected, or if the value of the transfer counter is not "0" even if CH4 is selected, the current address (address register 104) of the selected channel (now, for example, CH2) is selected.
(The content of the current address register of CH2) is output to the address bus (8-9). Then, the control register 10 of the selected channel (now, for example, CH2)
5 to determine in which direction the DMA transfer is to be performed (8-10). If the data is to be transferred from the buffers 9-1 to 9-3 to another element (I / O), the processing is to be performed from 8-11. 8-12
Then, the read signal RD is given to the buffer selected from among the buffers 9-1 to 9-3, and conversely, the transfer is performed from another element (I / O) to the buffers 9-1 to 9-3. If so, the process proceeds to 8-13, and the write signal WR is sent to the buffer.
give.

Thereafter, the answer signal DAK is activated (8-14). As a result, in this case, the audio input / output device 8-2 of the Tr2 sends out the sampled audio data to the data bus by the processing of 7-7 and 7-8 (FIG. 7), and the current of the buffer 9-2. The DMA controller 10 writes data in the address area (FIG. 1).
0).

In the step 8-15, since the data transfer is completed, the read signal RD or the write signal WR and the answer signal DAK are made inactive, and in the step 8-16, the current address (the address in FIG. (In the register 104) is set to +1 and after reaching the final address of the buffer, the buffer is reset to the buffer start address. By the operation of 8-16, the buffers 9-1 to 9
-3, each time new sampled audio data is written, or each time new audio data is read out,
It will be reset to the up-count or buffer start address. Then, after the processing of 8-16, 8-
Return to 1.

In the above state, the data transfer request from the audio input / output devices 8-2 and 8-3 for Tr2 and Tr3
Has been done for the controller 10 and so far T
Since the data transfer has been executed only for r2, YES is determined in the following 8-5. Below T
Regarding r3, the voice input / output device 8-3 sends the buffer 9-
The data transfer in the direction 3 is 8-7 to 8-11 and 8-1.
By executing the steps 3 to 8-16, the operation is performed in the same manner as in the case described above.

When such data transfer is completed, 8-5
From 8 to 17, the DMA enable signal is set to "0" (inactive), the DMA controller 10 stops occupying the data bus and address bus in the DMA unit, and the access from the CPU 1 can be accepted. To

[0096] Regarding Tr2 and Tr3, the audio input / output devices 8-2 and 8-3 transmit the corresponding buffers 9-2 and 9-3, respectively.
The data transfer to the audio input / output device 8-1 has been described above.
Is transferred by the DMA controller 10.

The CPU 1 sequentially performs data transfer between the buffers 9-1 to 9-3 corresponding to the operating track and the disk 12 for each track, and for each track, the Data transfer following transfer (block transfer) is performed. In the example of FIG.
As for the track No. 1, the data amount corresponding to the blank portion between the illustrated start address (CH1) and the current address (CH1) will be transferred from the disk 12 (the data transfer direction is also applied to other tracks). Conversely, it is clear that similar control is performed.) Note that, in the play mode buffer (corresponding to 9-1) and the record mode buffer (corresponding to 9-2 and 9-3), the hatched portions correspond to the voice-inputted data portions.

When the DMA controller 10 detects that there is a transfer request from the device controller 11 at 8-5, the DMA controller 10 executes 8-6 to 8 in the same manner as described above.
After executing -10, a request for data transfer from the buffers 9-1 to 9-3 to the disk 12 or a request for data transfer from the disk 12 to the buffers 9-1 to 9-3, 8-11 In the former, go to 8-12,
If the latter, the process proceeds to 8-13, and then executes the processes of 8-14 to 8-16. At this time, for example, digital audio data for one sample is transferred by one transfer operation, and the operations of 8-5 to 8-16 are repeated a plurality of times to perform block transfer. This disk 12
For the data transfer between the buffer 9-1 and the buffers 9-1 to 9-3,
The operation of the device controller 11 is also closely related, and will be further described later.

When the DMA transfer is completed, the request signals DRQ1 to DRQ4 do not arrive, and the request signals 8-5 to 8-17
Then, the DMA enable signal DMAENB is set to "0" (inactive).

<Operation of Device Controller 11> Next, the operation of the device controller 11 will be described with reference to FIG. This device controller 11 may be realized by hardware logic or microprogram control, and in any case, implements the operation flow of FIG.

First, it is determined whether the designation signal CS is given from the CPU 1 (9-1). In the case of NO, the process returns to the original, but in the case of YES, the process proceeds to 9-2, and it is determined whether the read signal RD or the write signal WR is provided from the CPU 1, and at the time of reading, the device controller 11 is determined in 9-3. The internal designated data (contents of the address register, etc.) is output to the CPU 1 via the data bus.

When the write signal WR is given, the process proceeds from 9-2 to 9-4, and the data transfer direction between the buffer for DMA transfer and the disk 12 in the channel CH4 of the DMA controller 10 this time is set. At 9-5, an access point of the disk 12 to be accessed is set. This is based on the access pointer of the track obtained by the CPU 1 from the RAM 3.

Subsequently, in step 9-6, the number of transfer data (the number of digital audio data) is set in an internal counter of the device controller 11.

As described above, by executing steps 9-4 to 9-6, the device controller 11 is programmed under the control of the CPU 1, and thereafter, the device controller 11 requests the DMA controller 10 for data transfer ( 9-7). As you can see from this,
Upon receiving the interrupt signal INT from the device controller 11, the CPU 1 corresponds to the next track (that is, if all of Tr1 to Tr3 are operating now,
1, in the order of Tr2, Tr3, Tr1,...
Program the device controller 11. afterwards,
The CPU 1 is separated from the device controller 11 and the DMA controller 10 to execute an actual DMA transfer by mutual interaction.

The device controller 11 proceeds to 9-8 following 9-7, and repeats 9-8 until receiving the answer signal DACK (DAK4) from the DMA controller 10 (see 8-14 in FIG. 8). When the judgment in 9-8 becomes YES, the process proceeds to 9-9, in which the operation of CH4 of the DMA controller 10 transfers the digital audio data of one sample, and the transfer counter set in 9-6 is counted down by one. (9-10). In the following 9-11, judgment is made according to the contents of the transfer counter as to whether the data transfer for the preset number of transfer data has been completed,
If NO, return to 9-8 again. Therefore, the DMA controller 10 continuously receives the transfer request DRQ4 until the transfer (block transfer) of the number of data set from the device controller 11 is completed. The device controller 11 executes the processing (FIG. 8) and responds thereto.
The side executes the processes of 9-8 to 9-11.

When the end of the transfer is determined in 9-11, the process proceeds to 9-12, in which a request D for data transfer from the device controller 11 to the DMA controller 10 is issued.
REQ (DRQ4) is set to “0” (inactive). Then, the device controller 11 supplies an interrupt signal INT to the CPU 1 in order to transfer data between the disk 12 and any of the buffers 9-1 to 9-3 for the next track (9-13). In response to this, the CPU 1 executes the interrupt routine (FIG. 5) as described above.

In the above embodiment, the total reproduction time lengths of the tracks 1 to 3 are the same, but when the values are different, the following processing can be performed. That is, the processing shown in FIG. 4 is performed at predetermined time intervals. For example, the first 5 seconds are calculated as a first buffer ratio, and the next 5 seconds are calculated as a second buffer ratio. The area can be changed for each section in accordance with the previously obtained data. In this way, the present invention can be applied even when the reproduction time length of each track is different, that is, when the number of tracks is changed. In such a case, address data of the top and tail of each buffer is stored at predetermined time intervals in the area data buffer 112, and this is set in the area data register 111 at an optimal timing in data transfer. I do.

[0108]

As described above, according to the digital recorder of the first aspect, the information reproduced from the first external recording means having a short access time and the information reproduced from the second external recording means having a short access time. Since the ratio of the information to be obtained is calculated and the ratio of the area of the temporary storage means is set in accordance with the calculation result, the temporary storage means can be used efficiently. Therefore, the capacity of the temporary storage means is reduced,
The cost of the device can be reduced.

According to the digital recorder of the present invention, since the setting of the area ratio of the temporary storage means is performed at predetermined time intervals, the present invention can be applied even when the reproduction time length differs for each track. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital recorder according to the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of a DMA controller in FIG. 1;

FIG. 3 is a flowchart illustrating a main operation of a CPU 1 of FIG. 1;

FIG. 4 is a flowchart illustrating a more detailed process of step 3-20 in FIG. 3;

FIG. 5 is a flowchart illustrating the operation of an interrupt routine of CPU 1 of FIG. 1;

FIG. 6 is a flowchart showing a more detailed process of step 5-2 in FIG. 5;

FIG. 7 is a flowchart illustrating the operation of the audio input / output devices 8-1 to 8-3 in FIG. 1;

FIG. 8 is a flowchart illustrating the operation of the DMA controller 10 of FIG. 1;

FIG. 9 is a flowchart illustrating an operation of the device controller 11 of FIG. 1;

FIG. 10 is a conceptual diagram showing an overall operation of the digital recorder in FIG.

FIG. 11 is an explanatory diagram showing an example of an event table in the embodiment of FIG. 1;

FIG. 12 is an explanatory diagram showing an example of an event sequence table of original recording data in the embodiment of FIG.

FIG. 13 is an explanatory diagram showing an example of a user-defined event sequence table.

FIG. 14 is an explanatory diagram showing an example of current data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 RAM 8-1 to 8-3 Audio input / output device 9-1 to 9-3 Buffer 10 DMA controller 11 Device controller 12-1 Hard disk 12-2 Magneto-optical disk

Claims (2)

(57) [Claims] A first external recording unit on which a digital signal is recorded; a second external recording unit on which a digital signal is recorded and which has a slower access time than the first external recording unit; Temporary storage means having a plurality of areas for temporarily storing digital signals reproduced by the first and second external recording means; information reproduced by the first external recording means;
A digital device comprising: a calculating means for calculating a ratio of information reproduced from an external storage means; and a setting means for setting a ratio of an area of the temporary storage means in accordance with a calculation result of the calculating means. decoder. 2. The digital decoder according to claim 1, wherein the setting unit sets the ratio of the area of the temporary storage unit at predetermined time intervals.