JP3055221B2 - Digital recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recorder capable of digitally recording, reproducing and editing an audio signal.

[0002]

2. Description of the Related Art Conventionally, as a method of recording (recording), reproducing, and editing an audio signal, an analog audio signal is magnetically recorded on a magnetic tape, and the analog signal is reproduced and edited. However, since such a conventional technique relies on analog recording and reproduction, deterioration of sound quality cannot be avoided, and particularly when audio signals once recorded are dubbed, the deterioration becomes remarkable.

In addition, since a magnetic tape is used as a recording medium, it takes a long time to reach a target editing point. The recording portion of the magnetic tape is physically cut and pasted. There is also a problem that the editing work cannot be performed unless it is copied to the place once.

Although the problem of sound quality deterioration can be dealt with by digitizing a recording method on a magnetic tape, the disadvantages of cueing and editing flexibility caused by using a sequential access recording medium are merely digital. It cannot be removed depending on the chemical.

Therefore, recently, for example, a random access type (that is, a direct recording type) for storing digital audio data supplied from audio input / output means for inputting / outputting audio data as it is, or for storing digital audio data after editing is completed. A digital recorder having an audio data storage means such as a hard disk drive or a magneto-optical disk has been proposed (for example, Japanese Patent Application No. Hei.
123788).

[0006]

However, in the conventional apparatus, a so-called punch-in and punch-out process for replacing a portion of a predetermined range of an audio signal stored in a predetermined track with another audio signal is performed. Therefore, the punch-in operation is often slightly delayed from the place where the user actually wants to perform the punch-in operation, so that it is difficult to perform the punch-in operation at an accurate position. Problems also accesses the hard disk at the time of punching out, to transfer it to the buffer by reading the audio signal recorded, from where it takes some time, the audio signal is sounded is interrupted halfway in one Dan was there.

The present invention has been made in view of such a situation, and it is an object of the present invention to accurately set a punch-in point and to prevent a reproduced audio signal from being interrupted.

[0008]

According to a first aspect of the present invention, there is provided a digital recorder including: a recording medium on which an audio signal is recorded; a first storage unit on which an input punch-in audio signal is written; operates in parallel with the storage means, second storage means for audio signal reproduced from the recording medium is written, a command means for commanding the punch in and out, before the punch is commanded, written in the recording medium
Read out the recorded audio signal and record it in the second storage means.
And the voice written in the first storage means.
Only the writing is continued without reading out the signal, and when a punch-in is instructed, the audio signal written in the first storage means is read out and recorded on the recording medium, and also written in the second storage means. When the punch-out is instructed, the recording of the audio signal written in the first storage means to the recording medium is stopped, and the second recording is stopped. Control means for restarting reading of the audio signal written in the storage means.

The digital recorder according to the present invention is characterized in that the command means detects the level of the voice signal for punch-in, and instructs punch-in when the level exceeds a predetermined reference level.

According to a third aspect of the present invention, in the digital recorder, the control unit is configured to control the time of the audio signal written in the first storage unit which is offset by a predetermined time before the punch-in command is generated. The audio signal is recorded on a recording medium.

The digital recorder according to a fourth aspect is characterized in that the control means obtains the address of the second storage means at the time of punch-in or immediately after the punch-out from the address of the first storage means.

[0012]

In the digital recorder according to the present invention, the first storage means for storing the punch- in audio signal (punch-in data) and the second storage means for storing the punch-in audio signal are operated in parallel. Before the punch-in command, it is written on the recording medium.
Reads out the recorded audio signal and stores it in the second storage means.
Recorded in the first storage means.
Continue writing only without reading audio signal
When a punch-in is commanded, the first storage means
Reads out the written audio signal and records it on a recording medium
And the sound written in the second storage means.
Stop reading the voice signal and continue writing only,
When punch-out is instructed, the data is written to the first storage means.
Stop recording the recorded audio signal on the recording medium.
And the voice signal written in the second storage means.
That it is controlled so as to resume the issue of reading.

In the digital recorder according to the present invention, punch-in is instructed when the sound signal level for punch-in exceeds a predetermined reference level.

In the digital recorder according to the third aspect, the audio signal at the time offset by a predetermined time before the punch-in command time is punched-in.

In the digital recorder according to the present invention, the address of the second storage means at the time of punch-in or immediately after punch-out is obtained from the address of the first storage means.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the digital recorder according to the present invention will be described below with reference to the drawings.

<Overall Configuration> FIG. 1 shows the overall configuration of an embodiment of a digital recorder according to the present invention. In this embodiment, recording and playback of up to four tracks (one of which is dedicated to punch-in) is performed simultaneously. It can operate. As shown in the figure, a CPU unit (the left part in the figure) and a DMA unit (audio recording / reproducing processing device)
(The right part in the figure).

The CPU section includes a CPU 1, a program ROM 2 for storing a program (to be described in detail later) for defining the operation of the CPU 1, an area for storing various data,
A RAM 3 including an area for storing a current pointer of a track, a work area, and the like;
It has a keyboard 4 including various function keys and data input keys as peripheral devices connected to the port, a display device 5 including a CRT or LCD and its driver and performing various displays. As will be described later, the CPU 1 controls each component of the DMA unit as needed during an idle time of the address bus and the data bus of the DMA unit during a real-time operation (recording / reproduction or the like), and during editing, It performs rearrangement of data blocks, operation of a disk access pointer, and the like. From the keyboard 4, as described later, each track (hereinafter referred to as Tr)
The user can set the recording / playback mode, and specify edit points such as start, stop, locate, punch-in, and punch-out. An address signal is sent from the CPU 1 to the address terminals of the program ROM 2 and the RAM 3 via the address bus, and the output terminal is connected to the CPU via the data bus.
1 or to the transceiver 7.

That is, in order to connect the CPU unit and the DMA unit, the buffer 6 and the transceiver 7
It is provided in the unit. The buffer 6 is connected to the CPU 1 via an address bus, and further connected to an address bus in the DMA unit. The transceiver 7 is a CPU
1 and a data bus, and further connected to a data bus in the DMA unit.

In the DMA unit, in addition to the audio input / output device 8-1 for the track Tr1, the audio input / output device 8-2 for the track Tr2, the audio input / output device 8-3 for the track Tr3, An audio input / output device 8-4 for the punch-in track Tr4 is provided, and analog audio signals can be input / output independently of each other (however, the audio input / output device 8-4
4 can only be input).

In each of the audio input / output devices 8-1 to 8-4, there is provided a converter (the audio input / output device 8-4 is an A / D converter) for selectively executing A / D conversion and D / A conversion. Operation only), a low-pass filter for removing sampling noise, and a clock circuit for generating a clock at a sampling period are included. These audio input / output devices 8-1 to 8-1
In 8-4, if the track is set to a record state, an external analog audio signal is appropriately filtered at each sampling period, and then A / D converted to obtain digital audio data. Conversely, the track is set to the play (playback) state (the audio input / output device 8-4).
If not, the digital audio data read out in advance is D / A-converted at each sampling period, filtered appropriately, and then output as an analog audio signal.

Each audio input / output device 8-1 of Tr1 to Tr4
8-4 correspond to the corresponding buffers 9- via the data bus.
1 (BUF1), buffer 9-2 (BUF2), buffer 9-3 (BUF3), punch-in buffer 9-4 (B
UF4), and exchanges digital audio data.

The buffers 9-1 to 9-4 are Tr1 to T
r4, and the voice input / output devices 8-1 to 8-
4 is performed by the DMA controller 10 by a direct memory access (DMA) method.

The audio input / output devices 8-1, 8-2, 8-3,
Request signals (DRQ1 to DRQ4) and acknowledge signals (DAK1 to DAK4) are transmitted between 8-4 and the DMA controller 10.

Each of the audio input / output devices 8-1 to 8-4 includes:
At the time of recording, the audio input / output devices 8-1 to 8-4 are transmitted to the DMA controller 10 at the sampling period.
Transfer (single transfer) of digital data relating to one sampling in the direction from the buffer to the buffers 9-1 to 9-4
Request (request) and send a DRQ signal (Tr1
DRQ1, DRQ2 for Tr2, DRQ for Tr3
3. In Tr4, the DMA controller 10 is used as DRQ4.
)), The actual data transfer is executed in response to the acknowledgment from the DMA controller 10 (acknowledge given as DAK1 for Tr1, DAK2 for Tr2, DAK3 for Tr3, and DAK4 for Tr4). Is done. At the time of play, a request for DMA transfer (single transfer) of digital data relating to one sampling from the buffers 9-1 to 9-3 in the direction of the audio input / output devices 8-1 to 8-3 in the sampling cycle is issued when audio input Data is transferred from the output devices 8-1 to 8-3 by the DMA controller 10 in the same manner as described above.

Each of the buffers 9-1 to 9-4 has a capacity capable of storing digital audio data once or a plurality of times. For example, the RAM is divided into four parts Tr1 to Tr4, and each of them is divided into a ring buffer (last address and first address). Is used as a buffer that is virtually connected to the
It is configured to function as an O buffer.

The addresses for the buffers 9-1 to 9-4 are specified by the DMA controller 10 or the like via an address bus. That is, when the DMA transfer is performed, the DMA controller 10 occupies the address bus, the data bus, and the control signal line in the DMA unit.

The buffers 9-1 to 9-4 are connected via a data bus to a hard disk controller (hereinafter H).
Data is exchanged with the hard disk 12 under the control of the D controller 11. The hard disk 12 and the HD controller 11 are connected via a data bus and a control signal line, and all read / write accesses to the hard disk 12 are performed by the HD controller 11.
Made by The hard disk 12 has Tr1 to Tr
The storage area is divided into four storage areas of four tracks, and data transfer with the buffers 9-1 to 9-4 is performed by the DMA controller 10. This is done by the HD controller 11 issuing an interrupt (INT) to the CPU 1 when the transfer of one data block is completed, and instructing the CPU 1 to transfer the next data block. CP
U1 is an interrupt signal I from the HD controller 11.
When the NT arrives, the DMA controller 10 and the HD controller 11 are set to a desired state or programmed, and then the DMA transfer is performed. Details of this operation will be described later.

At the time of playing, the DMA controller 10 reads a predetermined amount (for a plurality of sampling periods) of digital audio data from the hard disk 12 and then specifies one of the buffers 9-1 to 9-3. It operates to perform DMA transfer (block transfer) to a buffer. At the time of recording, digital audio data of a predetermined amount (for a plurality of sampling cycles) is specified from a specified buffer among buffers 9-1 to 9-4. The read operation is performed to perform a DMA transfer (block transfer) to a designated position on the hard disk 12.

The hard disk 12 and the buffer 9-1
9-9, the HD controller 11 sends a request signal DRE to the DMA controller 10.
Q is output (received as DRQ5 on the DMA controller 10 side).
(The DMA controller 10 outputs it as DAK5), and the actual transfer state is set.

As described above, the DMA controller 10
4 channels between audio input / output devices 8-1 to 8-4 of Tr1 to Tr4 and buffers 9-1 to 9-4 (C to be described later)
H1 to CH4) data transfer and one-channel (CH5) data transfer between any of the sequentially selected buffers 9-1 to 9-4 and the hard disk 12 for a total of five channels Perform the divided data transfer operation.

The CPU 1 supplies an address signal to the buffer 6 via an address bus and manages a designation signal of each component to the decoder 13 via the buffer 6 in order to manage the function and operation of each component in the DMA unit. Supply,
Each of the designation signals CS is transmitted to each of the audio input / output devices 8-1 to 8-
4, buffers 9-1 to 9-4, DMA controller 1
0, given to the HD controller 11. At the same time, various data are exchanged with the CPU 1 via the transceiver 7 and the data bus.

Further, each of the voice input / output devices 8-
To the IOWR terminals 1 to 8-3, a designation signal WR for designating a record state (write state) or a play state (read state) is given via the buffer 6. The voice input / output device 8-4 is always in a record state.

Each of the buffers 9-1 to 9-4, DMA
The designation signal (write signal) WR and another designation signal (read signal) RD are also supplied from the CPU 1 to the controller 10 and the HD controller 11 via the buffer 6 to read data from the respective constituent elements. Conversely, data is written. The DMA controller 10 also outputs these designation signals RD and WR in the DMA transfer state (the buffer 9).
-4 is WR only). These signals and the function of each component,
The relationship between the operations will be described later.

The DMA controller 10 sets the DMA enable signal DMAENB to "1" and outputs it when the DMA transfer is being performed between the constituent elements. As a result, the output of the AND gate 14 to which the signal DMAENB is applied via the inverter 16 becomes “0”,
The enabling signal E is supplied to the buffer 6 and the transceiver 7.
Is given as "0", so that data and addresses cannot be transferred between the CPU unit and the DMA unit. At this time, if a "1" signal is given to the AND gate 15 from the decoder 13, the output of the AND gate 15 becomes "1" and the wait signal WAIT is supplied to the CPU 1.

That is, when the CPU 1 supplies a predetermined signal to the decoder 13 to open the buffer 6 and the transceiver 7 in order to manage the DMA unit, that is, the decoder 13 supplies one input terminal of the AND gate 14 to the decoder 13. When the “1” signal is being supplied (the CPU 1
When an address signal for accessing any one of -1 to 9-4, the DMA controller 10, the HD controller 11, and the audio input / output devices 8-1 to 8-4 is output, the output of the decoder 13 becomes active and the AND gate 14 , 1
5 is "1" at each input terminal.)
When the transfer is started, a wait (WAIT) is applied to the CPU 1, and after the DMA transfer is preferentially executed, the operation of the CPU 1 is restarted with the release of the wait.

Conversely, the DMA controller 10
When executing the MA transfer, the CPU 1
Even if an attempt is made to access MA controller 10, wait signal WAIT is applied from AND gate 15 and CP
The execution cycle of U1 is extended halfway, and the buffer 6 and the transceiver 7 are closed during that time.

After all, the CPU 1 can access each component of the DMA unit because: CPU 1 issues an address for accessing each component of the DMA unit. 2. The signal DMAENB is inactive ("0"), that is, the data bus of the DMA unit is free. When the two conditions are satisfied, the CPU 1
As described above, the processing can be advanced without considering when to access the DMA unit by the operation of the gates 14 and 15.

When the CPU 1 wants to immediately change the operation state of the DMA unit in response to a key input or a trigger of control data, the CPU 1 is not limited to the DMA controller 10 regardless of the state of the DMA controller 10. A command DMAEND for interrupting the DMA transfer can be output (this is given to the DMA controller 10 as an END signal).

The comparator 19 compares the level of the punch-in audio signal input to the audio input / output device 8-4 with a predetermined reference level, and when the level of the audio signal becomes higher than the reference level, a detection signal. Is output to the CPU 1. This detection signal functions as a punch-in command signal (interrupt signal) as described later.

<Main Configuration of DMA Controller 10> Next, an example of the configuration of the DMA controller 10 will be described. D
The MA controller 10 has a transfer capability in which one bus cycle is several hundred nanoseconds. Therefore, the time for transferring the sampling data for four tracks is 1 to 2 microseconds.

When the sampling frequency fs is 48 KHz, one sampling time interval is about 21 microseconds, and most of the sampling time interval is between the buffers 9-1 to 9-4, the HD controller 11, and the hard disk 12. The time for data transfer and the programming time of each component from the CPU 1 can be allocated.

FIG. 2 shows the main configuration of the specific example. The DMA controller 10 has an input (IN) address buffer 1 connected to an address bus.
01 and an output side (OUT) address buffer 102. The contents specified by the register selector 103 change according to the address signal applied to the input side address buffer 101, and the desired registers existing in the address register 104 and the control register 105 are specified.

The address register 104 and the control register 105 have areas of five channels CH1 to CH5.
This is a register for performing DMA transfer between -1 to 9-4, and the channel CH5 has buffers 9-1 to 9-4.
Is a register for performing a DMA transfer between the designated buffer and the hard disk 12.

The registers of the channels CH1 to CH5 in the address register 104 correspond to the corresponding buffers 9-1.
9-4 and an area for storing at least the current address and the start address of the designated buffer.
For example, control data for designating the direction of DMA transfer is stored in the areas CH5 to CH5.

The contents of the address register 104 and the control register 105 can be input / output to / from a data bus via a data buffer 106. These components are controlled by the timing control logic 107, the service controller 108, and the channel selector 109.

The service controller 108 has a hardware logic or microprogram control configuration, and receives signals from the timing control logic 107, audio input devices 8-1 to 8-4, and the HD controller 1
DMA request signals DRQ1 to DRQ5 from CPU 1
Receiving a DMA suspend command END (DMAEND) from the controller 1 and responding to each of the above components (acknowledge)
In addition to outputting signals DAK1 to DAK5 and a DMA enable (enabling) signal DMAENB indicating that a DMA transfer is being performed, it also issues various commands to the timing control logic 107 and outputs a channel select signal to the channel selector 109. The channel selector 109 selectively specifies registers corresponding to each of the channels CH1 to CH5 in the address register 104 and the control register 105.

Timing control logic 107
Receives the designation signal CS from the decoder 13, the control signal from the control register 105, and the control signal from the service controller 108, controls the input / output of the address buffer 102 and the data buffer 106, and operates the address incrementer 110. Then, the current address register of the designated channel in the address register 104 is incremented.

<Overall Operation of CPU 1>
Will be described. 3 and 4 are flowcharts showing the operation of the CPU 1. This is the program (software) stored in the program ROM 2
FIG. 3 shows a main routine, and FIG.
4 shows an interrupt routine that is executed in response to an interrupt signal INT from the D controller 11.

First, in FIG. 3, it is judged whether the mode set by the keyboard 4 is the play / record mode or the punch-in edit (edit) mode (step 3-1; hereinafter simply referred to as 3-1). ). If the mode is the punch-in edit mode, the process proceeds to 3-2, where execution of punch-in is designated, and 3-3
In, a track to be punched in and a point offset amount are set. For example, of Tr1 to Tr3, Tr
2 is designated as the track to be punched in, and a predetermined value is set as the point offset amount. The point offset specifies how much sound is to be recorded before the punch-in trigger is generated, and the recording can be started from the point up to the capacity of the maximum punch-in buffer 9-4.

The editing work will be described in general terms. Programs for reading access points from the hard disk 12 to the HD controller 11 and the DMA controller 10, transfer to the RAM 3, various kinds of editing using the RAM 3, and digital audio after editing The operation includes re-storing data on the hard disk 12, specifying an access point, and the like, which are executed under the control of the CPU 1.

When the CPU 1 judges in 3-1 that the current play / record mode is set, 3-1.
To 3-4, the operation mode of each of the three tracks is set in accordance with the input instruction of the keyboard 4, and in 3-5, any one of the A / D conversion and the D / A conversion is performed by each audio input / output device. Whether 8-1 to 8-3 are executed, IOWR is given and set while sequentially transmitting the designation signal CS through the buffer 6 and the decoder 13. Now, for example, for all of Tr1 to Tr3, the play state (accordingly, D
/ A conversion operation state). FIG. 10 shows the concept of the schematic operation when such a mode is set.

In 3-5, the DMA controller 1
0, the buffer 9-1 for each of the Tr1 to Tr3
.. 9-3 (and buffer 9-4 if punch-in is specified in 3-2). That is, each register (address register 1) of the channels CH1 to CH4 is controlled by the address buffer 101, the register selector 103, the channel selector 109, and the like in FIG.
04, while specifying the control register 105)
Initial setting data is input and set via the data buffer 106.

Here, the buffers 9-1 to 9-4 are used cyclically as ring buffers.
In the initial state, the start addresses of the buffers 9-1 to 9-4 are set so as to match the current addresses.

Subsequently, the CPU 1 executes the processing of 3-6,
A current pointer corresponding to each of the tracks Tr1 to Tr3 of the hard disk 12 existing in the work (work) memory area in the RAM 3 is initialized. When punch-in is specified, an area for recording punch-in data is secured on the hard disk 12, and the current pointer is set.

Next, the CPU 1 controls each audio input / output device 8-1.
A / D conversion operation or D / A conversion operation of 8-4 is started (3-7). Subsequently, in 3-8, a software interrupt is issued, and the HD controller 11 issues a program request for data transfer between the hard disk 12 and one of the buffers 9-1 to 9-4 (the HD controller 11 interrupts the CPU 1). (The application of INT) is performed (described later).

Specifically, the operation according to the flowchart shown in FIG. 4 is executed in 3-8. That is, 4
At -1, it is determined whether a punch-in operation is being performed,
If the punch-in operation is being performed, the process proceeds to 4-2, and the buffer of the track punched in from the current address of the punch-in buffer 9-4 (for example, the buffer 9-
The current address of 2) is obtained. If the punch-in operation is not being performed, 4-2 is skipped.

That is, during the punch-in operation, the reproduction data is sequentially written from the hard disk 12 to the punch-in track buffer 9-2, but the read data is prohibited from being read out to the audio input / output device 8-2 (FIG. 8-8-3 and FIG. 11). Each buffer 9-1 to 9-4
Are accessed by the audio input / output devices 8-1 to 8-4 to the current address, and the access by the hard disk 12 is performed to the start address. Therefore, during the punch-in operation, the current address of the punch-in track buffer 9-2 is not managed by the DMA controller 10. On the other hand, in the punch-in buffer 9-4, data input from the audio input / output device 8-4 is written during the punch-in operation, and data read therefrom is transferred to the hard disk 12. Therefore, the DMA controller 1
0 manages the current address of the punch-in buffer 9-4.

The current addresses of the buffers 9-1 to 9-4 change synchronously. That is, it advances by one word address at one sample time. For example, each buffer length is secured for every 128 k from address 80000h, and the start address at the start of operation is set to 80000, A0000, C0000 or E000, respectively.
If it is set to 0, the lower 17 bits of each track will always have the same value. Therefore, by changing the value of 17 bits or more, the current address of a desired track can be converted to the current address of another buffer. Therefore, the current address of the punch-in track buffer 9-2 is obtained from the current address of the punch-in buffer 9-4. The current address of the punch-in track buffer 9-2 is used to calculate the free space when transferring data from the hard disk 12 to the punch-in track buffer 9-2 (next 4-3).

Next, in 4-3, the next track to be transferred is determined, and the number of data to be transferred is calculated. If there is no particularly high priority transfer, the priority order is set in the order of channels CH4 (for punch-in), CH1, CH2, CH3 (for recording or reproduction), and CH5 (for transfer with the hard disk 12). When the punch-in operation is not being performed, the audio signal of the punch-in buffer 9-4 is not selected to be transferred to the hard disk 12 (FIG. 10). However, during the punch-in operation, the data transfer of the punch-in buffer 9-4 to the hard disk 12 is permitted at 8-2 in FIG.
1). Therefore, the punch-in tracks are selected in a predetermined order in the step 4-3. After the punch-out, the punch-in buffer 9-4 is selected so that the data is preferentially transferred to the hard disk 12 even if the amount of data in the punch-in buffer 9-4 is small.

For example, the hard disk 1 for Tr1
2 to transfer digital audio data to buffer 9-1.
In order to perform the transfer, the channel CH1 corresponding to Tr1 is selected as the channel of the DMA controller 10 (4-3). Further, the current address and the start address are read from the area of CH1 of the address register 104 of the DMA controller 10, and read out from the buffer 9-1.
The number of data that can be transferred from or to the buffer 9-1 (the amount of free space in the buffer 9-1 during reproduction, that is, the number of data that can be transferred to the buffer 9-1;
The amount of one data full area, that is, the number of data transferable from the buffer 9-1) is calculated (4-3).

Next, it is determined whether the track (in this case, the track Tr1) is in the recording mode or the reproduction mode (see FIG.
4). In the recording mode (for example, when the punch-in is designated, the track Tr4 enters the recording mode), the DMA controller 10 and the HD controller 11 are programmed to transfer data from the buffer 9-4 to the HD controller 10 (4-9). ). More specifically, DM
The programming for the A controller 10 is CH4
Is copied to the start address and the current address of CH5. CH5
Is the current address, the unit amount of data is stored in the buffer 9-.
4 to the HD controller 11. Programming for the HD controller 11 is as follows.
The current pointer of Tr4 is read from the working memory of RAM3, this pointer, the number of data transferable from the buffer 9-4 to the HD controller 11 calculated in 4-3, and the mode detected in 4-4 (recording mode) And by doing.

As a result, in this case, the HD controller 11 requests the DMA controller 10 to perform DMA transfer in the direction from the buffer 9-4 to the hard disk 12 (outputs DREQ), and the DMA controller 10 The transfer will be performed. Then, CPU
1 updates the current pointer of the hard disk 12 to a value that will be the result of executing the above-described transfer processing (4-11). That is, the data transfer between the buffer 9-4 and the hard disk 12 is thereafter performed entirely by the DMA controller 10, and the CPU 1 sets the address of the hard disk 12 when the DMA transfer is completed to the current pointer. You do it.

If it is determined in 4-4 in FIG. 4 that the current mode is the reproduction mode, the CPU 1 calculates the number of remaining data of the current table element in the reproduction schedule table to which the current pointer in the RAM 3 belongs (4-5). The reproduction schedule table is generated for each track, and includes, for example, a start address and an end address indicating a start point and an end point of an area to be reproduced on the hard disk 12 as shown in FIG. Is remembered inside. The playback schedule table is 1
One table element is composed of one start address and one end address. The reproduction schedule table shown in FIG. 12 is made up of five table elements.

The current pointer in the RAM 3 does not indicate the storage position of the audio data currently reproduced or recorded by the audio input / output devices 8-1 to 8-4, but the audio input / output devices 8-1 to 8-4. -4 is the buffer to be accessed next 9-
1 to 9-4 are shown. That is, the outputs of the audio input / output devices 8-1 to 8-4 are sequentially written to the current addresses of the buffers 9-1 to 9-4, and the buffers 9-1 to 8-4 are sequentially written.
The data read from the current address 9-3 is supplied to the audio input / output devices 8-1 to 8-3.

Now, the value of the current pointer is 4900
0, assuming that the end address of the table element to which this pointer belongs is 49899 as shown in FIG. 12, the remaining data number is 49899- (49000-1) = 900.

Next, in 4-6, the number of remaining data obtained in 4-5 is compared with the number of transferable data calculated in 4-3. If the number of transferable data is larger, the table element is determined. The indicated data is transferred from the hard disk 12 to, for example, the buffer 9-1 (4-7). Now, as described above, assuming that the value of the current pointer is (49000), the number of remaining data is 900, and the number of data transferable is 5000,
Since 900 <5000, the audio data stored at 900 addresses from the address 49000 of the disk 12 indicated by the current pointer is transferred to the buffer 9-1.

The data transfer from the disk 12 to the buffer 9-1 is performed by programming the DMA controller 10 and the HD controller 11. Programming to the DMA controller 10 is performed by copying the start address of CH1 to the start address of CH5 and the current address. The current address of CH5 increases every time a unit amount of data is transferred from the hard disk 12 to the buffer 9-1. The programming for the HD controller 11 includes the value of the current pointer ((49000) in this example), the number of remaining data of the current table element calculated in 4-5 (900 in this example),
And the mode detected in 4-4 (reproduction mode in this example).

As a result, the HD controller 11 requests the DMA controller 10 to perform a DMA transfer from the hard disk 12 to the buffer 9-1 (outputs DREQ), and the DMA controller 10 executes the corresponding DMA transfer. Will be. Subsequently, the CPU 1 updates the current pointer to a value to be obtained as a result of executing the transfer processing (4-8). In the example of FIG. 12, the current pointer is updated to 30,000 and the next table element (FIG.
In the example of (2), the processing shifts to the second table element from the top). Then, the number of data transferable to the buffer 9-1 is also updated (4100 in this example) (4-8).

Then, returning to step 4-5, the number of remaining data of the current table element of the reproduction schedule table to which the current pointer belongs is calculated (200 in the example of FIG. 12, since it is from 30000 to 30199). Next, the number of remaining data (200) is compared with the number of data that can be transferred to the buffer 9-1 (4100) (4-6). In this example, since the number of data transferable is large, in 4-7, the data indicated by the table element is stored in the buffer 9-1.
Transfer to

This data transfer is performed by programming the DMA controller 10 using the current pointer and the number of remaining data. With this programming, the start and current address of CH5 are
H1 is set to the value of the start address, and when the current address increases by the number of remaining data, the hard disk 1
2 to the buffer 9-1.

During the 4-7 transfer period, the CPU 1
May execute the main routine of FIG. 3 and return to the interrupt routine of FIG. 4 in accordance with a notification from the DMA controller 10 or the HD controller 11 of the completion of the transfer. Upon completion of this data transfer, the current pointer is updated to 120100 (FIG. 12), and the number of data transferable is updated to 3900 (4-8).

Next, returning to 4-5, the number of remaining data of the table element is calculated again. In this case, the remaining data number is 19800 = (139899−120100 + 1), which is larger than the data transferable number of 3900.
From -6 to 4-10, 3900 data are transferred from the address 120100 of the hard disk 12.
Further, the process proceeds to 4-11, where the current pointer is set to 1240.
It is updated to 00.

After 4-11, the process proceeds to 4-12, where it is determined whether or not the punch-in end flag is turned on. In 9-3 of FIG. 9, when the punch-in end flag is turned on, the process proceeds from 4-12 to 4-13, and the DMA transfer of the punch-in buffer 9-4 to the hard disk 12 is prohibited. This prohibits the data in the punch-in buffer 9-4 from being transferred and recorded on the hard disk 12 after punching out.

After the DMA transfer prohibition process of the punch-in buffer 9-4 to the hard disk 12 has been executed, or if it is determined in 4-12 that the punch-in end flag has not been turned on, the process returns to the main routine.

As will be apparent from the following description, when the first interrupt routine (FIG. 4) is started and the HD controller 11 is operated once, every time the transfer of the data block designated by the CPU 1 is completed, , An interrupt is issued from the HD controller 11 (the INT signal is
The CPU 1 only determines whether the recording / playback operation has been completed, whether there has been a key input such as punch-in or punch-out, or whether a trigger specified in the control data has been applied. .

That is, the CPU 1 refers to the current pointer (RAM3) in 3-9 and judges whether or not the memory area is over, that is, whether or not to end (3-1).
0), in the case of YES, each of the voice input / output devices 8-1 to 8-
The A / D conversion and D / A conversion operations of 4 are stopped (3-11), and when it is determined in 3-12 that the punch-in editing has not been performed, the process returns to 3-1. If NO in 3-10, the process returns to 3-9 to check the current pointer.

If it is determined in 3-12 that punch-in editing has been performed, the process proceeds to 3-13, where 8-1 in FIG.
Punch-in points set and stored in, and FIG.
The schedule table is changed based on the punch-out points set and stored in 9-1. Therefore,
In the subsequent normal reproduction, reproduction is performed in a state of being replaced with punch-in data.

As described above, at the time of play / record, after performing the initial setting of 3-4 to 3-8, the CPU 1 repeatedly executes the steps 3-9 and 3-10, and Respond to a change instruction (for example, pause (A / D, D / A interruption) or punch-in / out (A / D, D / A operation switching) for a certain track) or a change in control data obtained during editing Then, the DMA transfer control is immediately suspended, the program is changed, and the same processing is performed again.

Next, with reference to FIG. 8, the operation when the keyboard 4 is operated and a punch-in is instructed will be described. At this time, a punch-in trigger interruption process shown in FIG. 8 is executed. That is, in 8-1, the start address of the punch-in buffer 9-4 is calculated, and the start address is stored as the punch-in point. This start address is calculated from the current address of the punch-in buffer 9-4 and the point offset set in 3-3 in FIG. That is, as shown in FIG. 10, before the punch-in trigger is input, the punch-in buffer 9-4 stores the voice input / output device 8 in its current address.
-4 are sequentially written. Since this data is not transferred to the hard disk 12, the punch-in buffer 9-4 sequentially accumulates the input punch-in data, and only overwrites the punch-in data when the data exceeds the capacity. Therefore, when the punch-in trigger is input, the punch-in data supplied before that is already written in the punch-in buffer 9-4.

Therefore, by using data from an address that is returned from the current current address by a predetermined offset value as punch-in data to be transferred to the hard disk 12, a delay in punch-in key input can be compensated. That is, for example, when the punch-in key is operated at a predetermined timing while listening to the audio signal to be punched-in being reproduced from the buffer 9-2, the timing at which the punch-in trigger is actually generated from the punch-in point desired by the user becomes: It will be slightly slower.
By setting an offset value corresponding to the delay, the delay can be compensated.

As described above, by setting the start address to a position which is returned from the current address by an amount corresponding to the offset value, data from this start address is sequentially transferred to the hard disk 12, so that
Data including the offset value can be transferred.

Next, the process proceeds to 8-2, where the punch-in buffer 9
-4 is programmed to permit DMA transfer to the hard disk 12. Thereby, the punch-in buffer 9-4 is selected as a transfer target track in 4-3 in FIG. 4, and the data is transferred to the hard disk 12 (FIG. 11). Then, at 8-3, the punch-in track buffer (in this case, the buffer 9-
The program is programmed so that the data transfer to the audio input / output device 8-2 of 2) is prohibited. Thereby, 4-3 in FIG.
In this case, the buffer 9-2 is no longer selected as the transfer target track, and the data written in the buffer 9-2 is supplied to the audio input / output device 8-2, and is subjected to D / A conversion and sound generation. It is stopped (FIG. 11).

On the other hand, when a punch-out command is issued by operating the keyboard 4, a punch-out trigger interrupt routine shown in FIG. 9 is executed. That is, in 9-1, the punch-in track buffer (in this case, the buffer 9-
The current address of 2) is obtained from the current address of the punch-in buffer 9-4. This process is the same as the process 4-2 in FIG. That is, in the punch-in track buffer 9-2, although the data transferred from the hard disk 12 is sequentially written at the start address, the written data is not read out to the audio input / output device 8-2. -3), the DMA controller 10 cannot manage the current address of the buffer 9-2. Therefore,
From the current address of the punch-in buffer 9-4 operating synchronously, the punch-in track buffer 9-2
Is obtained.

Next, at 9-2, programming is performed so that the punch-in track buffer 9-2 can be read. As a result of programming in this way, 4 in FIG.
In -3, the buffer 9-2 is selected as the transfer target buffer, and the data written in the buffer 9-2 is sounded through the audio input / output device 8-2.

At 9-3, the punch-in end flag is turned on. By turning on this flag,
In 4-13 in FIG. 4, reading from the punch-in buffer 9-4 is prohibited. Also, if the hard disk transfer end interrupt routine shown in FIG.
, The data transfer of the punch-in buffer 9-4 is preferentially selected and recorded in a predetermined area of the hard disk 12. In the hard disk 12, independent tracks are formed corresponding to the buffers 9-1 to 9-4. Therefore, the punched-in data is not overwritten on the track to be punched in.
As described in -13, only the schedule table is changed. Therefore, if the schedule table is changed, the original audio signal before the punch-in data is inserted can be reproduced. That is, redoing of editing is possible any number of times.

In the above description, the punch-in trigger is input by operating a key.
Reference numeral 9 indicates that a detection signal generated when the level of the punch-in audio signal exceeds a predetermined reference level is used as a punch-in trigger signal, that is, the punch-in trigger interruption process shown in FIG. 8 is executed in response to this detection signal. Then, the punch-in process can be started automatically. As described above, when the punch-in operation is automatically started when the punch-in audio signal exceeds a predetermined level, the voice signal at the moment of punch-in tends to lack the attack portion. However, in this embodiment, since the audio signal before the trigger signal is input can be secured as punch-in data by offset, such data loss can be prevented.

FIG. 10 shows a state before the punch-in processing is started. In this embodiment, the three tracks Tr1 to Tr3 are in a reproduction state. Accordingly, in this case, the buffer 9-1 is stored in the hard disk 12.
Data is sequentially time-divisionally transferred from tracks of channels corresponding to .about.9-3. And buffers 9-1 to 9
-3 are the voice input / output devices 8-1 to 8-1
After being supplied to 8-3 and D / A converted, the sound is generated.
In this state, an audio signal input from the outside is A / D converted and written into the punch-in buffer 9-4 by the audio input / output device 8-4. However, the data written in the punch-in buffer 9-4 has not been transferred to the hard disk 12.

FIG. 11 shows a state during the punch-in operation. At this time, the data written in the punch-in buffer 9-4 has been read and transferred to the hard disk 12. On the other hand, in the track Tr2 targeted for punch-in, data is sequentially transferred from the hard disk 12 to the buffer 9-2 and written therein, but the written data is not read out and the sound generation of the track Tr2 is stopped.

<Operation of Audio Input / Output Devices 8-1 to 8-4>
Next, an operation state of the audio input / output devices 8-1 to 8-4 will be described with reference to FIG. This flowchart may be based on microprogram control or hard logic control, and various means for implementing functions can be selected.

At 5-1 a judgment is made as to whether or not a designation signal CS of the audio input / output device has arrived from the CPU 1 (active).
In 2, the CPU 1 sets an operation state (record, play, stop, etc.).

Then, if a negative determination is made in 5-1, in 5-3, the voice input / output devices 8-1 to 8-1
It is determined whether 8-4 is a record state or a play state.
Proceed to the processing of 4 to 5-9, and if it is determined that the playing state is
The process proceeds to -10 to 5-15.

First, the operation of the voice input / output device set in the record state will be described. At 5-4, it is determined whether or not the sampling time has come, and this 5-4 is repeated until the sampling time comes. In addition, the determination of the sampling time may be performed by the output of each of the audio input / output devices 8-1 to 8-4 using a hard timer in each of the audio input / output devices 8-1 to 8-4.
Alternatively, a common hardware timer may be provided so that each audio input / output device operates according to the output. As will be understood from the following description, each of the audio input / output devices 8-1 to 8-1.
It is also possible to use different sampling frequencies of 8-4.

If the determination of YES is made in 5-4, the applied analog audio signal is sampled and held (S / H) in 5-5 and A / D converted. Subsequently, in 5-6, the DMA transfer request DRQ is activated and output to the DMA controller 10.

The DMA controller 10 receives the request signal DRQ and outputs an answer signal DAK for performing DMA transfer (detailed operation in this case will be described later). Therefore, the audio input / output devices 8-1 to 8-4 are
If the determination at 7 is YES, the process proceeds to 5-8, where the digital audio data obtained by the A / D conversion is output to the data bus and sent to the corresponding buffers 9-1 to 9-4. And 5-9
, The DMA transfer request DRQ is made inactive.
Accordingly, an analog audio signal supplied from the outside is converted into a digital audio signal at each sampling period, and is transferred to the current addresses of the buffers 9-1 to 9-4 specified by the DMA controller 10 as described later.

If it is determined in step 5-3 that the player is in the play state, the flow advances to step 5-10 to activate the DMA transfer request DRQ to the DMA controller 10 and wait for the response signal DAK from the DMA controller 10 (5). −
11), fetch digital voice data on the data bus (5-12), and inactivate the request DRQ (5-13). The operation of the DMA controller 10 at this time will be described later. For example, the contents of the current addresses of the buffers 9-1 and 9-2 corresponding to Tr1 and Tr2 (the contents of the areas of Tr1 and Tr2 of the hard disk 12 are already transferred) Recorded) are input and set to the audio input / output devices 8-1 and 8-2 by the above operation.
Then, it is determined whether or not the sampling time has come (5.
-14). The meaning of detecting the arrival of the sampling time is the same as in the case of 5-4.

If the answer is YES in 5-14, 5-1
Proceed to 5 to execute D / A conversion and low-pass filtering, and then output an analog audio signal to the outside.

The operation at one sampling time in the case of the record state and the case of the play state has been described above. However, the processing returns to 5-1 after completion of each processing of 5-9 and 5-15, and so on. And processing for the sampling time.

<Operation of DMA Controller 10>
The operation of the DMA controller 10 will be described with reference to FIG. The flowchart of FIG. 6 may represent that the service controller 108 of FIG. 2 operates under microprogram control, or the function of the DMA controller 10 may be realized by hard logic.

First, in 6-1, the designation signal CS from the CPU 1 has arrived (is active).
It is determined whether the read signal RD or the write signal WR is supplied from the CPU 1 at 6-2 if YES, and if it is the read signal RD, the process proceeds to 6-3 and is supplied via the address bus. The contents of the registers 104 and 105 specified by the address signal are output via the data bus so that the CPU 1 can read them. Conversely, if the write signal WR, the process proceeds to 6-4, and the specified register is transferred to the specified register via the data bus. Desired data is input and set. Accordingly, desired data is set in each of the registers 104 and 105 in FIG. 2 by the processing of 6-4.

The DMA from such a CPU 1
When the access to the controller 10 or the program is completed, the designation signal CS is made inactive, and 6-1 to 6
The process proceeds to -5.

In 6-5, each of the audio input / output devices 8-1 to 8-8
-4, DMA transfer requests DRQ1 to DRQ4 have been received from the HD controller 11,
It is determined whether (DRQ5) is received, and if a request is received from any of them, the process proceeds to 6-6, where the DMA enable signal DMA
ENB is set to “1” (active), and the address bus and data bus in the DMA unit are connected to the DMA controller 10.
, So that access from the CPU 1 is not accepted.

Subsequently, for a plurality of requests, a channel is selected according to the priority order of channels CH4, CH1 to CH3, and CH5 (6-7). For example, immediately after sampling, the audio input / output device of Tr2 and Tr3 8-
When data transfer requests from 2, 8-3 are made at the same time,
Since the priority of Tr2 is high, the DMA transfer of CH2 is performed first. As will be understood from the description below, since the priority of CH5 is the lowest, when data is transferred between the hard disk 12 and one of the buffers 9-1 to 9-4, any audio input is performed. Output device 8
When a data transfer request is made from -1 to 8-4, the latter data transfer is performed with priority first.

Subsequently, the selected channel (eg, CH
2) Current address (C of address register 104)
The content of the H2 current address register) is output to the address bus (6-8). Then, referring to the contents of the control register 105 of the selected channel (for example, CH2), it is determined in which direction the DMA transfer is to be performed (6-9), and if the buffer 9-1 to 9-4 has another element (I If the transfer is to (/ O), the process proceeds from 6-10 to 6-11, where the read signal RD is given to the buffer selected from among the buffers 9-1 to 9-4, and conversely, the other element (I /
6-1 if transfer from O) to buffers 9-1 to 9-4
Proceed to 2 to apply the write signal WR to the buffer.

Thereafter, the answer signal DAK is activated (6-13). As a result, for example, the buffer 9-2
The audio data read from the area of the current address is sent to the data bus by the processing of 5-11 and 5-12 (FIG. 5) and supplied to the audio input / output devices 8-2 and 8-3. .

In 6-14, since the data transfer has been completed,
The read signal RD or the write signal WR, the answer signal D
AK is made inactive, and the contents of the current address (in the address register 104 in FIG. 2) of the channel (for example, CH2) are incremented by 1 in 6-15. This 6-15
The current address is incremented each time new sampled audio data is written into the buffers 9-1 to 9-4 or whenever new audio data is read out. Then, after the process of 6-15, the process returns to 6-1.

For example, a data transfer request from the voice input / output devices 8-2 and 8-3 of Tr2 and Tr3 in the play mode is D
If it is done for MA controller 10,
Since the data transfer has been executed only for Tr2 so far, YES is determined in the following 6-5. Hereinafter, with respect to Tr3, data transfer from the buffer 9-3 to the audio input / output device 8-3 is performed in 6-7 to 6-6.
-10, 6-12 to 6-15 are executed in the same manner as described above.

When such data transfer is completed, 6-5
To 6-16, the DMA enable signal is set to "0" (inactive), the DMA controller 10 stops occupying the data bus and the address bus in the DMA unit, and the access from the CPU 1 can be accepted. To

The Tr2, Tr set in the play mode as described above
3, the transfer of data from the buffers 9-2 and 9-3 to the audio input / output devices 8-2 and 8-3 has been described. Data transfer from 8-4 to buffers 9-1 to 9-4 is performed by DMA controller 10.

For example, if all of the Tr1 to Tr3 are in the play mode, the audio input / output devices 8-1 to 8-3 corresponding to the Tr1 to Tr3 are located between the sampling time t and the next sampling time t + 1. , And outputs a request signal DRQ to the DMA controller 10 (FIGS. 5, 5-1).
0).

In response, the DMA controller 10
Executes 6-5 to 6-7 in the same manner as described above, and supplies address data indicating the address to be read from the buffer 9-1 via the address bus at 6-8. 6-9,
By executing 6-10, the process proceeds to 6-11, in which the read signal RD is supplied to the buffer 9-1, and the answer signal DAK is set to "1" at 6-13.

As a result, the digital audio data at the designated address in the buffer 9-1 is transferred to the Tr1 via the data bus.
To the voice input / output device 8-1. Then, through the processing of 6-14 and 6-15, 6-
Return to 1.

The DMA controller 10 also transfers data between the hard disk 12 and the buffers 9-1 to 9-4. In this case, the address register 104 and the control register 105 of the channel CH5 are used. This operation is performed by executing an interrupt routine (FIG. 4) of the CPU 1 and after setting / control operations 4-2, 4-3, and 4-9 for the DMA controller 10 and a programming operation 4-9 for the HD controller 11.
Be executed.

The CP for the DMA controller 10
The DMA controller 10 performs the processes of 6-3 and 6-4 in accordance with the setting / control operations 4-2, 4-3 and 4-9 of U1. That is, the CPU 1 determines the track to which the data is transferred by the current channel CH5, and sets the start address of the buffer corresponding to the track (that is, the address next to the block data for which the data was previously transferred between the buffer and the hard disk 12). The start address register (in the address register 104 of FIG. 2) is set in the start address register, and the current data transfer number for this track is set to the start address and the current address (the address incremented after the previous data transfer with the hard disk 12). ) And copy the current address for this track to the start address.

The CPU 1 performs data transfer between the buffers 9-1 to 9-4 corresponding to the operating track and the hard disk 12 in order for each track. Data transfer following transfer (block transfer) is performed.

Then, the CPU 1 controls the HD controller 11
, The HD controller 11 generates an actual transfer request to start the DMA transfer.

When the DMA controller 10 detects that there is a transfer request from the HD controller 11 in 6-5, the DMA controller 10 executes 6-6 to 6-9 in the same manner as described above, and then executes the buffers 9-1 to 9-. 4 to hard disk 12
A request for data transfer in the direction of the direction or a request for data transfer from the hard disk 12 to the direction of the buffers 9-1 to 9-3.
The determination is made at -10, and if the former, the process proceeds to 6-11, and if the latter, the process proceeds to 6-12, and then the processes of 6-13 and 6-15 are executed. At this time, for example, one sample of digital audio data is transferred by one transfer operation.
These operations 6-5 to 6-15 are repeatedly executed a plurality of times to perform block transfer. This hard disk 12
For the data transfer between the buffer and the buffers 9-1 to 9-4,
The operation of the HD controller 11 is also closely related, and will be further described later.

When the DMA transfer is completed, the request signals DRQ1 to DRQ5 do not arrive, and 6-5 to 6-16
Then, the DMA enable signal DMAENB is set to "0" (inactive).

<Operation of HD Controller 11> Next, the operation of the HD controller 11 will be described with reference to FIG.
The HD controller 11 may be controlled by hard logic or by microprogram control, and in any case, implements the operation flow of FIG.

First, it is determined whether the designation signal CS is given from the CPU 1 (7-1). This is given by the interrupt routine of the CPU 1 (4-9 in FIG. 4).
In the case of NO, it returns to the original, but in the case of YES, 7-2
It is determined whether a read signal RD or a write signal WR is supplied from the CPU 1 at the time of reading, and at the time of reading, designated data (contents of an address register, etc.) inside the HD controller 11 is read via a data bus at 7-3. C
Output to PU1.

When the write signal WR is given, the process proceeds from 7-2 to 7-4, and the data transfer direction between the hard disk 12 and the buffer for DMA transfer on the channel CH5 of the DMA controller 10 this time is set. 7-
At 5, the access point of the hard disk 12 to be accessed is set. This is based on the access pointer of the track obtained by the CPU 1 from the RAM 3.

Subsequently, in step 7-6, the number of transfer data (the number of digital audio data) is set in an internal counter of the HD controller 11. This transfer data number is obtained in 4-9 in the interrupt routine of the CPU 1.

As described above, by executing 7-4 to 7-6, the HD controller 1 is controlled under the control of the CPU 1.
1 is programmed, then the HD controller 11
Requests data transfer to the MA controller 10 (7-7). As understood from this, CPU
1 is an interrupt signal IN from the HD controller 11.
When receiving T, it corresponds to the next track (that is, assuming that all of Tr1 to Tr4 are now in operation, Tr4, Tr4
1, Tr2, Tr3, Tr5, Tr4,...) D
The setting and control of the MA transfer are executed for the DMA controller 10 and the HD controller 11 is programmed. Thereafter, the CPU 1 separates from the HD controller 11 and the DMA controller 10 and causes the actual DMA transfer to be executed by mutual interaction.

[0124] The HD controller 11 proceeds from 7-7 to 7
-8, the answer signal DA from the DMA controller 10
7-8 are repeated until CK (DAK5) is received (see FIG. 6, 6-13).

If the determination in 7-8 is YES, the process proceeds to 7-9, where the operation of CH5 of the DMA controller 10 causes
One sample of digital audio data is transferred, and 7-
The transfer counter set in 6 is counted down by 1 (7-10). In the following 7-11, judgment is made according to the contents of the transfer counter as to whether or not the data transfer for the preset number of transfer data has been completed.
Return to -8. Therefore, in the DMA controller 10, the transfer request DRQ5 is kept until the transfer (block transfer) of the number of data set from the HD controller 11 is completed.
Will be received continuously, and according to this transfer request, 6
The processes of -5 to 6-15 (FIG. 6) are executed, and the HD controller 11 executes the processes of 7-8 to 7-11 in response thereto.

When the end of the transfer is determined in step 7-11, the flow advances to step 7-12, where the HD controller 11
Request DRE for data transfer to A controller 10
Q (DRQ5) is set to “0” (inactive). Then, the HD controller 11 supplies an interrupt signal INT to the CPU 1 in order to transfer data between the hard disk 12 and one of the buffers 9-1 to 9-4 for the next track (7-13). In response to this, the CPU 1 executes the interrupt routine (FIG. 4) as described above.

In the above embodiment, the hard disk 12 is used as a recording medium. However, a random access type recording medium may be used. For example, a magneto-optical disk may be used.

[0128]

According to the digital recorder of the present invention, the audio signal for punch-in is stored in the first storage means, and the audio signal reproduced from the recording medium is stored in the second storage means. Since both are operated in parallel, it is possible to prevent a delay in operation at the time of punch-in or to prevent a silent portion from occurring at the time of punch-out.

According to the digital recorder of the second aspect, since the punch-in is instructed when the level of the punch-in audio signal exceeds the reference level, the punch-in operation can be automated.

According to the digital recorder of the present invention, since the audio signal offset from the punch-in time is used as the punch-in data, the punch-in operation can be compensated for and the punch-in can be performed at an accurate position. Becomes

According to the digital recorder of the fourth aspect, the second recorder at the time of punch-in or immediately after punch-out is used.
Since the address of the storage means is obtained from the address of the first storage means, the punch-in data can be accurately managed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital recorder according to the present invention.

FIG. 2 is a block diagram showing a configuration of one embodiment of a DMA controller in FIG. 1;

FIG. 3 is a flowchart of a main routine for explaining the operation of the embodiment of FIG. 1;

FIG. 4 is a flowchart of a hard disk transfer end interrupt routine for explaining the operation of the embodiment of FIG. 1;

FIG. 5 is a flowchart illustrating an operation of the voice input / output device in FIG. 1;

FIG. 6 is a flowchart illustrating the operation of the DMA controller in FIG. 1;

FIG. 7 is a flowchart illustrating an operation of the HD controller in FIG. 1;

FIG. 8 is a flowchart of a punch-in trigger interrupt routine for explaining the operation in the embodiment of FIG. 1;

FIG. 9 is a flowchart of a punch-out trigger interrupt routine for explaining the operation in the embodiment of FIG. 1;

FIG. 10 is a diagram for explaining an operation at the time of reproduction in the embodiment of FIG. 1;

FIG. 11 is a diagram illustrating an operation at the time of punch-in in the embodiment of FIG. 1;

FIG. 12 is a diagram illustrating a reproduction schedule table.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 ROM 3 RAM 8-1 to 8-4 Audio input / output device 9-1 to 9-4 Buffer 10 DMA controller 11 HD controller 12 Hard disk 19 Comparator

Claims (4)

(57) [Claims] 1. A recording medium on which an audio signal is recorded, and a first recording medium on which an input punch-in audio signal is written.
Storage means operate in parallel with the first storage means, second storage means for audio signal reproduced from the recording medium is written, a command means for commanding the punch in and out, punch is Before instructed, write on the recording medium
The stored audio signal is read out and stored in the second storage means.
Recorded in the first storage means.
Continue writing only without reading the audio signal
When a punch-in is instructed, the audio signal written in the first storage means is read and recorded on the recording medium, and the reading of the audio signal written in the second storage means is stopped. And when only punch-out is instructed, the first
Control means for stopping recording of the audio signal written in the storage means on the recording medium and restarting reading of the audio signal written in the second storage means. Digital recorder. 2. The digital recorder according to claim 1, wherein said command means detects a level of the audio signal for punch-in and issues a punch-in command when the level exceeds a predetermined reference level. 3. The recording medium according to claim 1, wherein the control unit is configured to control the recording medium from an audio signal at a time offset by a predetermined time before a punch-in command is issued, from among the audio signals written in the first storage unit. The digital recorder according to claim 1 or 2, wherein the digital recorder is recorded. 4. The apparatus according to claim 1, wherein said control means obtains an address of said second storage means at the time of punch-in or immediately after punch-out from an address of said first storage means. Digital recorder.