JPH0513526A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0513526A JPH0513526A JP16138591A JP16138591A JPH0513526A JP H0513526 A JPH0513526 A JP H0513526A JP 16138591 A JP16138591 A JP 16138591A JP 16138591 A JP16138591 A JP 16138591A JP H0513526 A JPH0513526 A JP H0513526A
- Authority
- JP
- Japan
- Prior art keywords
- lands
- contact
- contact pin
- substrate
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、基板上にランドを配置
してある、例えば混成集積回路装置等の半導体装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, such as a hybrid integrated circuit device, in which lands are arranged on a substrate.
【0002】[0002]
【従来の技術】図3は従来の半導体装置を示す平面図で
あり、図中1は厚膜基板である。厚膜基板1の縁には矩
形のランド2,2,…がピッチAで配置されている。こ
のようなランド2,2,…に図4に示した如く鉛筆型の
コンタクトピン3,3,…を接触させて回路の検査を行
う。図3及び図4においてrはコンタクトピン3,3,
…の半径、Bはコンタクトピン3,3,…の間隔を示
す。以上の如くにして回路の検査を行った後、ランド
2,2,…にリ−ドを付ける。2. Description of the Related Art FIG. 3 is a plan view showing a conventional semiconductor device, in which 1 is a thick film substrate. Rectangular lands 2, 2, ... Are arranged at a pitch A on the edge of the thick film substrate 1. The lands 2, 2, ... Are contacted with pencil-type contact pins 3, 3, ... As shown in FIG. 3 and 4, r is the contact pin 3, 3,
, Radius B indicates the distance between the contact pins 3, 3 ,. After inspecting the circuit as described above, the leads are attached to the lands 2, 2, ....
【0003】[0003]
【発明が解決しようとする課題】以上の如き半導体装置
においては、コンタクトピン3,3,…の接触を避ける
ために所定のコンタクトピン3,3の間隔Bを維持しな
ければならない。従ってランドのピッチAが短い場合に
はコンタクトピン3,3,…の半径rを小さくすること
になり、コンタクトピン3,3,…を固定するプローブ
カードに精密で困難な加工を施す必要が生じていた。コ
ンタクトピンの径が小さくなると許容電流容量が小さく
なり、ピンに加え得る針圧が小さくなるので確実な接触
ができず、正確な検査を行なうことができない等の問題
があった。In the semiconductor device as described above, the predetermined distance B between the contact pins 3, 3 must be maintained in order to avoid contact between the contact pins 3, 3, .... Therefore, when the land pitch A is short, the radius r of the contact pins 3, 3, ... Is reduced, and it becomes necessary to perform precise and difficult processing on the probe card for fixing the contact pins 3, 3 ,. Was there. When the diameter of the contact pin is reduced, the allowable current capacity is reduced, and the stylus pressure that can be applied to the pin is reduced, so that reliable contact cannot be made and accurate inspection cannot be performed.
【0004】本発明は斯かる事情に鑑みなされたもので
あり、基板の縁からの長さが異なるランドを相隣させて
配置することにより、径が大きくて許容針圧が高いコン
タクトピンの使用を可能にし、プローブカードに精密で
困難な加工を施す必要がなく、検査の信頼性を向上させ
ることができる半導体装置を提供することを目的とす
る。The present invention has been made in view of the above circumstances and uses contact pins having a large diameter and a high allowable stylus pressure by arranging lands having different lengths from the edge of a substrate adjacent to each other. It is an object of the present invention to provide a semiconductor device capable of improving the reliability of inspection without requiring precise and difficult processing on the probe card.
【0005】[0005]
【課題を解決するための手段】本発明に係る半導体装置
は、複数のリ−ドを実装すべき基板上に、基板の縁から
の長さが異なるランドを相隣させて配置するものであ
る。In a semiconductor device according to the present invention, lands having different lengths from the edge of the substrate are arranged next to each other on a substrate on which a plurality of leads are to be mounted. .
【0006】[0006]
【作用】基板の縁からの長さが異なるランドを相隣させ
て配置することにより、ランドのピッチ及びコンタクト
ピンの間隔が所定値に定められている場合、径が大きく
て許容針圧が高いコンタクトピンの使用を使用すること
が可能になる。By arranging lands having different lengths from the edge of the substrate adjacent to each other, the diameter is large and the allowable stylus pressure is high when the land pitch and the contact pin spacing are set to predetermined values. It becomes possible to use the use of contact pins.
【0007】[0007]
【実施例】図1は本発明に係る半導体装置を示す平面図
であり、図中1は厚膜基板である。厚膜基板1の端部に
は、厚膜基板の縁からの長さがl1 である矩形のランド
2a,2a,…と縁からの長さがl2 (l2 >l1 )で
ある矩形のランド2b,2b,…とが交互に配置されて
いる。Aはこのランド2a,2bのピッチを示す。この
ようなランド2,2,…に図2に示した如く鉛筆型のコ
ンタクトピン4,4,…を接触させて回路の検査を行
う。なお図1及び図2においてrはコンタクトピン4,
4,…の半径、Bはコンタクトピン4,4,…の間隔を
示す。以上の如くにして回路の検査を行った後、ランド
2a,2a,…及びランド2b,2b,…にリ−ドを付
ける。1 is a plan view showing a semiconductor device according to the present invention, in which 1 is a thick film substrate. At the end of the thick film substrate 1 , there are rectangular lands 2a, 2a, ..., Which have a length l 1 from the edge of the thick film substrate, and l 2 (l 2 > l 1 ) from the edge. Rectangular lands 2b, 2b, ... Are alternately arranged. A indicates the pitch of the lands 2a and 2b. The lands 2, 2, ... Are contacted with pencil-type contact pins 4, 4, ... As shown in FIG. 1 and 2, r is a contact pin 4,
The radius of 4, ..., B represents the distance between the contact pins 4, 4 ,. After inspecting the circuit as described above, lands 2a, 2a, ... And lands 2b, 2b ,.
【0008】ランドのピッチAとコンタクトピンの間隔
Bとが一定であるとき、図4に示した従来の半導体装置
では、2r+B=Aの関係式が成り立つからコンタクト
ピンの半径rはr=(A−B)/2で限定される。一
方、図1に示した本発明の半導体装置では、ランド2
b,2b,…において、その先端からl1/2の位置に
コンタクトピン4,4,…を接触させるとすると(2r
+B)2 =A2 +(l2 −l1 )2 の関係式が成り立つ
からコンタクトピンの半径rはr=〔{(l2 −l1 )
2 +A2 }1/2 −B〕/2である。従って、l2 −l1
を大きくさせることでコンタクトピンの半径を大きくす
ることができる。When the land pitch A and the contact pin spacing B are constant, in the conventional semiconductor device shown in FIG. 4, the relational expression of 2r + B = A is established, so that the radius r of the contact pin is r = (A -B) / 2. On the other hand, in the semiconductor device of the present invention shown in FIG.
, b, 2b, ... If the contact pins 4, 4, ... Are brought into contact with the position of l 1/2 from the tip thereof (2r
Since the relational expression of + B) 2 = A 2 + (l 2 −l 1 ) 2 is established, the radius r of the contact pin is r = [{(l 2 −l 1 )
2 + A 2} 1/2 -B] is / 2. Therefore, l 2 −l 1
The radius of the contact pin can be increased by increasing.
【0009】[0009]
【発明の効果】以上の如く本発明の半導体装置において
は、基板の縁からの長さが異なるランドを相隣させて配
置しているので、径が大きくて許容針圧が高いコンタク
トピンの使用を可能にし、検査の信頼性を向上させるこ
とができる。そして、コンタクトピンの径が大きいとプ
ローブカードに精密で困難な加工を施す必要がなくな
り、コンタクトピン自体の寿命が延びてそのメンテナン
ス性が向上する等、本発明は優れた効果を奏するもので
ある。As described above, in the semiconductor device of the present invention, since the lands having different lengths from the edge of the substrate are arranged adjacent to each other, use of the contact pin having a large diameter and a high allowable stylus pressure is used. It is possible to improve the reliability of the inspection. Further, when the diameter of the contact pin is large, it is not necessary to perform precise and difficult processing on the probe card, the life of the contact pin itself is extended, and its maintainability is improved, and the present invention has excellent effects. .
【図1】本発明に係る半導体装置を示す平面図である。FIG. 1 is a plan view showing a semiconductor device according to the present invention.
【図2】ランドにコンタクトピンを接触させて検査を行
うときの実施状態を示す斜視図である。FIG. 2 is a perspective view showing an implementation state when a contact pin is brought into contact with a land to perform an inspection.
【図3】従来の半導体装置を示す平面図である。FIG. 3 is a plan view showing a conventional semiconductor device.
【図4】従来のランドにコンタクトピンを接触させて検
査を行うときの実施状態を示す側面図である。FIG. 4 is a side view showing an implementation state when a contact is brought into contact with a conventional land to perform an inspection.
1 厚膜基板 2a ランド 2b ランド 1 Thick film substrate 2a land 2b land
Claims (1)
べきランドを配置してある半導体装置において、前記基
板の縁からの長さが異なるランドを相隣させて配置して
あることを特徴とする半導体装置。Claim: What is claimed is: 1. In a semiconductor device in which a plurality of leads are to be mounted along an edge of a substrate, lands having different lengths from the edge of the substrate are adjacent to each other. A semiconductor device characterized in that the semiconductor devices are arranged in a row.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16138591A JPH0513526A (en) | 1991-07-02 | 1991-07-02 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16138591A JPH0513526A (en) | 1991-07-02 | 1991-07-02 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0513526A true JPH0513526A (en) | 1993-01-22 |
Family
ID=15734089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16138591A Pending JPH0513526A (en) | 1991-07-02 | 1991-07-02 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0513526A (en) |
-
1991
- 1991-07-02 JP JP16138591A patent/JPH0513526A/en active Pending
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