JPH0513396B2 - - Google Patents
Info
- Publication number
- JPH0513396B2 JPH0513396B2 JP60102697A JP10269785A JPH0513396B2 JP H0513396 B2 JPH0513396 B2 JP H0513396B2 JP 60102697 A JP60102697 A JP 60102697A JP 10269785 A JP10269785 A JP 10269785A JP H0513396 B2 JPH0513396 B2 JP H0513396B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- superconducting
- silica
- insulating film
- metal layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000000034 method Methods 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 60
- 239000000377 silicon dioxide Substances 0.000 description 30
- 239000010410 layer Substances 0.000 description 13
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N60/00—Superconducting devices
- H10N60/01—Manufacture or treatment
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は超電導集積回路の製造方法、より具体
的には超電導金属間の絶縁膜の製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a superconducting integrated circuit, and more specifically to a method of manufacturing an insulating film between superconducting metals.
ジヨセフソン接合素子を利用した超電導集積回
路は、その高速性のため、超大型コンピユータの
構成要素として期待されている。これにはジヨセ
フソン接合素子の高速性を充分生かしたデバイス
設計を行う必要がある。中でも超電導線路の持つ
インダクタンスは高速化を妨げる大きな要因とな
つており、インダクタンスを下げられるデバイス
構造が望まれている。超電導線路のインダクタン
スを下げるためには、層間の絶縁膜をできるだけ
うすくする事が必要である。このことはメモリ動
作を高速化するために非常に重要な問題である。 Superconducting integrated circuits using Josephson junction devices are expected to be used as components of ultra-large computers due to their high speed. To achieve this, it is necessary to design a device that takes full advantage of the high-speed performance of Josephson junction elements. Among these, the inductance of superconducting lines is a major factor hindering speed increases, and a device structure that can reduce inductance is desired. In order to lower the inductance of a superconducting line, it is necessary to make the interlayer insulating film as thin as possible. This is a very important problem for speeding up memory operations.
（従来技術とその問題点）
第３図は従来の超電導集積回路の製造方法の一
例を説明するための図である。従来、絶縁膜とし
ては抵抗加熱蒸着のSiOで形成した膜が多用され
ている。これはジヨセフソン接合の温度耐性が
200℃〜300℃と低く、他の絶縁膜例えばスパツタ
蒸着のSiO2膜やプラズマCVD法によるSi3N4等
は、製造時に300℃以上の温度が必要となるので、
不適当であるためである。しかしながら第３図ａ
に示すごとくSiO膜２２は段差部分にクラツクが
発生しやすい。そのため、超電導膜２１，２３の
間を完全に絶縁するためには、SiO膜２２を超電
導膜２１より充分に厚く蒸着する必要がある（第
３図ｂ）。また超電導膜２１，２３間のコンタク
トをとるため、SiO膜２２を蒸着したあと反応性
イオンエツチング等の技術によりコンタクトホー
ルをあけ、その上に超電導膜２３を堆積する。コ
ンタクトをを完全にするため、また、SiO膜のク
ラツク部で段切れしないよう超電導膜２３はSiO
膜２２より充分厚くする必要がある。したがつて
上層部にいくほど層間絶縁膜の厚さは厚くする事
になる。しかも、SiO膜はピンホールの比較的多
い膜でありこの事からもある程度の厚さが必要と
なる。これらの事から超電導線路のインダクタン
スを充分に小さくすることができず、従来の製造
方法ではおのずと高速化に限度があつた。(Prior art and its problems) FIG. 3 is a diagram for explaining an example of a conventional method for manufacturing a superconducting integrated circuit. Conventionally, a film formed of SiO by resistance heating vapor deposition has been frequently used as an insulating film. This means that the temperature resistance of Josephson junction is
Other insulating films, such as sputter-deposited SiO 2 films and plasma CVD Si 3 N 4 , require temperatures of 300°C or higher during production.
This is because it is inappropriate. However, Figure 3a
As shown in the figure, cracks are likely to occur in the SiO film 22 at the step portions. Therefore, in order to completely insulate between the superconducting films 21 and 23, it is necessary to deposit the SiO film 22 sufficiently thicker than the superconducting film 21 (FIG. 3b). Further, in order to establish contact between the superconducting films 21 and 23, after the SiO film 22 is deposited, a contact hole is made by a technique such as reactive ion etching, and the superconducting film 23 is deposited thereon. The superconducting film 23 is made of SiO to ensure a perfect contact and to prevent breakage at cracks in the SiO film.
It is necessary to make it sufficiently thicker than the film 22. Therefore, the thickness of the interlayer insulating film becomes thicker toward the upper layer. Moreover, the SiO film is a film with relatively many pinholes, and for this reason, a certain degree of thickness is required. For these reasons, it was not possible to reduce the inductance of the superconducting line sufficiently, and conventional manufacturing methods naturally had a limit to how high the speed could be achieved.
（発明の目的）
本発明の目的は、上記従来例の問題点を解決す
るための超電導集積回路の製造方法を提案する事
にある。(Object of the Invention) An object of the present invention is to propose a method for manufacturing a superconducting integrated circuit to solve the problems of the conventional method described above.
（発明の構成）
本発明によれば少なくとも、所望のパターンを
有する第１の超電導金属層を形成する工程と、該
第１の超電導金属層の上部にSi酸化物を主成分と
する被膜を得るためにSi化合物を含む溶液を塗布
及び熱処理して固化し、絶縁被膜と化する工程
と、続いて該絶縁被膜の上部に金属層を堆積し、
該金属層全体を酸化する事により、絶縁体と化す
る工程と、該絶縁体の上部に第２の超電導金属を
堆積する工程を含む事を特徴とする超電導集積回
路の製造方法が得られる。(Structure of the Invention) According to the present invention, there is at least the step of forming a first superconducting metal layer having a desired pattern, and obtaining a film containing Si oxide as a main component on the first superconducting metal layer. For this purpose, a solution containing a Si compound is applied and heat treated to solidify it and become an insulating film, and then a metal layer is deposited on top of the insulating film,
A method for manufacturing a superconducting integrated circuit is obtained, which includes the steps of oxidizing the entire metal layer to make it an insulator, and depositing a second superconducting metal on top of the insulator.
（発明の構成の詳細な説明）
超電導線配線の自己インダクタンスは単位電流
を流した時に蓄えられる磁気的エネルギーで定義
される。今、配線とグランドプレーン間の配線膜
の厚さをtp、配線の巾をＷとすると自己インダク
タンスＬは超電導体中λLまで磁界が侵入している
ことを考慮してＬ＝μp（tp＋2λL）／Ｗで近似でき
る。（ただしμ0は透磁率、配線の厚さはtsはts≫λL
とする。）つまり層間の絶縁膜が厚くなるとイン
ダクタンスは大きくなる。特に微細化が進みＷが
小さくなると、さらにインダクタンスは増し高速
化のさまたげになる。インダクタンスを下げるた
めに絶縁膜をうすくすることは不可欠な技術とな
る。(Detailed explanation of the structure of the invention) The self-inductance of superconducting wire wiring is defined by the magnetic energy stored when a unit current flows. Now, if the thickness of the wiring film between the wiring and the ground plane is t p and the width of the wiring is W, then the self-inductance L is L = μ p ( It can be approximated by t p +2λ L )/W. (However, μ 0 is the magnetic permeability, and the wiring thickness is t s ≫λ L
shall be. ) In other words, the thicker the insulating film between layers, the greater the inductance. In particular, as miniaturization progresses and W becomes smaller, the inductance further increases and becomes a hindrance to speeding up. Making the insulation film thinner is an essential technology to lower inductance.
本発明は超電導層間の絶縁膜にSi化合物を含む
溶液を塗布し、固化する事により得られるSi酸化
物（以下シリカフイルムと呼ぶ）と金属酸化膜を
用いる事で、層間絶縁膜をうすくし、超電導線路
のインダクタンスを下げる事を可能とする超電導
集積回路の製造方法である。シリカフイルム等の
絶縁被膜は本質的にステツプカバレージがよく、
また絶縁膜に二層膜を用いる事でピンホールの問
題も大幅に改善される。 The present invention thins the interlayer insulating film by using a metal oxide film and Si oxide (hereinafter referred to as silica film) obtained by applying and solidifying a solution containing a Si compound to the insulating film between superconducting layers. This is a method for manufacturing superconducting integrated circuits that makes it possible to lower the inductance of superconducting lines. Insulating coatings such as silica film inherently have good step coverage;
Furthermore, by using a two-layer film for the insulating film, the problem of pinholes can be greatly improved.
以下実施例に基づき本発明について説明する。 The present invention will be described below based on Examples.
実施例 １
第１図は本発明の第１の実施例を説明するため
の図である。第１図ａはスパツタ蒸着法により堆
積した超電導膜１の上に、シリカフイルム溶液を
スピン塗布し数100℃の熱処理により固化し、シ
リカフイルム２を形成した状態を示す。シリカフ
イルム溶液は液体状であるので、凹凸のある面に
滴下すると、液体は凹凸面にそつて侵入し、滑ら
かな表面を程して凹凸部分を緩和してしまう。さ
らにシリカフイルム溶液の濃度を適当に選ぶこと
により段差部分はなだらかな傾斜がつき、平坦な
部分ではうすく塗布され、段差を解消する事がで
きる。次に第１図ｂに示されるように常電導金属
膜３（ここでは緻密な膜ができる事がしられてい
るAl膜を用いる）を数10nｍスパツタ蒸着法で堆
積する。ここでウエハー全面にAl膜が形成され
ている事を利用して陽極酸化法でAl膜を酸化し
絶縁膜体に変える。この時、もしAl膜に一部酸
化残りが生じたとしてもシリカフイルムにより絶
縁膜は保たれる。またシリカフイルムは本来500
℃以上の高温で固化する事が望ましいが、ジヨセ
フソン集積回路においては、ジヨセフソン接合後
の工程では200℃以下で固化せざるを得ない。そ
のためシリカフイルムの強度やフツ化物耐性等の
点で問題が残るがここではシリカフイルムの上層
にAl酸化膜を形成する事で、この問題を解決し
ている。このようにシリカフイルムとAl酸化膜
の二層構造により薄いほぼ完全な層間絶縁膜を実
現できる。またピンホールの問題も大幅に改善さ
れる。つづいて第１図ｃに示すごとく、該酸化膜
上に超電導膜４を堆積し、超電導線路を形成す
る。この方法によれば、層間絶縁膜の厚さを非常
にうすくできるため、配線のインダクタンスを極
力下げることが可能で、回路の高速化の効果が得
られる。なおここでは酸化方法として陽極酸化法
を取り上げたがRFプラズマ酸化でも可能である。
さらに、スパツタ法によりAl酸化膜を蒸着する
事もできる。また、絶縁被膜としてシリカフイル
ムを用いたが、その他拡散用不純物を含むシリカ
フイルムやポリイミド等の他の絶縁被膜を用いる
事も可能である。Embodiment 1 FIG. 1 is a diagram for explaining a first embodiment of the present invention. FIG. 1a shows a state in which a silica film solution is spin-coated on a superconducting film 1 deposited by sputter deposition and solidified by heat treatment at several 100° C. to form a silica film 2. Since the silica film solution is in a liquid state, when it is dropped onto an uneven surface, the liquid penetrates along the uneven surface, softening the smooth surface and softening the uneven portion. Furthermore, by appropriately selecting the concentration of the silica film solution, the stepped portions will have a gentle slope, and the flat portions will be coated thinly, making it possible to eliminate the stepped portions. Next, as shown in FIG. 1b, a normal conductive metal film 3 (here, an Al film, which is known to form a dense film, is used) is deposited to a thickness of several tens of nanometers by sputter deposition. Here, taking advantage of the fact that the Al film is formed on the entire surface of the wafer, the Al film is oxidized using an anodic oxidation method to transform it into an insulating film. At this time, even if some oxidation remains on the Al film, the insulating film is maintained by the silica film. Also, silica film is originally 500
Although it is desirable to solidify at a high temperature of ℃ or higher, in the Josephson integrated circuit, solidification must be done at a temperature of 200℃ or lower in the process after Josephson bonding. Therefore, problems remain in terms of strength and fluoride resistance of the silica film, but this problem is solved here by forming an Al oxide film on top of the silica film. In this way, a thin, almost perfect interlayer insulating film can be realized by using the two-layer structure of silica film and Al oxide film. The pinhole problem is also greatly improved. Subsequently, as shown in FIG. 1c, a superconducting film 4 is deposited on the oxide film to form a superconducting line. According to this method, since the thickness of the interlayer insulating film can be made very thin, the inductance of the wiring can be reduced as much as possible, and the effect of increasing the speed of the circuit can be obtained. Note that although anodic oxidation is used as the oxidation method here, RF plasma oxidation is also possible.
Furthermore, an Al oxide film can also be deposited by sputtering. Furthermore, although silica film was used as the insulating film, other insulating films such as silica film containing diffusion impurities or polyimide may also be used.
実施例 ２
第２図は本発明の第２の実施例を説明するため
の図である。この実施例はコンタクトホールの形
成をともなつた本発明の好しい実施様体例であ
る。第２図ａはスパツタ蒸着法により堆積した超
電導膜１１の上に、シリカフイルム溶液をスピン
塗布し数100℃の熱処理により固化し、シリカフ
イルム１２を形成した状態を示す。シリカフイル
ム溶液は液体状であるので、凹凸のある面に滴下
すると、液体は凹凸面にそつて侵入し、滑らかな
表面を程して凹凸部分を緩和してしまう。さらに
シリカフイルム溶液の濃度を適当に選ぶことによ
り段差部分はなだらかな傾斜がつき、平坦な部分
ではうすく塗布され、段差を解消することができ
る。Embodiment 2 FIG. 2 is a diagram for explaining a second embodiment of the present invention. This embodiment is a preferred embodiment of the present invention involving the formation of contact holes. FIG. 2a shows a state in which a silica film solution is spin-coated on a superconducting film 11 deposited by sputter deposition and solidified by heat treatment at several 100° C. to form a silica film 12. Since the silica film solution is in a liquid state, when it is dropped onto an uneven surface, the liquid penetrates along the uneven surface, softening the smooth surface and softening the uneven portion. Furthermore, by appropriately selecting the concentration of the silica film solution, the stepped portions will be gently sloped, and the flat portions will be coated thinly, making it possible to eliminate the stepped portions.
次にレジストステンシル１３を形成してコンタ
クトホールのパターニングを行なう（第２図ｂ）。
次に第２図ｃに示されるように常電導金属膜１５
（ここでは緻密な膜ができる事がしられているAl
膜を用いる）を数10nｍ堆積する。ここでウエハ
ー全面にAl膜が形成されている事を利用して陽
極酸化法でAl膜を酸化し、Al酸化膜１４を形成
する。次にリフトオフによりレジスト１３及び
Al膜１５を除去した後CF4ガス等を用いた反応性
イオンエツチング法によりシリカフイルムにコン
タクトホールをあける（第２図ｄ）。Al酸化膜１
４はエツチングされにくいので、シリカフイルム
１２をパーニングするマスクとして使用される。
またシリカフイルム１２はうすいためにエツチン
グも容易である。この絶縁膜形成法によれば、
Al膜に一部酸化残りが生じたとしても、シリカ
フイルムにより絶縁性は保たれる。またシリカフ
イルムは本来、500℃以上の高温で固化する事が
望ましいが、ジヨセフソン集積回路においては、
ジヨセフソン接合形成後の工程では200℃以下で
固化せざるを得ない。そのためシリカフイルムの
強度やフツ化物耐性等の点で問題が残るが、ここ
ではシリカフイルムの上層にAl酸化膜を形成す
る事で、この問題を解決している。このようにシ
リカフイルムとAl酸化膜の二層構造により薄い
ほぼ完全なかつ、コンタクトホールの形成も容易
な層間絶縁膜を実現できる。また、ピンホールの
問題も大幅に改善される。つづいて第２図ｅに示
すごとく、該酸化膜上に超電導膜１６を堆積し、
超電導線路を形成する。この方法によれば、層間
絶縁膜の厚さを非常にうすくできるため、配線の
インダクタンスを極力下げることが可能で、回路
の高速化の効果が得られる。なおここでは酸化方
法として陽極酸化法を取り上げたがプラズマ酸化
法でも可能である。さらに、スパツタ法により
Al酸化膜を蒸着する事もできる。また絶縁被膜
としてシリカフイルムを用いたが、他に拡散用不
純物を含むシリカフイルムやポリイミド等の絶縁
被膜を用いる事も可能である。 Next, a resist stencil 13 is formed and contact holes are patterned (FIG. 2b).
Next, as shown in FIG. 2c, the normal conductive metal film 15
(Here, we use Al, which is known to form a dense film.)
(using a film) is deposited to a thickness of several tens of nanometers. Here, taking advantage of the fact that the Al film is formed on the entire surface of the wafer, the Al film is oxidized by anodic oxidation to form the Al oxide film 14. Next, resist 13 and
After removing the Al film 15, a contact hole is made in the silica film by reactive ion etching using CF 4 gas or the like (FIG. 2d). Al oxide film 1
Since 4 is difficult to be etched, it is used as a mask for paring the silica film 12.
Furthermore, since the silica film 12 is thin, it can be easily etched. According to this insulating film forming method,
Even if some oxidation remains on the Al film, the insulation is maintained by the silica film. Additionally, it is desirable for silica film to solidify at a high temperature of 500°C or higher, but in Josephson integrated circuits,
In the process after forming the diosefson junction, it is forced to solidify at temperatures below 200°C. Therefore, problems remain with respect to the strength and fluoride resistance of the silica film, but this problem is solved here by forming an Al oxide film on top of the silica film. In this way, the two-layer structure of the silica film and the Al oxide film makes it possible to realize a thin, almost perfect interlayer insulating film in which contact holes can be easily formed. Also, the problem of pinholes is greatly improved. Subsequently, as shown in FIG. 2e, a superconducting film 16 is deposited on the oxide film,
Form a superconducting line. According to this method, since the thickness of the interlayer insulating film can be made very thin, the inductance of the wiring can be reduced as much as possible, and the effect of increasing the speed of the circuit can be obtained. Although the anodic oxidation method is used as the oxidation method here, a plasma oxidation method is also possible. Furthermore, by the spatsuta method
It is also possible to deposit an Al oxide film. Furthermore, although silica film was used as the insulating film, it is also possible to use other insulating films such as silica film containing diffusion impurities or polyimide.
本実施例では金属層としてAlを取り上げたが、
それ以外の常電導金属もしくはNb等の超電導金
属を用いる事も可能である。 In this example, Al was used as the metal layer, but
It is also possible to use other normal conducting metals or superconducting metals such as Nb.
（本発明の効果）
本発明の方法によれば、絶縁膜等をシリカフイ
ルム等の絶縁被膜と金属酸化物との二層構造にす
る事により、段切れやピンホール等の絶縁不良の
ない100nｍ前後のうすい絶縁層を実現する事が
できる。このため配線のインダクタンスの低下が
はかられ、ジヨセフソン接合の高速性を充分生か
した回路を実現できる効果が得られる。特に高速
メモリの高速化がはかられる効果が得られる。ま
た他の効果として、陽極酸化法は酸化膜厚の制御
も容易であり素子の歩留りの向上の効果が得られ
る。(Effects of the present invention) According to the method of the present invention, by forming the insulating film etc. into a two-layer structure of an insulating film such as a silica film and a metal oxide, a thickness of 100 nm without insulation defects such as breakage or pinholes can be achieved. It is possible to realize thin insulation layers on the front and back. Therefore, the inductance of the wiring is reduced, and the effect of realizing a circuit that takes full advantage of the high-speed properties of Josephson junctions is achieved. In particular, the effect of increasing the speed of high-speed memory can be obtained. Another advantage of the anodic oxidation method is that the oxide film thickness can be easily controlled, resulting in an improvement in the yield of devices.
第１図ａ〜ｃ、第２図ａ〜ｅは、本発明の第
１、第２の実施例を示す構造工程の断面図であ
り、第３図ａ，ｂは従来の超電導集積回路の製造
方法の一例として、SiO膜よりなる絶縁膜を用い
た製造工程の断面図である。
それぞれの図において、１……超電導膜、２…
…シリカフイルム、３……Al酸化膜、４……超
電導膜、１１……超電導膜、１２……シリカフイ
ルム、１３……レジスト、１４，１５……Al酸
化膜、１６……超電導膜、２１……超電導膜、２
２……SiO膜、２３……超電導膜を示す。
1a to 2c and 2a to 2e are cross-sectional views of the structural steps showing the first and second embodiments of the present invention, and FIGS. 3a and 3b are sectional views of conventional superconducting integrated circuit manufacturing. As an example of the method, it is a cross-sectional view of a manufacturing process using an insulating film made of an SiO film. In each figure, 1... superconducting film, 2...
... Silica film, 3 ... Al oxide film, 4 ... Superconducting film, 11 ... Superconducting film, 12 ... Silica film, 13 ... Resist, 14, 15 ... Al oxide film, 16 ... Superconducting film, 21 ...Superconducting film, 2
2...SiO film, 23... superconducting film.
Claims (1)
超電導金属層を形成する工程と、該第１の超電導
金属層の上部にSi酸化物を主成分とする被膜を得
るためにSi化合物を含む溶液を塗布及び熱処理し
て固化し、絶縁被膜と化す工程と、続いて該絶縁
被膜の上部に金属層を堆積し、該金属層全体を酸
化する事により、絶縁体と化する工程と、該絶縁
体の上部に第２の超電導金属を堆積する工程を含
む事を特徴とする超電導集積回路の製造方法。1 At least a step of forming a first superconducting metal layer having a desired pattern, and applying a solution containing a Si compound on the top of the first superconducting metal layer to obtain a film mainly composed of Si oxide. and heat treatment to solidify and turn into an insulating film, followed by depositing a metal layer on top of the insulating film and oxidizing the entire metal layer to turn it into an insulator; A method for manufacturing a superconducting integrated circuit, comprising the step of depositing a second superconducting metal on top.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60102697A JPS61263178A (en) | 1985-05-16 | 1985-05-16 | Manufacture of superconducting integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60102697A JPS61263178A (en) | 1985-05-16 | 1985-05-16 | Manufacture of superconducting integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61263178A JPS61263178A (en) | 1986-11-21 |
| JPH0513396B2 true JPH0513396B2 (en) | 1993-02-22 |
Family
ID=14334448
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60102697A Granted JPS61263178A (en) | 1985-05-16 | 1985-05-16 | Manufacture of superconducting integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61263178A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710752B2 (en) * | 1972-10-28 | 1982-02-27 | ||
| JPS59105339A (en) * | 1982-12-08 | 1984-06-18 | Nec Corp | Manufacture of semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710752U (en) * | 1980-06-20 | 1982-01-20 |
-
1985
- 1985-05-16 JP JP60102697A patent/JPS61263178A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5710752B2 (en) * | 1972-10-28 | 1982-02-27 | ||
| JPS59105339A (en) * | 1982-12-08 | 1984-06-18 | Nec Corp | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61263178A (en) | 1986-11-21 |
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| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |