JPH0513359A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make a film of uniform thickness and reduce contact resistance of the film with metal interconnections by re-forming a metal silicide layer after the previous silicide layer is removed when contact holes for source and drain regions are opened. CONSTITUTION:A refractory metal silicide layer 11, such as of titanium, is formed on the surface of source and drain regions of a MISFET. After an insulating film 12, like PSG, is deposited, contact holes 13 are opened. Exposed portions of the silicide layer 11 is removed by down-blow plasma etching using chlorine gas, and then a titanium film 13 is deposited to a thickness of 5-600 angstroms by sputtering. A titanium silicide film 16 is formed by a heat treatment at approximately 800 deg.C. A titanium film 15, not converted to silicide, is removed by etching with a mixture of ammonia and oxygen peroxide, and then an aluminum interconnection 14 is formed by sputtering and patterning. According to this method, the metal silicide layer 16 has a uniform thickness without damage; therefore, its contact resistance with metal interconnections is reduced and has less unevenness.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a MIS field effect transistor (hereinafter referred to as MISFET) having a metal source / drain.

[0002]

2. Description of the Related Art To increase the operating speed of MISFET,
It is necessary to reduce the contact resistance between the source / drain of the MISFET and the metal wiring as much as possible. MI with metal source / drain was developed in response to this demand.
It is an SFET.

MISF having metal source / drain
ET is a MISFE in which the surface layer of the source / drain is metal-silicided, and the source / drain and the metal wiring are connected via the metal silicide to reduce the contact resistance and further reduce the surface resistance of the source / drain.
T.

A method of forming a MISFET having a metal source / drain according to the prior art will be described with reference to FIGS. 2 and 3. As shown in FIG. 2A, the surface of an element formation region of, for example, a p-type silicon substrate 1 which is element-isolated with a LOCOS field oxide film 2 and a channel prevention layer 3 is oxidized by a known method to oxidize it. A silicon insulating film 4 is formed, and a laminated body of a gate electrode 5 made of polycrystalline silicon and a silicon dioxide film 6 is formed on the silicon insulating film 4. Then, the n-type impurity is ion-implanted at a low concentration to form the low-impurity concentration region 7.

A silicon dioxide film is deposited on the entire surface and anisotropic dry etching is performed, as shown in FIG.
From the source / drain formation region to the silicon dioxide insulating film 4
Then, the silicon dioxide film 8 remains on the side wall of the gate electrode 5, and then n-type impurities are ion-implanted to form the source / drain 9.

As shown in FIG. 2C, a refractory metal film 10 of titanium, molybdenum, tungsten, tantalum or the like is formed to a thickness of 5 to 600 Å by using a sputtering method. 800
When heat treatment is performed by heating to a temperature of about .degree. C., the refractory metal undergoes a solid phase reaction with silicon to form a metal silicide layer 11 on the surface layer of the source / drain 9 as shown in FIG. . The refractory metal film 10 in the non-silicided region is removed by etching using a mixed solution of ammonia and hydrogen peroxide solution.

As shown in FIG. 3 (e), an insulating film 12 such as a PSG film is formed by using a CVD method, and then, although not shown, a photolithography method is used to form an opening in a contact hole forming region. A resist film having the same is formed, and reactive ion etching is performed using a mixed gas of carbon tetrafluoride (CF ₄ ) and fluoroform (CHF ₃ ) using this resist film as a mask to form a contact hole in the insulating film 12. Form 13.

As shown in FIG. 3 (f), an aluminum film is formed by using the sputtering method, and this is patterned to form an aluminum wiring 14.

[0009]

When the contact hole is miniaturized, it is inappropriate to use an isotropic etching method represented by wet etching for forming the contact hole, and an anisotropic shape is generally obtained. A dry etching method is used.

In the case of dry etching, it cannot be expected that the selection ratio between the film to be etched and the film to be the stopper be as high as that obtained in wet etching. If the selection ratio between the insulating film 12 such as PSG in which the contact hole 13 is formed and the metal silicide layer 11 cannot be made sufficiently large, the surface of the metal silicide layer 11 deteriorates during formation of the contact hole, or The metal silicide layer 11 may be etched, which may not decrease the contact resistance with the metal wiring as expected. Furthermore, when the film thickness of the insulating film 12 in which the contact hole 13 is formed and the etching rate of the dry etching at the time of forming the contact hole 13 are nonuniform in the wafer surface, the deterioration state of the metal silicide layer 11 is a surface. It becomes non-uniform in the inside, which causes variation in resistance value.

In the dry etching process,
Since a damage layer due to ion implantation is formed in the metal silicide layer 11 serving as a stopper film, it is desired to remove this damage layer in order to stabilize the contact resistance. However, since the metal silicide layer 11 formed on the source / drain is extremely thin and has a thickness of only about 5 to 600 Å, the damage layer is removed from the metal silicide layer 11 and the metal silicide layer having a uniform thickness with good reproducibility. Is difficult to remain, and this problem causes an increase in the variation in contact resistance.

An object of the present invention is to eliminate these drawbacks, and a method of forming a MISFET having a metal source / drain having a small contact resistance between the source / drain and a metal wiring and a small variation in resistance value. To provide.

[0013]

The above object is to provide a method for manufacturing a semiconductor device for forming a MIS field effect transistor having a metal source / drain, after the contact hole (13) for the source / drain is opened. A step of etching away the metal silicide layer (11) exposed in the contact hole (13), and a silicon layer (1) exposed after the metal silicide layer (11) is removed.
And a step of silicidizing the surface layer of the above. As a method for removing the metal silicide layer (11) by etching, a dry etching method which is mainly carried out by contacting with a gas containing chlorine radicals is preferable.

[0014]

[Function] The metal silicide layer 11 damaged at the time of forming the contact hole 13 is etched and removed without damaging the silicon substrate 1 by bringing a gas mainly containing chlorine radicals into contact with the metal silicide layer 11. Then, a new contact hole 13 is newly formed. Since the metal silicide layer 16 is formed on the exposed silicon substrate 1, the film thickness of the metal silicide layer 16 is uniform and no damage layer is formed. Therefore, the contact resistance with the metal wiring is reduced, Variability is also reduced.

As a device for etching by mainly bringing a gas containing chlorine radicals into contact, there is a downflow plasma etching device using chlorine gas, for example. This apparatus generates chlorine plasma, removes ions in the chlorine plasma using a grid electrode, and causes only chlorine radicals to drop onto the object to be etched for etching. Since this etching method is isotropic etching and the etching rate is slow, it is not usually used in the processing step and is mainly used for removing heavy metals adhering to the wafer surface. Exposed thin metal silicide layer 11
The inventor of the present application has found out that it is an effective etching method for removing the impurities. The reason is that this method can remove the metal silicide layer 11 without damaging the silicon substrate 1 under the metal silicide layer 11, and the thin metal silicide layer 11 can be removed even by isotropic etching. This is because there is no problem in removing.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of forming a MISFET having a metal source / drain according to an embodiment of the present invention will be described below with reference to the drawings.

A refractory metal silicide layer, for example, a titanium silicide layer 11 is formed on the surface layer of the source / drain 9 by the same process as the conventional technique shown in FIGS. 2A to 2D and FIG. 3E. Then, an insulating film 12 such as PSG is formed and a contact hole 13 is formed therein.

For example, etching is performed using a down-flow plasma etching apparatus using chlorine gas,
As shown in FIG. 1A, the titanium silicide layer 11 exposed in the contact hole 13 is removed.

As shown in FIG. 1B, a refractory metal, for example, a titanium film 15 is formed to a thickness of 5 to 600 Å using a sputtering method. As shown in FIG. 1C, a titanium silicide layer is formed on the surface layer of the source / drain 9 exposed in the contact hole 13 by heating to a temperature of about 800 ° C.
16 is formed, and the non-silicided titanium film 15 is removed by etching using a mixed solution of ammonia and hydrogen peroxide solution.

As shown in FIG. 1D, an aluminum film is formed by the sputtering method, and the aluminum film is patterned to form the wiring 14.

[0021]

As described above, in the method of manufacturing a semiconductor device according to the present invention, a metal silicide having a damaged layer formed when a contact hole is etched in an insulating film formed on a source / drain. The layer is removed once without damaging the silicon substrate and a new metal silicide layer is formed there, so that the film thickness of the metal silicide layer in the region in contact with the metal wiring is uniform, and there is also a damaged layer. I don't
The contact resistance with the metal wiring is reduced, and the variation in resistance is reduced.

The source / drain junction depth of the MISFET will become thinner and thinner in the future, and the thickness of the metal silicide layer tends to be thinner accordingly. Therefore, the effect of the present invention will be further and larger in the future.

[Brief description of drawings]

FIG. 1 is a process drawing of forming a MISFET having a metal source / drain according to the present invention.

FIG. 2 is a process diagram (1) of forming a MISFET having a metal source / drain according to a conventional technique.

FIG. 3 is a process diagram (No. 2) of forming a MISFET having a metal source / drain according to a conventional technique.

[Explanation of symbols]

1 Silicon substrate 5 Gate electrode 9 Source / Drain 10, 15 Refractory metal film (titanium film) 11, 16 Metal silicide layer (titanium silicide layer) 12 Insulating film 13 Contact hole 14 metal wiring

Claims (2)

[Claims] 1. A MIS having a metal source / drain
A method of manufacturing a semiconductor device for forming a field effect transistor, the method comprising: etching a metal silicide layer (11) exposed in the contact hole (13) after opening the source / drain contact hole (13); And a step of silicidizing the surface layer of the silicon layer (1) exposed by removing the metal silicide layer (11). 2. The method of manufacturing a semiconductor device according to claim 1, wherein the method of etching away the metal silicide layer (11) is a dry etching method mainly in contact with a gas containing chlorine radicals. .