JPH05129533A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device wherein its high integration is achieved by shortening a gate length, its high speed is achieved by lowering a threshold voltage and its mass production is achieved simultaneously by forming a gate electrode composed of polysilicon of the same conductivity type without lowering the reliability of a MOS transistor. CONSTITUTION:In a PMOS region, a PMOS is constituted of the following on the surface of an N-well 4: a P-type source 16s and a P-type drain 16d; a P-type impurity layer (a threshold-voltage control layer) 10; a gate insulating film 11; and a gate electrode 12b composed of N-type polysilicon. In an NMOS region, an NMOS is constituted of the following on the surface of a P-well 5: an N-type source 15s and an N-type drain 15d; a P-type impurity layer (a threshold-voltage control layer) 9; the gate insulating film 11; and a gate electrode 12a composed of N-type polysilicon.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a combination of a bipolar transistor circuit and a CMOS in which PMOS and NMOS are complementarily connected.
The present invention relates to a semiconductor integrated circuit device suitable for so-called BiCMOS.

[0002]

2. Description of the Related Art In recent years, various studies have been conducted in order to realize higher integration, higher speed, lower power consumption and the like of semiconductor integrated circuits. MOS transistor (hereinafter M
For an integrated circuit including an abbreviated OS, high integration is achieved by shortening the channel length, that is, gate length, high speed is achieved by lowering the threshold voltage, low power consumption, and further, gate electrodes of PMOS and NMOS are provided. Research on mass production by forming the same conductivity type polysilicon is underway.

[0003]

However, high integration by shortening the gate length, high speed by lowering the threshold voltage, low power consumption, and forming the gate electrode with the same conductivity type polysilicon. It has been difficult to achieve these in mass production at the same time. The reason will be described in detail below.

18 and 19 are diagrams showing the relationship between the gate length and the threshold voltage of PMOS and NMOS, respectively.

If both the gate electrodes of the PMOS and the NMOS are formed of N-type polysilicon, the relationship between the gate length and the threshold voltage on the NMOS side is relatively easy to design as shown in FIG. Area surrounded by a frame: gate length Lg = 0.3 ± 0.05 μm, threshold voltage | Vth | =
0.4 ± 0.1 V).

On the other hand, on the PMOS side, the N-type polysilicon and the N well are opposed to each other with the gate insulating film interposed therebetween (see FIG. 20), and the work function difference between the two becomes small. As a result, as shown by the dotted line in FIG. 18, the threshold voltage with respect to the gate length deviates from the designed range, and it is difficult to match the threshold voltages of the PMOS and NMOS.

Therefore, as a means for making the threshold voltages of the PMOS and the NMOS match, as shown in FIG.
A buried channel structure has been proposed in which a P-type impurity layer 10 having a conductivity type opposite to that of the N well is formed by ion implantation as a threshold voltage control layer in the OS channel region. If the buried channel structure is applied, the work function difference becomes large, so that the threshold voltage of the PMOS is entirely lowered and the impurity concentration of the P-type impurity layer 10 is appropriately adjusted as shown by the chain line in FIG. By setting it, it becomes possible to match the threshold voltages of the PMOS and the NMOS.

However, when the buried channel structure is applied, the threshold voltage shifts to a lower level as it is in a portion having a long gate length (> 0.6 μm), but the threshold voltage rapidly increases in a portion having a short gate length. It falls (hereinafter referred to as the short channel effect) and falls below the design range.

This is because in the buried channel structure, the channel structure under the gate insulating film is P ⁺ (source) -P (impurity layer 10) -P ⁺ (drain), which is compared with the case where the buried channel structure is not applied. As a result, the potential barrier against carriers between the source and the drain is lowered, so that the phenomenon of majority carrier spillage (sole,
This is because a phenomenon in which majority carriers diffuse from the drain) occurs.

As described above, it has been difficult to realize a PMOS having a short channel length and a low threshold voltage. Therefore, in an integrated circuit including a MOS transistor, high integration by shortening the gate length is achieved. Becoming
Higher speed by lowering the threshold voltage, lower power consumption,
It was difficult to achieve mass production by forming the gate electrode with the same conductivity type polysilicon at the same time.

On the other hand, recently, a bipolar transistor such as an NPN transistor (hereinafter simply referred to as NPN) or a PNP transistor (hereinafter simply referred to as PNP) is combined with a CMOS circuit in which a PMOS and an NMOS are connected in a complementary manner. Also, so-called BiCMOS circuits have been studied. And the problem mentioned above is this BiCMO
It was particularly remarkable in the S circuit. The reason will be described in detail below.

Regarding the BiCMOS, for example, the structure shown in FIG. 21 is the technical digest of 1986 IDM in 1986, pages 408 to 411 (1986 IE).
DM, TECHNICAL DIGEST, PP408-411).

In the figure, in the NPN region, a high-concentration N ⁺ type buried layer 2a and a shallow N well 4a are stacked on the P type substrate 1, the N well 4a is the collector, the P layer 17 is the base, and the N layer is the N layer. An NPN having 19 as an emitter is formed.

In the PMOS region, a high concentration N ⁺ type buried layer 2b and a shallow N well 4b are stacked on the P type substrate 1,
A PMOS is formed in which the surface of the well 4b serves as a channel and the P ⁺ layer 16 serves as a source / drain.

In the NMOS region, the P-type buried layer 3 and the shallow P-well 5 are formed on the P-type substrate 1, the surface of the P-well 5 is a channel, and the N ⁺ layer 15 is a source / drain NM.
OS is formed.

22 (a) and 22 (b) are diagrams showing the impurity concentration distribution in the depth direction of the well from the channel surface of the PMOS / NMOS to immediately before the substrate. In particular, the solid line is shown in FIG. The distribution of the BiCMOS device in the MOS region as described above is shown, and the alternate long and short dash line represents a device that is composed of only MOS and does not include a bipolar transistor (hereinafter, referred to as CMO
(Expressed as S).

In the CMOS, as shown in FIG. 20, since the well is formed on the substrate and the element is formed on the surface of the well, the well concentration in the PMOS region is constant regardless of the depth.

On the other hand, in the BiCMOS, in order to realize a high-speed bipolar operation, as shown in FIG. 21, there is a high concentration of N between the N well (4b) and the substrate (1).
^{The +} buried layer (2b) is formed, and the N well (4b) and the N ⁺ buried layer (2b) function as actual wells.

Therefore, in the PMOS region of BiCMOS, if the heat treatment is applied after the well is formed, the impurities in the buried layer 2b are exposed into the N well 4b, so that the heat treatment cannot be sufficiently performed, and the PMOS region and the NMOS region are not formed. The well concentration from the channel portion (X1, Y1) to the substrate (X2, Y2) immediately before the substrate shows a distribution having a slope as shown in the figure, and the impurity concentration near the surface of the NMOS and PMOS regions of BiCMOS is NMOS and P
It was higher than that of the MOS region.

As a result, the threshold voltage of the PMOS of BiCMOS tends to be higher than the threshold voltage of the PMOS of CMOS, so that the PMO of BiCMOS is increased.
It was more difficult to match the threshold voltage of S and NMOS.

As one means for lowering the threshold voltage of PMOS, there is thinning of the gate insulating film. For example, 199
Year 0 IE DM Technical Digest page 493 to page 496 (1990, IEDM, TECHNICAL
In the conventional example described in DIGEST, PP493-496), the gate oxide film is a thin film of 3.5 nm, and the source / drain junction depth is made shallow so that the gate length is 0.25 μm.
The following fine CMOS is realized.

However, the thickness of the gate oxide film is 3.5n.
If it is set to about m, the voltage applied to the gate is limited to about 2 V from the viewpoint of reliability of the MOS transistor.
There is a problem that the use range is limited and the operation speed is reduced.

In addition, the embedded channel is applied to the PMO.
When the threshold voltage of S is lowered, the impurity concentration near the surface of the PMOS region in BiCMOS becomes higher than that in the PMOS region of CMOS, so that the impurity concentration of the buried channel (impurity layer 10; see FIG. 20) is increased. Must be higher. As a result, the threshold voltage drop becomes steeper in the region where the gate length is short (<0.6 μm), and PM is suppressed while suppressing the short channel effect.
There is a problem that it becomes more difficult to match the threshold voltages of the OS and the NMOS.

The object of the present invention is to solve the above-mentioned problems of the prior art and to achieve high integration by shortening the gate length without lowering the reliability of the MOS transistor.
It is an object of the present invention to provide a semiconductor integrated circuit device that simultaneously achieves high speed by lowering a threshold voltage and mass production by forming a gate electrode of the same conductivity type polysilicon.

More specifically, a semiconductor integrated circuit device having a BiCMOS structure including a fine CMOS having an absolute value of a threshold voltage of 0.5 V or less, a driving voltage of about 3.3 V and a gate length of 0.5 μm or less. To provide.

[0026]

In order to achieve the above object, the present invention has a channel having a source region and a drain region made of a first conductivity type semiconductor and a gate electrode made of a second conductivity type semiconductor. A first MOS transistor having a first conductivity type semiconductor threshold voltage control layer in a portion thereof, a source region and a drain region made of a second conductivity type semiconductor, and a second MOS having a gate electrode made of a second conductivity type semiconductor. In a semiconductor integrated circuit device having a transistor on the same substrate, a part of a channel region of a first MOS transistor is exposed on a channel surface, and at least one of a source region, a threshold voltage control layer, and a drain region is formed. It is characterized in that a second conductivity type semiconductor region which forms a junction with the contact is provided.

[0027]

According to the above structure, the junction formed in the channel portion under the gate oxide film acts as a potential barrier for carriers (suppresses the phenomenon of majority carrier spill).
Therefore, lowering of the threshold value of the first MOS transistor is suppressed, and high integration is achieved by shortening the gate length.
Higher speed by lowering the threshold voltage and mass production by forming the gate electrode with the same conductivity type polysilicon can be achieved at the same time.

[0028]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a BiCM which is an embodiment of the present invention.
FIG. 2 is a sectional view of the OS element, FIG. 2 is an enlarged sectional view of the PMOS region of FIG. 1, and FIG. 3 is a diagram showing an impurity concentration distribution of the PMOS region in the channel direction Z1-Z2. It represents a part.

An N ⁺ buried layer 2 is formed in the NPN region and the PMOS region of the P substrate 1, and a P buried layer 3 is formed in the NMOS region. N well 4 on N ⁺ buried layer 2
And a P well 5 is formed on the P buried layer 3.

A P-type base layer 17, a P-type external base layer 18, and an N-type emitter layer 19 are formed in the NPN region on the surface of the N well 4 which is partitioned by the field oxide film 7, and the N well 4 is collected. And an NPN bipolar transistor is constructed.

In the PMOS region, P type source / drains 16s and 16d, a P type impurity layer (threshold voltage control layer) 10, a gate insulating film 11 and a gate electrode 12 made of N type polysilicon are formed on the surface of the N well 4. In the NMOS region, the N-type source / drain 15s, 15d, the P-type impurity layer 9, the gate insulating film 11, and the gate electrode 12 made of N-type polysilicon form the NMOS in the NMOS region. There is.

N-type source / drain layers 15s, 15d,
An electrode 21 is connected to the exposed surface of the P-type source / drain layers 16s and 16d, the P-type external base layer 18, the N-type emitter layer 19 and the N ⁺ pull-up layer 8 at the opening of the oxide film 20.

Also in this embodiment, a high performance bipolar transistor is used.
High concentration N to realize the transistor ⁺Mold embedding layer 2
The PMOS well has a shallow N
L4 and N⁺It has a layered structure with the type buried layer 2 and is an NMOS.
Is a shallow p-well 5 and p-type buried layer 3 having a laminated structure
Has become. As a result, the explanation with reference to FIG.
The shallow N well 4 and P well 5 are
It is an inclined type with a high concentration of pure substances.

However, in this embodiment, N-type semiconductor regions 13s and 13d for forming a junction with the P-type source / drain layers 16s and 16d and the P-type impurity layer 10 are formed in the channel portion under the gate oxide film 11 of the PMOS. Has been done.

Since this junction acts as a potential barrier for carriers moving from the source side to the drain side,
The phenomenon of majority carrier spillage is suppressed, and as shown by the solid line in FIG. 18, even if the gate oxide film is thick, a sharp drop in the threshold voltage at a short gate length is suppressed.

Since the N-type region 13 is provided,
Since the impurity concentration of the P-type impurity layer 10 for controlling the threshold voltage can be freely increased, it can be matched with the threshold voltage of the NMOS.

As a result, according to the present embodiment, the voltage 3.3.
Even with V, a fine CMO in which the conductivity types of the gate electrodes of the NMOS and PMOS are the same and the absolute value of the threshold voltage is 0.5 V or less.
BiCMO in which S and bipolar transistors coexist
An S structure can be provided.

In FIG. 2, symbols a and b are the width and depth of the N-type region 13, respectively. Since the threshold voltage increases as the width a and the depth b increase, it is desirable that the width a and the depth b be narrow and shallow within a range in which the short channel effect can be suppressed. Further, the impurity concentration distribution in the channel direction Z1 -Z2 is P ⁺ -N-P-N-P ⁺ , as shown in FIG. Regarding the impurity concentration of the N-type region 13, the higher the concentration is, the more the short channel effect is improved, but the threshold voltage also becomes higher. Therefore, it is desirable to set the impurity concentration to a little higher than that of the P-type impurity layer 10.

4 to 6 are sectional views showing the manufacturing method of this embodiment. (a) A P-type buried layer 3 is formed in the NMOS region and a high-concentration N ⁺ -type buried layer 2 is formed in the PMOS region and the NPN region of the main surface of the P-type silicon substrate 1 having a specific resistance of about 10 Ωcm. .. (b) After the N-type epitaxial layer is formed on the P substrate 1 by the existing epitaxial technique, the N well 4 and P having the impurity concentration of about 10 ¹⁷ cm ³ are formed by the ion implantation technique.
Wells 5 are formed on the N ⁺ type buried layer 2 and the P type buried layer 3, respectively. (c) In order to electrically separate individual devices, a field oxide film 7 of 300 to 500 n is formed by a known selective oxidation method.
It is formed with a film thickness of m. At this time, N-channel parasitic MOS
In order to prevent the above operation, the high concentration P-type region 6 is formed.
Next, the N-type pull-up layer 8 connected to the N ⁺ buried layer 2 of NPN is formed by using the photolithography technique and the ion implantation technique.

Then, by a well-known photolithography technique, about 10 ¹¹ to 10 ¹³ cm ^{2 of} boron, which is a P-type impurity, is implanted into the surface of the P well 5 in the NMOS region, and NM is implanted.
A P-type impurity layer 9 for controlling the threshold voltage of OS is formed.

Similarly, boron is implanted into the surface of the N well 4 in the PMOS region to about 10 ¹¹ to 10 ¹³ cm ² to form the P-type impurity layer 10 for controlling the threshold voltage of the PMOS.

In this embodiment, since it is not necessary to make the N well 4 have a high concentration, the P-type impurity layer 9 and the P-type impurity layer 10 can be shared. (d) A gate oxide film 11 having a film thickness of about 9 nm is formed on the surfaces of the N well 4 and the P well 5, and a polycrystalline silicon film 12 containing phosphorus is deposited thereon with a film thickness of 50 to 200 nm. To do. (e) A polycrystalline silicon film 1 having a desired gate size is formed by using photolithography technology and conventional dry etching technology.
2 is processed to obtain gate electrodes 12a and 12b. (f) By photolithography technology, N
-Type impurities such as phosphorus or helium are shallowly implanted to the substrate surface by an ion implantation technique to a depth of about 10 ¹² to 10 ¹⁴ cm ² and N
The mold regions 13s and 13d are formed. The PMOS is L
In the case of the DD structure, it is desirable to form the N-type regions 13s and 13d by the oblique ion implantation technique. (g) Using photolithography, phosphorus is implanted into the NMOS region by ion implantation to about 10 ¹³ to 10 ¹⁴ cm ² to form the N-type region 14. The N-type region 14 weakens the electric field in the vicinity of the drain and reduces the generation of hot carriers.

Next, the existing CMOS process technology is advanced to N ⁺ type source 15s, N ⁺ type drain 15d, P ⁺
A type source 16s, a P ⁺ type drain 16d, a P ⁺ external base 18 and a P base region 17 are formed. (h) with an insulating film 23 for forming the NPN emitter is provided to open the emitter section, after depositing a polycrystalline silicon film, 10 ¹⁵ arsenic using an ion implantation technique to 10 ¹⁶ cm ²
Inject a certain amount and heat-treat to make it N ⁺ type. At this time, N
^{The +} emitter region 19 is also formed at the same time. Next, the polycrystalline silicon film is processed to obtain the emitter electrode 38.

Next, an interlayer insulating film 20 having a thickness of 300 to 1000 nm is provided, the resist in the portion to be contacted with the metal wiring is opened by the photolithography technique, and the interlayer insulating film 20 is opened by the dry etching technique. Finally, a metal wiring film is evaporated to a thickness of about 500 to 1500 nm, a resist is left where the metal wiring film is to be left by a photolithography technique, and the metal wiring film is processed by a dry etching technique to obtain a metal electrode 21 [FIG. 1].

In the above embodiment, the N-type region 13 is used.
Although it has been described that s and 13d are formed to a position deeper than the P-type impurity layer 10, as shown in FIG.
The N-type regions 13s and 13d may be formed in the P-type impurity layer 10 so that the P ⁺ -type source 16s, the drain 16d and a part of the P-type impurity layer 10 are directly connected.

FIG. 7 is a BiCM whose sectional structure is shown in FIG.
It is a circuit diagram of an example which applied an OS device to a 2NAND BiCMOS gate circuit. This gate circuit is C
It can operate at high speed when the load applied to the gate circuit is larger than that of the MOS gate circuit.

FIG. 8 shows a schematic plan view of the gate circuit shown in FIG. In this embodiment, NMOS and PMOS
Since the gate electrodes 12 can have the same conductivity type and the same gate length, the layout of the gate circuit can be increased by arranging the NMOS, the PMOS, and the NPN as illustrated.

9 to 13 show P to which the present invention is applied.
It is a cross-sectional structure of another embodiment of the MOS, and the same symbols as those used above represent the same or equivalent portions.

In the embodiment shown in FIGS. 9 and 10, the structure in the channel direction is P ⁺ (16s) -N (13) from the source side.
It becomes -P (10) -P ⁺ (16d). Source/
Since the drains 16s and 16d are asymmetrical, it is difficult to apply it to a gate circuit or the like, but the drain current is larger than that of the embodiment shown in FIG. 1 and the action of suppressing the short channel effect remains the same. It should be noted that the same effects as the above can be achieved by the embodiments shown in FIGS. 11 to 13.

In each of the above embodiments, the case where the gate electrode is the N ⁺ type has been described. However, when the gate electrode is the P ⁺ type, the NMOS is the buried channel type and the PMOS is the PMOS.
Similarly to the above, an N-type impurity layer may be provided in the channel region of the NMOS.

In the above-mentioned embodiment, the BiCMOS is explained, but the present invention is not limited to this.
Even when applied to a CMOS device in which only OS transistors are formed, the same effect can be achieved.

FIG. 14 shows a B with PNP and NPN.
FIG. 15 is a sectional view of an iCMOS, showing an example of a gate circuit to which this device structure is applied, and the same reference numerals as those used above denote the same or equivalent portions.

According to this embodiment, since the short channel effect is suppressed in the same manner as described above, it is possible to operate at a high speed at an applied voltage of around 3.3V.

FIG. 16 is a diagram showing the configuration of a microprocessor to which the present invention is applied.

As is well known, the microprocessor has a C cache memory 401 for receiving instructions and a decoder section 40.
4. The data structure macrocell (DS which executes and outputs arithmetic processing based on the output signal of the decoder section
Macro cell) 405, D cache memory 402 for storing the operation result, and cache memory 401 for the next instruction after the operation.
Code translation lookaside buffer (C-TL) that specifies the address to read from
B) 403b, which is composed of a D-TLB 403a for converting the logical address of the operation result into the physical address of the D cache and designating the data storage address.

In a recent microprocessor, CMOS or Bi is used for a portion other than a memory cell that executes an operation.
Since the CMOS logic gate circuit is used, the BiCMOS using the device structure of the present invention in the corresponding portion.
A high-speed processor can be realized by applying a logic gate circuit or the like.

FIG. 17 is a block diagram of an embodiment of an SRAM to which a logic gate circuit using the device structure of the present invention is applied.

The SRAM has an input pad 901 for inputting an address signal and an input buffer 9 for receiving the address signal.
02, a decoder unit 903 that selects an address based on a signal from an input buffer, a memory cell 904 that holds information with a unique address, a sense amplifier 905 that amplifies information in the memory cell, and a sense amplifier 905. It is composed of an output buffer 906 that outputs an output signal to a circuit in the subsequent stage, and a signal output pad 907.

If the logic gate circuit using the device structure of the present invention is applied to the input buffer 902 and the decoder circuit 903, the SRAM operates at high speed even if the power supply voltage is lowered.
Can be realized.

In the above description, the present invention is applied to the SRAM.
However, the same effect can be obtained by applying it to a DRAM or a ROM.

[0062]

According to the present invention, a buried channel type MOS is provided.
By providing the junction in the channel portion under the gate oxide film of, the short channel effect is suppressed, and as a result, the following effects are achieved. (1) Since the gate electrodes of the NMOS and the PMOS can have the same conductivity type and can have a short gate length, a semiconductor integrated circuit device which can be easily mass-produced and has a high degree of integration can be obtained. (2) Since the short channel effect is suppressed even if the gate oxide film is thickened, a highly reliable semiconductor integrated circuit device can be obtained. (3) Set the absolute value of the threshold voltage of the buried channel MOS to 0.
Since the voltage can be set to 5 V or less and the threshold voltage can be matched with that of the surface channel MOS, the circuit design can be facilitated and the drain current of the buried channel MOS can be increased to obtain a faster semiconductor integrated circuit device.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a BiCMOS device that is an embodiment of the present invention.

FIG. 2 is a partially enlarged sectional view of FIG.

FIG. 3 is a diagram showing a relationship between a well depth and an impurity concentration.

FIG. 4 is a cross-sectional view showing the manufacturing method of FIG.

5 is a cross-sectional view showing the manufacturing method of FIG.

6 is a cross-sectional view showing the manufacturing method of FIG.

FIG. 7 is a circuit diagram of a 2NAND circuit to which the present invention is applied.

FIG. 8 is a plan view of a 2NAND circuit to which the present invention is applied.

FIG. 9 is a sectional view of a PMOS which is another embodiment of the present invention.

FIG. 10 is a sectional view of a PMOS which is another embodiment of the present invention.

FIG. 11 is a sectional view of a PMOS which is another embodiment of the present invention.

FIG. 12 is a cross-sectional view of a PMOS which is another embodiment of the present invention.

FIG. 13 is a sectional view of a PMOS which is another embodiment of the present invention.

FIG. 14 is a sectional view of a BiCMOS according to another embodiment of the present invention.

15 is a circuit diagram of the BiCMOS shown in FIG.

FIG. 16 is a configuration diagram of a microprocessor to which the present invention is applied.

FIG. 17 is a plan view of an SRAM to which the present invention has been applied.

FIG. 18 is a diagram showing the relationship between the MOS gate length and the threshold voltage.

FIG. 19 is a diagram showing the relationship between the MOS gate length and the threshold voltage.

FIG. 20 is a diagram showing an impurity concentration distribution of a conventional MOS.

FIG. 21 is a cross-sectional view of a conventional BiCMOS device.

FIG. 22 is a diagram showing an impurity concentration distribution of a conventional MOS.

FIG. 23 is a sectional view of a PMOS which is another embodiment of the present invention.

[Explanation of symbols]

1 ... Silicon substrate, 2 ... N ⁺ type buried layer, 3 ... P type buried layer, 4 ... N well, 5 ... P well, 7 ... Field oxide film, 8 ... Pull-up layer, 9, 10 ... P type impurity Layer (threshold voltage control layer), 11 ... Gate oxide film, 12 ... Gate electrode, 1
3 ... N-type region, 14 ... N ^- region, 15 ... N ⁺ source / drain region, 16 ... P ⁺ source / drain region, 17 ...
P-type base region, 18 ... P-type external base region, 19 ... N
⁺ Type emitter region, 20 ... Interlayer insulating film, 21 ... Electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takahiro Nagano 4026 Kuji Town, Hitachi City, Hitachi, Ibaraki Prefecture Hitachi Research Laboratory, Nitate Manufacturing Co., Ltd.

Claims (4)

[Claims] 1. A first region having a source region and a drain region made of a first conductivity type semiconductor, and a gate electrode made of a second conductivity type semiconductor, and a first conductivity type semiconductor threshold voltage control layer in a channel portion. A semiconductor integrated circuit device having a MOS transistor, a source region and a drain region made of a second conductivity type semiconductor, and a second MOS transistor having a gate electrode made of a second conductivity type semiconductor on the same substrate. A part of the channel region of the MOS transistor is exposed at the channel surface, and forms a junction that acts as a potential barrier against carriers together with at least one of the source region, the threshold voltage control layer, and the drain region. A semiconductor integrated circuit device comprising a second conductivity type semiconductor region. 2. The semiconductor integrated circuit device according to claim 1, wherein a first conductivity type semiconductor threshold voltage control layer is formed in a channel portion of the second MOS transistor. 3. The semiconductor integrated circuit according to claim 1, wherein the impurity concentration of the second conductivity type semiconductor region is higher than the impurity concentration of the first conductivity type semiconductor threshold voltage control layer. apparatus. 4. The semiconductor integrated circuit device according to claim 1, wherein the bipolar transistors are formed on the same substrate.