JPH05129499A - Mounting structure for electronic component - Google Patents
Mounting structure for electronic componentInfo
- Publication number
- JPH05129499A JPH05129499A JP3319894A JP31989491A JPH05129499A JP H05129499 A JPH05129499 A JP H05129499A JP 3319894 A JP3319894 A JP 3319894A JP 31989491 A JP31989491 A JP 31989491A JP H05129499 A JPH05129499 A JP H05129499A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- electronic component
- substrate
- mounting structure
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子部品の実装構造に
係り、特にキャリアテープ上に形成された複数本のリー
ド（以下ＴＣＰリードと称する）を介してＩＣチップと
基板とを接続する電子部品の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure for electronic parts, and more particularly to an electronic device for connecting an IC chip and a substrate through a plurality of leads (hereinafter referred to as TCP leads) formed on a carrier tape. The mounting structure of parts.
【０００２】[0002]
【従来の技術】電子機器の高機能化、高性能化などに伴
い、集積回路（ＩＣ）の大規模化が進み、１パッケージ
当りの消費電力が増加している。このため何等かの放熱
手段を設けないと、ＩＣの性能、機能を維持できなくな
るばかりかＩＣの破壊を招く恐れもある。特に小型化と
同時に低消費電力化が要求される携帯パソコンやデジタ
ルＶＴＲなどのポータブル機器においては、ファンモー
タなどの強制放熱手段を設けることは好ましくない。2. Description of the Related Art As electronic devices have become more sophisticated and have higher performance, the scale of integrated circuits (ICs) has increased, and the power consumption per package has increased. For this reason, unless some kind of heat dissipation means is provided, not only the performance and function of the IC cannot be maintained but also the IC may be destroyed. In particular, in portable devices such as portable personal computers and digital VTRs, which are required to be compact and low in power consumption at the same time, it is not preferable to provide a forced heat dissipation means such as a fan motor.
【０００３】強制放熱手段を用いない場合には、伝導放
熱が最も有効な手段となり、ＩＣからの発熱を実装基板
を介して外装部品などの外気に触れる部分に伝え、外部
に逃すことができる。このような放熱を考慮した従来の
ＩＣ実装構造の例を図２乃至図５に示す。When the forced heat radiating means is not used, conduction heat radiation is the most effective means, and the heat generated from the IC can be transmitted to a portion such as an exterior component exposed to the outside air through the mounting substrate and escaped to the outside. 2 to 5 show examples of the conventional IC mounting structure in consideration of such heat dissipation.
【０００４】図２に示すものは一般的な樹脂モールド型
ＩＣの実装例である。図２において、ＩＣチップ１の各
ピン２はボンディングワイヤ３を介して金属リードフレ
ーム４の一端に接続されており、リードフレーム４の他
端は基板５に形成された配線用銅パターン６に接続され
ている。またＩＣチップ１、ボンディングワイヤ３及び
リードフレーム４のボンディングワイヤ３が接続された
側の端部は、樹脂７によって一体にモールドされてい
る。そしてモールド樹脂７の底面は基板５に形成された
放熱用銅パターン８に接している。FIG. 2 shows an example of mounting a general resin mold type IC. In FIG. 2, each pin 2 of the IC chip 1 is connected to one end of a metal lead frame 4 via a bonding wire 3, and the other end of the lead frame 4 is connected to a wiring copper pattern 6 formed on a substrate 5. Has been done. Further, the ends of the IC chip 1, the bonding wires 3 and the lead frame 4 on the side to which the bonding wires 3 are connected are integrally molded with resin 7. The bottom surface of the mold resin 7 is in contact with the heat radiation copper pattern 8 formed on the substrate 5.
【０００５】上記の構成のＩＣチップ実装構造において
は、ＩＣチップ１から発生した熱はボンディングワイヤ
３、リードフレーム４及び配線用銅パターン６を介して
基板５に流れ、空気中に放熱される。同時にモールド樹
脂７及び放熱用銅パターン８を介して基板５に流れ空気
中に放熱される。In the IC chip mounting structure having the above structure, the heat generated from the IC chip 1 flows to the substrate 5 through the bonding wire 3, the lead frame 4 and the wiring copper pattern 6 and is radiated into the air. At the same time, it flows to the substrate 5 through the mold resin 7 and the heat radiation copper pattern 8 and is radiated into the air.
【０００６】図３に示すものは放熱板内蔵型樹脂モール
ドＩＣの実装例である。この実装例は図２に示すモール
ド樹脂７のＩＣチップ１と放熱用銅パターン８との間
に、熱伝導率のよい材料で構成された放熱板１１を設け
たものである。放熱板１１の上面はＩＣチップ１の下面
に当接し、放熱板１１の下面はモールド樹脂７の底面か
ら露出して放熱用銅パターン８に当接している。この構
成のＩＣ実装構造によると、ＩＣチップ１と基板５の表
面との間の熱抵抗を大幅に改善することができる。FIG. 3 shows a mounting example of a resin mold IC with a built-in heat sink. In this mounting example, a heat radiating plate 11 made of a material having a high thermal conductivity is provided between the IC chip 1 of the mold resin 7 and the heat radiating copper pattern 8 shown in FIG. The upper surface of the heat dissipation plate 11 is in contact with the lower surface of the IC chip 1, and the lower surface of the heat dissipation plate 11 is exposed from the bottom surface of the mold resin 7 and is in contact with the heat dissipation copper pattern 8. According to the IC mounting structure having this configuration, the thermal resistance between the IC chip 1 and the surface of the substrate 5 can be significantly improved.
【０００７】図４はＴＡＢ実装と称するＩＣの実装例で
ある。ＴＡＢ実装法は多極のＩＣまたは放熱量の大きい
ＩＣの高密度実装法として有効な手段であり、図５に示
すように４方向にそれぞれ複数本の銅箔などのＴＣＰリ
ード２１が形成されたキャリアテープ２２によって、Ｉ
Ｃチップと基板とが接続される。キャリアテープ２２の
中心にはＩＣチップが装着される角孔２２ａ内にＴＣＰ
リード２１のインナリード２１ａが突出している。また
キャリアテープ２２の角孔２２ａの４方向の外側には、
それぞれ長孔２２ｂが形成されており、ＴＣＰリード２
１のアウタリード２１ｂは長孔２２ｂの外側に延設され
ている。そしてアウタリード２１ｂの外側の端部にはそ
れぞれテストパッド２３が設けられている。FIG. 4 shows an example of mounting an IC called TAB mounting. The TAB mounting method is an effective means as a high-density mounting method for a multi-pole IC or an IC with a large heat radiation amount, and as shown in FIG. 5, TCP leads 21 such as a plurality of copper foils are formed in each of four directions. With the carrier tape 22, I
The C chip and the substrate are connected. At the center of the carrier tape 22, a TCP is placed in a square hole 22a in which an IC chip is mounted.
The inner lead 21a of the lead 21 projects. Further, on the outer side in four directions of the square hole 22a of the carrier tape 22,
Long holes 22b are formed in each of the TCP leads 2
The first outer lead 21b extends outside the elongated hole 22b. A test pad 23 is provided on the outer end of each outer lead 21b.
【０００８】上記のキャリアテープ２２の中央の角孔２
２ａ内にＩＣチップ１を装着し、ＩＣチップ１の各ピン
とインナリード２１ａの内側の一端とをそれぞれ接続す
る。次にテストパッド２３によりＩＣチップ１及びその
接続状態を検査したのち、長孔２２ｂの外側のキャリア
テープ２２を切り捨てる。。その後図４に示すようにア
ウタリード２１ｂの外側の一端をそれぞれ基板５に形成
された配線用銅パターン６に接続する。次にインナリー
ド２１ａとＩＣチップとの接続部をインナコート樹脂２
４により被覆する。なおインナコート樹脂２４は図４に
示すようにＩＣチップ１の上面を前面被覆してもよく、
接続部のみを被覆してもよい。The central square hole 2 of the carrier tape 22 described above.
The IC chip 1 is mounted in 2a, and each pin of the IC chip 1 is connected to one end of the inner lead 21a. Next, after inspecting the IC chip 1 and its connection state with the test pad 23, the carrier tape 22 outside the elongated hole 22b is cut off. . Thereafter, as shown in FIG. 4, the outer ends of the outer leads 21b are connected to the wiring copper patterns 6 formed on the substrate 5, respectively. Next, the connecting portion between the inner lead 21a and the IC chip is connected to the inner coat resin 2
4. The inner coat resin 24 may cover the upper surface of the IC chip 1 from the front, as shown in FIG.
You may coat only a connection part.
【０００９】上記のＴＡＢ実装法によると、ＩＣチップ
１から発生した熱はＴＣＰリード２１及び配線用銅パタ
ーン６を介して基板５に流れ、空気中に放熱される。According to the above-mentioned TAB mounting method, the heat generated from the IC chip 1 flows to the substrate 5 through the TCP leads 21 and the wiring copper pattern 6 and is radiated into the air.
【００１０】[0010]
【発明が解決しようとする課題】上記のように構成され
た従来の電子部品実装構造のうち、図２に示す実装例に
よると、ＩＣチップ１と放熱用銅パターン８との間に介
在するモールド樹脂７の厚さは通常１ｍｍ前後あり、樹
脂の熱伝導が悪いため、基板５への伝導放熱はほとんど
行なわれない。また構造上、実装上も小型化に限界があ
る。Among the conventional electronic component mounting structures configured as described above, according to the mounting example shown in FIG. 2, a mold interposed between the IC chip 1 and the heat radiation copper pattern 8 is provided. The thickness of the resin 7 is usually about 1 mm, and the heat conduction of the resin is poor, so that conduction and heat dissipation to the substrate 5 is hardly performed. Further, there is a limit to miniaturization in terms of structure and mounting.
【００１１】また図３に示す実装例によると、ＩＣチッ
プ１と放熱用銅パターン８との間に放熱板１１を設ける
ため、小型化に限界があり高密度実装に適さず、しかも
コスト高になる。Further, according to the mounting example shown in FIG. 3, since the heat dissipation plate 11 is provided between the IC chip 1 and the heat dissipation copper pattern 8, there is a limit to miniaturization, which is not suitable for high-density mounting, and the cost is high. Become.
【００１２】さらに図４に示す実装例によると、ＩＣチ
ップ１の下面と基板５とは直接接触しておらず、その間
に熱伝導率の悪い空気層が存在する。このためＩＣチッ
プ１から基板５への放熱は銅箔のＴＣＰリード２１を介
してわずかに行なわれるだけである。Further, according to the mounting example shown in FIG. 4, the lower surface of the IC chip 1 and the substrate 5 are not in direct contact with each other, and an air layer having poor thermal conductivity exists between them. Therefore, the heat radiation from the IC chip 1 to the substrate 5 is slightly performed via the TCP lead 21 of the copper foil.
【００１３】上述したように従来の電子部品の各実装例
にはそれぞれ問題があった。As described above, each mounting example of the conventional electronic component has a problem.
【００１４】本発明は、このような状況に鑑みてなされ
たもので、薄型高密度実装が可能で高放熱性を有する電
子部品の実装構造を提供することを目的とする。The present invention has been made in view of such a situation, and an object thereof is to provide a mounting structure of an electronic component which enables thin and high-density mounting and has high heat dissipation.
【００１５】[0015]
【課題を解決するための手段】請求項１に記載の電子部
品の実装構造は、キャリアテープ２２上に形成された複
数本のリードとしてのＴＣＰリード２１の一端をそれぞ
れ電子部品としてのＩＣチップ１のピン２に接続し、他
端をそれぞれ基板５上に形成された配線パターンとして
の配線用銅パターン６に接続する電子部品の実装構造に
おいて、ＩＣチップ１と基板５との間に放熱材３２また
は３３を充填したことを特徴とする。According to a mounting structure of an electronic component according to claim 1, one end of each of TCP leads 21 as a plurality of leads formed on a carrier tape 22 has an IC chip 1 as an electronic component. In the mounting structure of the electronic component, which is connected to the pin 2 and the other end is connected to the wiring copper pattern 6 as the wiring pattern formed on the substrate 5, respectively, between the IC chip 1 and the substrate 5. Or 33 is filled.
【００１６】請求項２に記載の電子部品の実装構造は、
放熱材が電気絶縁性を有する熱伝導性接着材３２である
ことを特徴とする。The mounting structure of the electronic component according to claim 2 is
The heat radiation material is a heat conductive adhesive material 32 having electrical insulation.
【００１７】請求項３に記載の電子部品の実装構造は、
放熱材が導電性ペースト３３であることを特徴とする。The mounting structure of the electronic component according to claim 3 is
The heat dissipation material is a conductive paste 33.
【００１８】[0018]
【作用】請求項１に記載の電子部品の実装構造において
は、ＩＣチップ１と基板５との間に放熱材を充填したの
で、空気層よりはるかに大きい熱伝導率を有する放熱材
を介して、ＩＣチップ１から発生する熱を基板５に積極
的に伝導を行なうことができる。In the electronic component mounting structure according to the first aspect, since the heat radiation material is filled between the IC chip 1 and the substrate 5, the heat radiation material having a thermal conductivity far higher than that of the air layer is interposed. The heat generated from the IC chip 1 can be positively conducted to the substrate 5.
【００１９】請求項２に記載の電子部品の実装構造にお
いては、ＩＣチップ１と基板５との間に電気抵抗値の大
きい熱伝導性接着材３２を充填することにより、ＩＣチ
ップ１と基板５との間を電気的に絶縁することができ
る。In the electronic component mounting structure according to the second aspect, the IC chip 1 and the substrate 5 are filled with the thermally conductive adhesive 32 having a large electric resistance value between the IC chip 1 and the substrate 5. It is possible to electrically insulate between and.
【００２０】請求項３に記載の電子部品の実装構造にお
いては、ＩＣチップ１と基板５との間に導電性ペースト
３３を充填することにより、ＩＣチップ１と基板５との
間の電気的導通を図ることができる。In the electronic component mounting structure according to the third aspect of the present invention, by filling the conductive paste 33 between the IC chip 1 and the substrate 5, electrical conduction between the IC chip 1 and the substrate 5 is achieved. Can be planned.
【００２１】[0021]
【実施例】以下、本発明の電子部品の実装構造の一実施
例を図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an electronic component mounting structure of the present invention will be described below with reference to the drawings.
【００２２】図１に本発明の一実施例の構成を示す。図
１において、図４に示す従来例の部分と対応する部分に
は同一の符号を付してあり、その説明は適宜省略する。
本実施例の特徴は基板５の表面でＩＣチップ１に対向す
る部分に放熱用銅パターン３１を設け、ＩＣチップ１の
下面と放熱用銅パターン３１との間に熱伝導性接着材３
２を充填した点にある。接着材３２としては熱伝導性エ
ポキシ樹脂などが用いられる。FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, portions corresponding to those of the conventional example shown in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted as appropriate.
The feature of this embodiment is that a heat-dissipating copper pattern 31 is provided on the surface of the substrate 5 facing the IC chip 1, and the heat-conductive adhesive 3 is provided between the lower surface of the IC chip 1 and the heat-dissipating copper pattern 31.
2 is the point filled. As the adhesive material 32, a heat conductive epoxy resin or the like is used.
【００２３】本実施例によれば、熱伝導性エポキシ樹脂
の熱伝導率が約１．４２Ｗ／ｍ・ｋであり、空気の熱伝
導率約０．２６Ｗ／ｍ・ｋに比べてはるかに大きい。こ
のためＩＣチップ１が発生する熱を熱伝導性接着材３２
及放熱用銅パターン３１を介して、積極的に基板５に伝
導することができる。またエポキシ樹脂は電気的絶縁体
であるので、ＩＣチップ１と基板５との間を電気的に絶
縁することができる。さらに基板５を放熱板としても有
効に活用することができ、基板５を熱的に外装に接続す
ることにより、機器全体がＩＣの放熱器となり、放熱に
寄与することができる。また機器の小型化及び低消費電
力化などにも大きく寄与する。According to this embodiment, the thermal conductivity of the thermally conductive epoxy resin is about 1.42 W / m · k, which is much higher than the thermal conductivity of air of about 0.26 W / m · k. .. Therefore, the heat generated by the IC chip 1 is transferred to the heat conductive adhesive 32.
It is possible to positively conduct to the substrate 5 via the heat dissipation copper pattern 31. Further, since the epoxy resin is an electrical insulator, the IC chip 1 and the substrate 5 can be electrically insulated. Further, the substrate 5 can be effectively used as a heat dissipation plate, and by thermally connecting the substrate 5 to the exterior, the entire device serves as a radiator of the IC, which can contribute to heat dissipation. In addition, it greatly contributes to downsizing of devices and reduction of power consumption.
【００２４】ここでＩＣチップ１を実装する基板５も、
セラミック基板、金属ベース基板、銅箔で厚く被覆した
ガラスエポキシ基板など、熱伝導率のよい基板を用いる
ことにより、さらに放熱効果を向上することができる。The substrate 5 on which the IC chip 1 is mounted is also
The heat dissipation effect can be further improved by using a substrate having good thermal conductivity such as a ceramic substrate, a metal base substrate, or a glass epoxy substrate thickly coated with copper foil.
【００２５】上記実施例では放熱材とし熱伝導性エポキ
シ樹脂などの電気的絶縁性を有する熱伝導性接着材３２
を用いた場合について説明したが、放熱材はこれに限定
されるものでない。例えば導電性を有するペースト状の
シリコンなどの導電性ペースト３３であってもよい。こ
のペースト３３も熱伝導率は約０．９乃至１．７Ｗ／ｍ
・ｋであり、空気に比べてはるかに高い熱伝導率を有す
る。またこの放熱材を用いればＩＣチップ１と基板５と
の間の電気的導通を図ることができる。In the above-described embodiment, the heat conductive adhesive 32 having an electrically insulating property such as a heat conductive epoxy resin is used as the heat dissipation material.
However, the heat dissipation material is not limited to this. For example, the conductive paste 33 such as conductive paste-like silicon may be used. This paste 33 also has a thermal conductivity of about 0.9 to 1.7 W / m.
• k, which has a much higher thermal conductivity than air. Further, by using this heat dissipation material, electrical conduction between the IC chip 1 and the substrate 5 can be achieved.
【００２６】[0026]
【発明の効果】請求項１に記載の電子部品の実装構造に
よれば、基板と、基板にＴＡＢ実装法により実装された
電子部品との間に放熱材を充填したので、電子部品の薄
型高密度実装が可能で、しかも高放熱性を得ることがで
きる。According to the electronic component mounting structure of the first aspect, the heat dissipation material is filled between the substrate and the electronic component mounted on the substrate by the TAB mounting method. High density mounting is possible and high heat dissipation can be obtained.
【００２７】請求項２に記載の電子部品の実装構造によ
れば、放熱材が電気絶縁性を有する熱伝導性接着材であ
るので、電子部品と基板との間を電気的に絶縁すること
ができる。According to the mounting structure of the electronic component of the second aspect, the heat dissipating material is a heat conductive adhesive having electrical insulation, so that the electronic component and the substrate can be electrically insulated. it can.
【００２８】請求項３に記載の電子部品の実装構造によ
れば、放熱材が導電性ペーストであるので、電子部品と
基板との間の電気的導通を図ることができる。According to the third aspect of the mounting structure of the electronic component, since the heat dissipation material is the conductive paste, it is possible to achieve electrical conduction between the electronic component and the substrate.
【図１】本発明の電子部品の実装構造の一実施例の構成
を示す縦断面図FIG. 1 is a vertical cross-sectional view showing the configuration of an embodiment of an electronic component mounting structure of the present invention.
【図２】従来の電子部品の実装構造の一例の構成を示す
縦断面図FIG. 2 is a vertical cross-sectional view showing the configuration of an example of a conventional electronic component mounting structure.
【図３】従来の電子部品の実装構造の他の一例の構成を
示す縦断面図FIG. 3 is a vertical cross-sectional view showing the configuration of another example of a conventional electronic component mounting structure.
【図４】従来の電子部品のＴＡＢ実装法による実装構造
の一例の構成を示す縦断面図FIG. 4 is a vertical cross-sectional view showing the configuration of an example of a mounting structure of a conventional electronic component by a TAB mounting method.
【図５】図４のＴＣＰリードの一例の構成を示す平面図FIG. 5 is a plan view showing the configuration of an example of the TCP lead shown in FIG.
１ ＩＣチップ（電子部品） ２ ピン ５ 基板 ６ 配線用銅パターン（配線パターン） ２１ ＴＣＰリード（リード） ２２ キャリアテープ ３２ 熱伝導性接着材（放熱材） ３３ 導電性ペースト（放熱材） 1 IC Chip (Electronic Component) 2 Pins 5 Substrate 6 Copper Pattern for Wiring (Wiring Pattern) 21 TCP Lead (Lead) 22 Carrier Tape 32 Thermal Conductive Adhesive (Radiation Material) 33 Conductive Paste (Radiation Material)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 青木 幸男 東京都品川区北品川６丁目７番35号 ソニ ー株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Aoki 6-735 Kitashinagawa, Shinagawa-ku, Tokyo Sony Corporation
Claims (3)
リードの一端をそれぞれ電子部品のピンに接続し、他端
をそれぞれ基板上に形成された配線パターンに接続する
電子部品の実装構造において、前記電子部品と基板との
間に放熱材を充填したことを特徴とする電子部品の実装
構造。1. A mounting structure of an electronic component, wherein one end of each of a plurality of leads formed on a carrier tape is connected to a pin of the electronic component, and the other end is connected to a wiring pattern formed on a substrate, respectively. A mounting structure of an electronic component, characterized in that a heat dissipation material is filled between the electronic component and the substrate.
着材であることを特徴とする請求項１記載の電子部品の
実装構造。2. The mounting structure for an electronic component according to claim 1, wherein the heat dissipation material is a heat conductive adhesive material having electrical insulation.
徴とする請求項１記載の電子部品の実装構造。3. The mounting structure for an electronic component according to claim 1, wherein the heat dissipation material is a conductive paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3319894A JPH05129499A (en) | 1991-11-07 | 1991-11-07 | Mounting structure for electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3319894A JPH05129499A (en) | 1991-11-07 | 1991-11-07 | Mounting structure for electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129499A true JPH05129499A (en) | 1993-05-25 |
Family
ID=18115421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3319894A Withdrawn JPH05129499A (en) | 1991-11-07 | 1991-11-07 | Mounting structure for electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129499A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0883818A (en) * | 1994-09-12 | 1996-03-26 | Nec Corp | Electronic parts assembly body |
-
1991
- 1991-11-07 JP JP3319894A patent/JPH05129499A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0883818A (en) * | 1994-09-12 | 1996-03-26 | Nec Corp | Electronic parts assembly body |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |