JPH05129362A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05129362A JPH05129362A JP3290236A JP29023691A JPH05129362A JP H05129362 A JPH05129362 A JP H05129362A JP 3290236 A JP3290236 A JP 3290236A JP 29023691 A JP29023691 A JP 29023691A JP H05129362 A JPH05129362 A JP H05129362A
- Authority
- JP
- Japan
- Prior art keywords
- block
- power supply
- blocks
- cells
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05553—Shape in top view being rectangular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明はチップ内の各セルに対
し電源を供給する電源配線に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply wiring for supplying power to each cell in a chip.
【０００２】近年のゲートアレイ等の半導体装置では益
々大規模化及び高集積化が進み、これにともなって消費
電流も増大している。このため、電源配線でのエレクト
ロマイグレーションの発生を防止するためにセル及び電
源パッドの効率的なレイアウトが必要となっている。In recent years, semiconductor devices such as gate arrays have become larger and more highly integrated, and the current consumption has increased accordingly. Therefore, an efficient layout of cells and power supply pads is required to prevent electromigration in the power supply wiring.
【０００３】[0003]
【従来の技術】従来のゲートアレイでは電源配線でのエ
レクトロマイグレーションを防止するために例えば図４
に示すようにチップの１／４のセル領域を５区画のブロ
ック１ａ〜１ｅに分割し、各ブロック１ａ〜１ｅには当
該ブロック内のセル数に応じた複数の電源パッド２ａが
設けられ、各電源パッド２ａから電源配線３ａを介して
高電位側電源Ｖccが供給されている。2. Description of the Related Art In a conventional gate array, in order to prevent electromigration in a power supply wiring, for example, FIG.
As shown in FIG. 4, a 1/4 cell area of the chip is divided into five blocks of blocks 1a to 1e, and each block 1a to 1e is provided with a plurality of power supply pads 2a corresponding to the number of cells in the block. The high potential side power supply Vcc is supplied from the power supply pad 2a through the power supply wiring 3a.
【０００４】一方、低電位側電源Ｖssに関しては図５に
示すように前記１／４チップの同一セル領域を異なる５
区画のブロック１ｆ〜１ｊに分割し、各ブロック１ｆ〜
１ｊには当該ブロック内のセル数に応じた複数の電源パ
ッド２ｂが設けられ、各電源パッド２ｂから電源配線３
ｂを介して低電位側電源Ｖssが供給されている。On the other hand, regarding the low-potential-side power source Vss, as shown in FIG.
The block is divided into blocks 1f to 1j, and each block 1f to 1j
1j is provided with a plurality of power supply pads 2b corresponding to the number of cells in the block.
The low-potential-side power supply Vss is supplied via b.
【０００５】そして、前記各ブロック１ａ〜１ｅでは内
部セルの消費電流に応じた許容電流密度を備えた電源パ
ッド２ａ及び電源配線３ａが確保されて、各ブロック１
ａ〜１ｅに電源Ｖccを供給する電源パッド２ａ及び電源
配線３ａでのエレクトロマイグレーションが防止され、
前記各ブロック１ｆ〜１ｊでは内部セルの消費電流に応
じた許容電流密度を備えた電源パッド２ｂ及び電源配線
３ｂが確保されて、各ブロック１ｆ〜１ｊに電源Ｖssを
供給する電源パッド２ｂ及び電源配線３ｂでのエレクト
ロマイグレーションが防止されている。In each of the blocks 1a to 1e, the power supply pad 2a and the power supply wiring 3a having the allowable current density according to the current consumption of the internal cell are secured, and each block 1a to 1e is secured.
The electromigration in the power supply pad 2a and the power supply wiring 3a for supplying the power supply Vcc to a to 1e is prevented,
In each of the blocks 1f to 1j, the power supply pad 2b and the power supply wiring 3b having an allowable current density according to the current consumption of the internal cell are secured, and the power supply pad 2b and the power supply wiring for supplying the power supply Vss to each of the blocks 1f to 1j. Electromigration in 3b is prevented.
【０００６】[0006]
【発明が解決しようとする課題】上記のようなゲートア
レイの電源供給構成では電源Ｖccに関するブロック１ａ
〜１ｅと電源Ｖssに関するブロック１ｆ〜１ｊとはそれ
ぞれ異なっているため、図６に示すように例えば電源Ｖ
ccに関してはブロック１ａに属し、電源Ｖssに関しては
ブロック１ｈに属するセルＣではブロック１ａの電源パ
ッド２ａから供給された電流Ｉccは、セルＣを経由して
ブロック１ｈの電源パッド２ｂに流れることになる。In the power supply structure of the gate array as described above, the block 1a relating to the power supply Vcc.
1e and the blocks 1f to 1j related to the power source Vss are different from each other, as shown in FIG.
Regarding the cc, in the cell C belonging to the block 1a regarding the power supply Vss and belonging to the block 1h, the current Icc supplied from the power supply pad 2a of the block 1a flows to the power supply pad 2b of the block 1h via the cell C. ..
【０００７】このような状況で、例えばブロック１ａに
おいて消費電流が電源パッド２ａの許容電流値を越え、
ブロック１ｈにおいて消費電流が電源パッド２ｂの許容
電流値を越えた場合には両ブロック１ａ，１ｈに共通す
るセルＣを他のブロックに移動させて両ブロック１ａ，
１ｈの消費電流が当該ブロック内の各電源パッド２ａ，
２ｂの許容電流値を越えないようにする必要がある。In such a situation, for example, in the block 1a, the current consumption exceeds the allowable current value of the power supply pad 2a,
When the consumption current exceeds the allowable current value of the power supply pad 2b in the block 1h, the cell C common to both the blocks 1a and 1h is moved to another block and the blocks 1a and 1h are moved.
The current consumption of 1h is the power supply pads 2a in the block,
It is necessary not to exceed the allowable current value of 2b.
【０００８】ところが、前記セルＣを移動させても電源
Ｖcc及び電源Ｖssに関する許容電流値を越えないブロッ
クを探すためには前記セルＣを移動させた場合に電源Ｖ
ccに関して移動先のブロック１ｂ〜１ｅの消費電流が当
該電源パッド２ａの許容電流値を越えるか否かを調べ、
かつ電源Ｖssに関して移動先のブロック１ｆ，１ｇ，１
ｉ，１ｊの消費電流が当該電源パッド２ｂの許容電流値
を越えるか否かを調べる必要があり、その作業が煩雑で
ある。従って、いずれかのブロックで当該電源パッドの
許容電流値を大幅に越えて多数のセルを移動させる場合
にはその作業が極めて煩雑となるという問題点があっ
た。However, in order to search for a block that does not exceed the allowable current value related to the power source Vcc and the power source Vss even if the cell C is moved, the power source V is moved when the cell C is moved.
Regarding cc, it is checked whether or not the consumption current of the blocks 1b to 1e of the moving destination exceeds the allowable current value of the power supply pad 2a,
In addition, with respect to the power source Vss, the destination blocks 1f, 1g, 1
It is necessary to check whether or not the current consumption of i and 1j exceeds the allowable current value of the power supply pad 2b, and the work is complicated. Therefore, when a large number of cells are moved in any one of the blocks by greatly exceeding the allowable current value of the power supply pad, there is a problem in that the work becomes extremely complicated.
【０００９】この発明の目的は、セル領域を分割した多
数のブロックに対し当該ブロックに電源を供給する電源
パッドの電流許容値を越えることなく効率的にセルを配
置し得る半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device capable of efficiently arranging cells in a large number of blocks into which a cell region is divided without exceeding a current allowable value of a power supply pad for supplying power to the blocks. It is in.
【００１０】[0010]
【課題を解決するための手段】図１は本発明の原理説明
図である。すなわち、四角形状のチップのセル領域が各
対角線方向に分割されて４つの領域に分割され、前記各
領域がチップ周縁に直行する方向に複数のブロックＢに
分割され、前記各ブロックＢにはその面積に応じたセル
数が配置され、かつ前記各ブロックＢには該ブロックＢ
のセル数に応じた高電位側電源パッド２ａ及び低電位側
電源パッド２ｂが設けられている。FIG. 1 illustrates the principle of the present invention. That is, the cell area of the quadrangular chip is divided in each diagonal direction into four areas, and each area is divided into a plurality of blocks B in the direction orthogonal to the chip periphery. The number of cells corresponding to the area is arranged, and the block B is provided in each block B.
High-potential-side power supply pads 2a and low-potential-side power supply pads 2b are provided according to the number of cells.
【００１１】[0011]
【作用】各ブロックＢの消費電流は各ブロックＢの高電
位側電源パッド２ａから当該ブロックＢの内部セルを経
て当該ブロックＢの低電位側電源パッド２ｂに流れるの
で、セルをブロック間で移動させる場合には高電位側電
源パッド２ａから当該ブロックＢに流れる電流が許容電
流値を越えないようにすればよい。また、各ブロックＢ
のパッド２ａ，２ｂの許容電流値に対する消費電流の割
合はほぼ等しくなる。Since the consumption current of each block B flows from the high potential side power supply pad 2a of each block B to the low potential side power supply pad 2b of the block B through the internal cells of the block B, the cells are moved between blocks. In this case, the current flowing from the high-potential side power supply pad 2a to the block B should not exceed the allowable current value. Also, each block B
The ratio of the consumed current to the allowable current values of the pads 2a and 2b is substantially equal.
【００１２】[0012]
【実施例】以下、この発明を具体化した一実施例を図２
に従って説明すると、図２はゲートアレイを構成するチ
ップの１／４部分を示し、その１／４部分はチップの対
角線方向に分割されるとともに同チップ周縁の各辺に直
行する方向にｎ個に分割されて多数のブロックＢＸ１〜
ＢＸｎ及び同ＢＹ１〜ＢＹｎに分割されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
2 shows a quarter portion of a chip that constitutes a gate array, and the quarter portion is divided in a diagonal direction of the chip and is divided into n pieces in a direction orthogonal to each side of the peripheral edge of the chip. Divided into many blocks BX1-
It is divided into BXn and BY1 to BYn.
【００１３】各ブロックＢＸ１〜ＢＸｎ及び同ＢＹ１〜
ＢＹｎにはその面積に応じた数のセルが配設され、各ブ
ロックＢＸ１〜ＢＸｎ及び同ＢＹ１〜ＢＹｎ毎に電源Ｖ
ccを供給するパッド２ａと電源Ｖssを供給するパッド２
ｂがそれぞれ設けられている。The blocks BX1 to BXn and the blocks BY1 to BXn
BYn is provided with a number of cells corresponding to the area thereof, and a power supply V is provided for each of the blocks BX1 to BXn and BY1 to BYn.
Pad 2a for supplying cc and pad 2 for supplying power supply Vss
b are provided respectively.
【００１４】そして、例えば最も面積の広いブロックＢ
Ｘｎ，ＢＹｎではパッド２ａ，２ｂをｎ個ずつ設け、ブ
ロックＢＸｎ−１，ＢＹｎ−１ではパッド２ａ，２ｂを
ｎ−１個ずつ設け、ブロックＢＸ１，ＢＹ１ではパッド
２ａ，２ｂを１個ずつ設けるというように各ブロックの
面積に応じてパッド２ａ，２ｂの数が設定され、各ブロ
ック内には各ブロックに設けられたパッド２ａ，２ｂの
全パッド数に対する当該ブロック内のパッド数の比に応
じたセル数が配設されている。なお、Ｉ／０セル等の消
費電流の大きいセルは単位セルに換算したセル数で配設
されている。Then, for example, the block B having the largest area
It is said that n pads 2a and 2b are provided for Xn and BYn, n pads 2a and 2b are provided for blocks BXn-1 and BYn-1, and 1 pad 2a and 2b are provided for blocks BX1 and BY1. Thus, the number of pads 2a and 2b is set according to the area of each block, and the number of pads 2a and 2b in each block depends on the ratio of the number of pads in the block to the total number of pads 2a and 2b provided in each block. The number of cells is arranged. It should be noted that cells with large current consumption such as I / 0 cells are arranged by the number of cells converted into unit cells.
【００１５】従って、各ブロックＢＸ１〜ＢＸｎ及び同
ＢＹ１〜ＢＹｎ内のセルの消費電流に対する当該ブロッ
クのパッド２ａ，２ｂの電流許容値の余裕度はほぼ同一
となり、例えばブロックＢＸｎ内に位置するセルＣは図
３に示すように同ブロックＢＸｎ内のパッド２ａにより
電源Ｖccから電流Ｉccが流れ込み、その電流Ｉccが同ブ
ロックＢＸｎ内のパッド２ｂから電源Ｖssに電流ＩEEと
して流れ込む。Therefore, the margins of the current allowable values of the pads 2a and 2b of the blocks with respect to the current consumption of the cells in the blocks BX1 to BXn and the blocks BY1 to BYn are almost the same, and for example, the cell C located in the block BXn. As shown in FIG. 3, the pad 2a in the block BXn causes a current Icc to flow from the power supply Vcc, and the current Icc flows from the pad 2b in the block BXn to the power supply Vss as a current IEE.
【００１６】以上のようにこのゲートアレイは多数のブ
ロックＢＸ１〜ＢＸｎ及び同ＢＹ１〜ＢＹｎ毎に電源Ｖ
ccを供給するパッド２ａと電源Ｖssを供給するパッド２
ｂがそれぞれ設けられているので、各ブロックにおいて
電源Ｖccから流れるＩccと電源Ｖssに流れるＩEEは同一
値となる。As described above, this gate array has a power source V for each of a large number of blocks BX1 to BXn and BY1 to BYn.
Pad 2a for supplying cc and pad 2 for supplying power supply Vss
Since each b is provided, Icc flowing from the power supply Vcc and IEE flowing to the power supply Vss have the same value in each block.
【００１７】この結果、各ブロックのパッド２ａの電流
許容値に対する消費電流を確認すれば、各ブロックのパ
ッド２ｂの電流許容値に対する消費電流の余裕度を確認
する必要はなく、各ブロック内には同ブロック内のパッ
ド数に応じたセル数が配設されているので、各ブロック
のパッドの電流許容値に対する消費電流の割合はほぼ同
一となっている。従って、いずれかのブロックからセル
を他のブロックに移動させるレイアウト変更を容易に行
うことができる。As a result, if the consumption current with respect to the allowable current value of the pad 2a of each block is confirmed, it is not necessary to confirm the margin of the consumption current with respect to the allowable current value of the pad 2b of each block. Since the number of cells corresponding to the number of pads in the same block is arranged, the ratio of the consumed current to the allowable current value of the pads in each block is almost the same. Therefore, it is possible to easily change the layout to move the cell from any block to another block.
【００１８】[0018]
【発明の効果】以上詳述したように、この発明はセル領
域を分割した多数のブロックに対し当該ブロックに電源
を供給する電源パッドの電流許容値を越えることなく効
率的にセルを配置することができる優れた効果を発揮す
る。As described above in detail, the present invention efficiently arranges cells in a large number of blocks into which the cell area is divided, without exceeding the allowable current value of the power supply pad for supplying power to the blocks. It has an excellent effect.
【図１】本発明の原理説明図である。FIG. 1 is a diagram illustrating the principle of the present invention.
【図２】本発明の一実施例のブロックレイアウトを示す
概要図である。FIG. 2 is a schematic diagram showing a block layout of one embodiment of the present invention.
【図３】一実施例のセルを示す回路図である。FIG. 3 is a circuit diagram showing a cell of an example.
【図４】従来例のブロックレイアウトを示す概要図であ
る。FIG. 4 is a schematic diagram showing a block layout of a conventional example.
【図５】従来例のブロックレイアウトを示す概要図であ
る。FIG. 5 is a schematic diagram showing a block layout of a conventional example.
【図６】従来例のセルを示す回路図である。FIG. 6 is a circuit diagram showing a cell of a conventional example.
２ａ 高電位側電源パッド ２ｂ 低電位側電源パッド Ｂ ブロック 2a High-potential power supply pad 2b Low-potential power supply pad B block
Claims (1)
方向に分割して４つの領域に分割し、前記各領域をチッ
プ周縁に直行する方向に複数のブロック（Ｂ）に分割
し、前記各ブロック（Ｂ）にはその面積に応じたセル数
を配置し、かつ前記各ブロック（Ｂ）には該ブロック
（Ｂ）のセル数に応じた高電位側電源パッド（２ａ）及
び低電位側電源パッド（２ｂ）を設けたことを特徴とす
る半導体装置。1. A cell area of a quadrangular chip is divided into four areas by dividing it in each diagonal direction, and each area is divided into a plurality of blocks (B) in a direction orthogonal to the periphery of the chip. The block (B) has a number of cells according to its area, and each block (B) has a high potential side power supply pad (2a) and a low potential side power source according to the number of cells of the block (B). A semiconductor device comprising a pad (2b).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3290236A JPH05129362A (en) | 1991-11-06 | 1991-11-06 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3290236A JPH05129362A (en) | 1991-11-06 | 1991-11-06 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05129362A true JPH05129362A (en) | 1993-05-25 |
Family
ID=17753522
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3290236A Withdrawn JPH05129362A (en) | 1991-11-06 | 1991-11-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05129362A (en) |
-
1991
- 1991-11-06 JP JP3290236A patent/JPH05129362A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990204 |