JPH05129326A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the junction breakdown strength of the title semiconductor device and to achieve high speed of the title semiconductor device while an effect suppressing a short channel is being maintained in the same manner as in the case of conventional MOSFETs having an NUDC structure by a method wherein, before a gate electrode is formed, first conductivity-type impurities are implanted into a first conductivity-type semiconductor substrate and an NUDC high concentration layer is formed. CONSTITUTION:First conductivity-type impurities are channel-implanted into a first conductivity-type semiconductor substrate 11; an NUDC layer 11a composed of a first conductivity-type high concentration layer is formed. Then, a gate electrode 14 is formed; after that, second conductivity-type impurities are ion-implanted; an NUDC layer 15a composed of a first conductivity-type low concentration layer is formed. Then, second conductivity-type impurities are ion-implanted; a second conductivity-type low concentration layer 16a is formed in the NUDC layer 15a. Then a side wall 18 is formed on the gate electrode 14; after that, second conductivity-type impurities 17 are ion-implanted into the first conductivity-type semiconductor substrate 11; a source-drain layer is formed in a second conductivity-type high concentration layer 17a; a MOSFET having an NUDC structure is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a channel layer having a nonuniform distribution of impurities between a source and a drain of a MOS transistor, that is, a portion where impurities are distributed at a high concentration and an impurity. A structure having a channel layer formed of portions distributed at low concentration, so-called NUDC (A Novel Source-to-Drai)
n Non-uniformly Doped Channel) Fine M
The present invention relates to a method of forming an OSFET.

[0002]

2. Description of the Related Art Conventional methods of this kind are described in the literature (A Novel
Source-to-Drain Nonuniformly Doped Channel (NU
DC) MOSFET for High CurrentDrivability and Thres
holdVoltage Controllability; Y.Okumura et.al IEDM9
0 391-394).

The conventional technique will be described below with reference to FIGS. First, as shown in FIG. 10, a gate oxide film 2 is formed on a P-type Si substrate 1, and then a phosphorus-doped polysilicon film 3 is deposited by a CVD method. next,
As shown in FIG. 11, the gate electrode 3a is patterned by using the known photolithography technique and etching technique, and then, the boron 4 is implanted into the Si substrate 1 with an implantation angle θ of 20 to 40 degrees. Direction and rotate for ion implantation, NU
A high concentration P-type channel layer 4a of DC is obtained.

Next, as shown in FIG. 12, phosphorus 5 is ion-implanted from directly above the Si substrate 1 at an implantation angle θ of 0 °, and the LDD low-concentration N-type impurity layer (N ⁻ layer) is implanted into the channel layer 4a. ) 5
get a. Next, as shown in FIG. 13, a sidewall 7 of the gate electrode 3a is formed, and then arsenic 6 is implanted at an implantation angle θ.
Is implanted with an inclination of 7 degrees to form the high-concentration N-type impurity layer 6a as the source / drain layer.

In such an N-channel fine MOSFET, the high concentration P of the NUDC of the channel is due to the NUDC structure.
The mold layer 4a suppresses punch-through between the source and drain and suppresses the short channel effect.

[0006]

However, in the above method, the high-concentration N-type formed as the source / drain is formed due to the NUDC structure in which the high-concentration injection of P-type carriers is performed in advance in the regions for forming the source / drain. Impurity layer 6
The junction breakdown voltage between a and the high-concentration P-type channel layer 4a of NUDC is remarkably lowered, and the electric field concentration is increased, so that it is also weak against hot carriers.

[0007]

The present invention comprises:
(I) A channel of the first conductivity type impurity is implanted on the first conductivity type semiconductor substrate to form a NUDC layer of the first conductivity type high concentration layer, and (ii) on the first conductivity type high concentration layer. A gate electrode is formed, and then ion implantation is performed with a second conductivity type impurity to form a NUDC layer of a first conductivity type low concentration layer, (iii)
Then, the second conductivity type impurity for forming LDD is ion-implanted to form the second conductivity type low concentration layer of LDD on the NUDC layer of the first conductivity type low concentration layer, and (iv) the sidewall of the gate electrode. And forming a second layer on the first conductivity type semiconductor substrate.
A source / drain layer of the second conductivity type high concentration layer is formed by ion-implanting conductivity type impurities, and a NUDC structure MOS is formed.
A method for manufacturing a semiconductor device, which comprises forming an FET.

That is, the present invention does not employ a method of injecting the first-conductivity-type impurities in a high concentration after the gate electrode is formed to form the first-conductivity-type high-concentration channel layer of NUDC, and the first electrode is formed before the gate electrode is formed. By injecting the first-conductivity-type impurity in a high concentration all over the conductivity-type semiconductor substrate to form a first-conductivity-type high-concentration layer (NUDC high-concentration layer), subsequently forming a gate electrode, and then counter-doping the N-type impurities. The first conductivity type low concentration layer (NUDC low concentration layer) is formed. Then, after forming the NUDC structure, a second conductivity type low concentration layer of LDD is formed, and a sidewall of the gate electrode is further formed, and thereafter, a source / drain layer to be a source / drain layer is formed on the first conductivity type semiconductor substrate. A two-conductivity-type high-concentration layer is formed.

According to another aspect of the present invention, (i) a channel of a first conductivity type impurity is implanted on a first conductivity type semiconductor substrate to form a NUDC layer of a first conductivity type high concentration layer, (Ii) forming a gate electrode on the first-conductivity-type high-concentration layer, and then performing ion implantation with a second-conductivity-type impurity;
A NUDC layer of low conductivity type is formed, and (iii) after that, ion implantation of a second conductivity type impurity is performed on the first conductivity type semiconductor substrate to form a source / drain layer of the second conductivity type high concentration layer. It is a method for manufacturing a semiconductor device, which comprises forming a MOSFET having a NUDC structure.

That is, according to the present invention, after forming the NUDC structure, the second conductivity type high concentration layer to be the source / drain layers is formed on the first conductivity type semiconductor substrate without providing the sidewall of the gate electrode. It was done. In the NUDC structure of the present invention, the NUDC low-concentration P-type layer (first conductivity-type low-concentration layer) of the channel formed on the first conductivity type semiconductor substrate suppresses punch-through between the source and the drain, thereby causing a short circuit. The channel effect can be suppressed and the junction breakdown voltage is improved, and the NUDC low concentration P-type layer (first conductivity type low concentration layer) is also formed under the source / drain of the second conductivity type high concentration layer. Therefore, the depletion layer is likely to expand, which reduces the parasitic capacitance and provides a structure suitable for speeding up. In addition, the effect of reducing the electric field strength is also observed, and the structure has high reliability.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 1, a P-type silicon substrate 11 is formed.
NUDC high concentration P-type layer (first conductivity type high concentration layer) 11
For forming a, boron (first conductivity type impurity) 12 is ion-implanted with an energy of 20 to 50 keV and a doping amount of 5 × 10 ¹² to
Ion implantation is performed under ion implantation conditions of about 2 × 10 ¹³ / cm ² .

Next, 850 is formed on the entire surface of the silicon substrate 11.
The gate oxide film 13 and the phosphorus-doped polysilicon layer are sequentially formed by the CVD method by thermal oxidation under a heat treatment condition of about 90 ° C. to 950 ° C. Then, the gate oxide film 13 is formed by using the known photolithography technique and etching technique. The gate electrode 14 is formed thereon (see FIG. 2). Next, NUDC
In order to form the low concentration P-type layer (first conductivity type low concentration layer) 15a, phosphorus (second conductivity type impurity) 15 is added at 20 keV to 150 keV.
Rotational ion implantation in the B direction with an implantation angle θ of about 5 × 10 ¹¹ to 1 × 10 ¹³ / cm ^{2 and} an inclination of 7 ° to 60 ° (Fig. 3
reference).

Next, the LDD N^-Layer (second conductivity type low concentration
Layer) 16a to form an LDD-forming N-type impurity (first layer).
Ion implantation of two conductivity type impurities) is performed. At this time, arsenic
(Second conductivity type impurity) 16 at 30 ° to 50 keV at an injection angle of 0 °
So 1 x 10¹³~ 5 x 10¹³/cm ²NU by ion implantation
N of LDD is formed on the DC low concentration P-type layer 15a.^-Form layer 16a
(See FIG. 4).

Next, the sidewall 1 of the gate electrode 14
8 is formed of, for example, SiO ₂ , and thereafter, arsenic 17 is implanted to form an N ⁺ layer (second conductivity type high concentration layer) 17 a for source / drain at an implantation angle of 0 to 7 ° and 1 × 10 ¹⁵ at 40 to 80 keV. ~
Ion implantation is performed at 5 × 10 ¹⁵ / cm ² (see FIG. 5). As described above, in this embodiment, before the gate electrode is formed, the boron 12 is heavily implanted into the entire region of the P-type silicon substrate 11 to form the NUDC high-concentration P-type layer 11a, and subsequently, after the gate electrode 14 is formed,
By counter-doping N-type impurities, NUD
After the C low-concentration P-type layer 15a is formed, and after the NUDC structure is formed, the LDD N ^- layer 16a is formed in the NUDC low-concentration P-type layer 15a, and the side wall 18 of the gate electrode is further formed. After that, since the source / drain layer 17a of the N ⁺ layer is formed on the P-type silicon substrate 11, punch-through between the source and the drain is suppressed by the NUDC layer 15a of the channel due to the NUDC structure, so that the short channel effect is achieved. The junction breakdown voltage can be suppressed and the junction breakdown voltage is improved. Further, since the NUDC layer 15a is also formed under the source / drain of the N ⁺ layer 17a, the depletion layer easily extends, which reduces the parasitic capacitance and increases the speed. Can be realized. Further, the effect of reducing the electric field strength is also seen, and an N-channel fine MOSFET having a highly reliable NUDC structure can be obtained.

In this embodiment, the NUDC high concentration layer 11
Although a is directly formed on the P-type silicon substrate 11 is shown, the NUDC high-concentration layer 11a may be formed on the P-well formed on the P-type silicon substrate 11. Moreover, FIG.
In FIG. 9, after obtaining the structure shown in FIG. 3 of the above-mentioned embodiment, arsenic 18 is implanted at 40 ° to 80 keV at an implantation angle of 0 ° to form an N ⁺ layer (high-concentration N type layer) 18a for source / drain. × 10 ¹⁵ ~ 5
The second aspect of the present invention in which × 10 ¹⁵ / cm ² ions are implanted
An example of is shown. In this embodiment, after forming the NUDC structure, the sidewall of the gate electrode is not provided, and the N ⁺ layer 18a to be the source / drain layer is formed in the NUDC low concentration layer 15a on the P-type silicon substrate 11. (See FIG. 9).

[0016]

As described above, according to the present manufacturing method, the junction breakdown voltage can be improved and the speed can be increased while maintaining the effect of suppressing the short channel as is the case with the conventional fine MOSFET having the NUDC structure. It is possible.

[Brief description of drawings]

FIG. 1 is a structural explanatory view showing a first step of a manufacturing process in a first embodiment of the present invention.

FIG. 2 is a structural explanatory view showing a second step of the manufacturing process in the first embodiment.

FIG. 3 is a structural explanatory view showing a third step of the manufacturing process in the first embodiment.

FIG. 4 is a structural explanatory view showing a fourth step of the manufacturing process in the first embodiment.

FIG. 5 is a structural explanatory view showing a fifth step of the manufacturing process in the first embodiment.

FIG. 6 is a structural explanatory view showing a first step of a manufacturing process in the second embodiment of the present invention.

FIG. 7 is a structural explanatory view showing a second step of the manufacturing process in the second embodiment.

FIG. 8 is a structural explanatory view showing a third step of the manufacturing process in the second embodiment.

FIG. 9 is a structural explanatory view showing a fourth step of the manufacturing process in the second embodiment.

FIG. 10 is a structural explanatory view showing a first step of a manufacturing process in a conventional example.

FIG. 11 is a structural explanatory view showing a second step of the manufacturing process in the conventional example.

FIG. 12 is a structural explanatory view showing a third step of the manufacturing process in the conventional example.

FIG. 13 is a structural explanatory view showing a fourth step of the manufacturing process in the conventional example.

[Explanation of symbols]

11 P-type silicon substrate 11a NUDC high-concentration P-type layer (first-conductivity-type high-concentration layer) 12 boron (first-conductivity-type impurity) 13 gate oxide film 14 gate electrode 15 phosphorus (second-conductivity-type impurity) 15a NUDC Low concentration N type layer (first conductivity type low concentration layer) 16, 17 Arsenic (second conductivity type impurity) 16a LDD N ⁻ layer (second conductivity type low concentration layer of LDD) 17a, 18a N ⁺ layer ( Source / drain layer)

Claims (2)

[Claims] 1. (i) a first conductive type semiconductor substrate on which a first
Channel injection of conductivity type impurities is performed to form a NUDC layer of the first conductivity type high concentration layer, (ii) a gate electrode is formed on the first conductivity type high concentration layer,
After that, ion implantation is performed with the second conductivity type impurities to form a NUDC layer of the first conductivity type low concentration layer, and (iii) after that, ion implantation of the second conductivity type impurities for LDD formation is performed to perform the first conductivity A second conductivity type low concentration layer of LDD is formed on the NUDC layer of the conductivity type low concentration layer, and (iv) a sidewall of the gate electrode is formed, and then ion implantation of a second conductivity type impurity is performed on the first conductivity type semiconductor substrate. A method for manufacturing a semiconductor device, which comprises forming source / drain layers of the second conductivity type high-concentration layer to form a MOSFET having a NUDC structure. 2. (i) a first conductive type semiconductor substrate on which a first
Channel injection of conductivity type impurities is performed to form a NUDC layer of the first conductivity type high concentration layer, (ii) a gate electrode is formed on the first conductivity type high concentration layer,
After that, ion implantation is performed with the second conductivity type impurity to form a NUDC layer of the first conductivity type low concentration layer, and (iii) after that, ion implantation of the second conductivity type impurity is performed on the first conductivity type semiconductor substrate. Form a source / drain layer of the second conductivity type high concentration layer, and have a NUDC structure
A method of manufacturing a semiconductor device, which comprises forming T.