JPH05129304A - Structure of bump electrode and its manufacture - Google Patents

Structure of bump electrode and its manufacture

Info

Publication number
JPH05129304A
JPH05129304A JP28875691A JP28875691A JPH05129304A JP H05129304 A JPH05129304 A JP H05129304A JP 28875691 A JP28875691 A JP 28875691A JP 28875691 A JP28875691 A JP 28875691A JP H05129304 A JPH05129304 A JP H05129304A
Authority
JP
Japan
Prior art keywords
circuit board
insulating layer
layer
shaped body
protrusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28875691A
Other languages
Japanese (ja)
Inventor
Yasushi Karasawa
康史 柄沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP28875691A priority Critical patent/JPH05129304A/en
Publication of JPH05129304A publication Critical patent/JPH05129304A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enhance the mounting density of the title structure and to enhance the reliability of the structure after the structure has been mounted by a method wherein the structure is constituted of the following: a protrusion-shaped body which is formed on a circuit board and which has worked a single-crystal material by an anisotropic etching method; an insulating layer on the protrusion-shaped body; and a conductive layer on the insulating layer. CONSTITUTION:The structure of bump electrodes which electrically connect an electronic element to a circuit board 1 is constituted of the following: a protrusion-shaped body which is formed on the circuit board 1 and which has worked a single-crystal material by an anisotropic etching method; an insulating layer 4 on the protrusion- shaped body; and a conductor layer 5 on the insulating layer 4. For example, an Si substrate 1 whose surface has been polished and which is provided with a (100) orientation is thermally oxidized; an oxide film 2 in about 1mum is formed. Then, the oxide film 2 is etched so that protrusions about 20mum square can be formed at a pitch of about 60mum; the film is etched by 20mum by using the aqueous solution of KOH so that Si (111) orientation crystal faces 3 are exposed. Then, an insulating film composed of an oxide film 4 is formed; after that, an Al layer 5 as a conductive layer is plated; a circuit is formed by a photolithographic method.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子素子を回路基板へ
接続する突起電極の構造及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a protruding electrode for connecting an electronic device to a circuit board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、半導体素子の微細加工技術の向上
及びそれを使った製品の高機能化により、回路実装密度
の大幅な向上が要求されている。そして実現のため、半
導体の電極や回路基板の電極へめっき法等で突起電極
(バンプ)を形成し、半導体素子を回路基板へ直接接続
する実装方法が考えられた。
2. Description of the Related Art In recent years, a drastic improvement in circuit packaging density has been required due to improvements in fine processing technology for semiconductor devices and higher functionality of products using the same. For realization, a mounting method has been considered in which a protruding electrode (bump) is formed on a semiconductor electrode or an electrode on a circuit board by a plating method or the like, and a semiconductor element is directly connected to the circuit board.

【0003】[0003]

【発明が解決しようとする課題】しかしながら従来の技
術は、実装密度の向上の点で満足させるものでなかっ
た。従来のめっき法等で製造したバンプでは、電極が接
近するとめっきの横方向への成長により電極同士が短絡
し、接続ピッチを小さくすることが不可能であった。ま
たこの対策のため、めっき工程で感光性樹脂を電極高さ
まで形成し、横方向へのめっき成長を防ぐ方法がある。
しかしこの方法は、バンプが小さくなると感光性樹脂の
膜厚と電極の径の比が1に近付き、パターンが正確に現
像できないという課題を有した。
However, the conventional techniques have not been satisfactory in terms of improvement in packaging density. In the bump manufactured by the conventional plating method or the like, when the electrodes come close to each other, the plating grows in the lateral direction to short-circuit the electrodes, making it impossible to reduce the connection pitch. As a countermeasure, there is a method of forming a photosensitive resin up to the electrode height in a plating process to prevent lateral plating growth.
However, this method has a problem that when the bump becomes smaller, the ratio of the film thickness of the photosensitive resin to the diameter of the electrode approaches 1, and the pattern cannot be accurately developed.

【0004】また半導体素子に形成するバンプは、半導
体素子へめっき等の処理により形成するため、半導体素
子の製造工程が長くなり、信頼性を低下させる不安要素
を有した。
Further, since the bumps formed on the semiconductor element are formed on the semiconductor element by a treatment such as plating, the manufacturing process of the semiconductor element is lengthened, and there is an anxiety factor that reduces reliability.

【0005】本発明はこれらの課題を解決するものでそ
の目的は、回路基板側へ突起形状をめっき法に依らず形
成し、細密接続の実現と実装の信頼性を向上させるもの
である。
The present invention solves these problems, and an object thereof is to form a protrusion shape on the circuit board side without depending on the plating method, and to realize fine connection and improve the reliability of mounting.

【0006】[0006]

【課題を解決するための手段】本発明の突起電極の構造
は、電子素子と回路基板を電気的接続する突起電極の構
造において、前記回路基板上に形成され、単結晶材料を
異方性エッチング法で加工した突起形状体と、該突起形
状体上に絶縁層と、該絶縁層上に導電層とから構成され
ていることを特徴とする。
The structure of the protruding electrode of the present invention is the structure of the protruding electrode for electrically connecting an electronic element and a circuit board, and is formed on the circuit board by anisotropic etching of a single crystal material. It is characterized in that it is composed of a protrusion-shaped body processed by the method, an insulating layer on the protrusion-shaped body, and a conductive layer on the insulating layer.

【0007】また電子素子と回路基板を電気的接続する
突起電極の構造において、前記回路基板上に形成され、
絶縁層と、該絶縁層上に単結晶材料を異方性エッチング
法で加工した突起形状体と、該突起形状体上に導電層と
から構成されていることを特徴とする。
Further, in the structure of the protruding electrode for electrically connecting the electronic element and the circuit board, the protruding electrode is formed on the circuit board,
It is characterized in that it is composed of an insulating layer, a protrusion-shaped body obtained by processing a single crystal material by an anisotropic etching method on the insulating layer, and a conductive layer on the protrusion-shaped body.

【0008】また、単結晶材料がシリコンまたはガリウ
ム・ひ素であることを特徴とする。また本発明の突起電
極の製造方法は、回路基板と突起形状体がシリコン単結
晶材料で、絶縁層が酸化膜を付けたシリコン単結晶材料
の高温張り合わせまたは酸素イオンの拡散により形成す
ることを特徴とする。
The single crystal material is silicon or gallium arsenide. Further, the method of manufacturing a bump electrode according to the present invention is characterized in that the circuit board and the bump-shaped body are made of a silicon single crystal material, and the insulating layer is formed by high-temperature bonding of a silicon single crystal material with an oxide film or diffusion of oxygen ions And

【0009】本発明に用いる材料は、シリコン、ガリウ
ム・ひ素、石英、インジウム・りん等がある。
Materials used in the present invention include silicon, gallium / arsenic, quartz, indium / phosphorus and the like.

【0010】本発明の異方性エッチング法は、単結晶材
料の結晶面方位により、エッチング速度が異なるメカニ
ズムを利用した加工方法で、水溶液を用いた湿式異方性
エッチング法または反応性プラズマを用いた乾式エッチ
ング法がある。例えば湿式法でシリコンを用いたエッチ
ングは、高濃度・高温のアルカリ金属またはアルカリ土
類金属の水酸化物例えばリチウム、ナトリウム、カリウ
ム、ルビジウム、セシウム、マグネシウム、カルシウ
ム、ストロンチウム、バリウム等の水酸化物水溶液へ、
シリコンの単結晶を浸漬してエッチングすると、シリコ
ンの結晶方位である(111)方位のエッチング速度が
(110)や(100)に比べて著しく遅くなるメカニ
ズムを利用している。そして、例えば(100)の基板
上へ(110)方位にエッチングマスクとして熱酸化膜
をパターンニングすると、(111)方位でエッチング
が停止し、ミクロン単位の精密加工が可能なのである。
尚、基板の結晶方位は(110)でもエッチング機構は
変わらず、またエッチング液は、微量添加物としてメタ
ノール、エタノール、1−プロパノール、2−プロパノ
ール、1−ブタノール、2−ブタノール等のアルコール
や、界面活性剤を添加して、エッチング速度比を変える
方法もある。またガリウム・ひ素は、硫酸、過酸化水素
の混合液によりエッチングされ、他の単結晶材料も異方
性エッチングの可能なエッチング水溶液がある。
The anisotropic etching method of the present invention is a processing method utilizing a mechanism in which the etching rate varies depending on the crystal plane orientation of a single crystal material, and uses a wet anisotropic etching method using an aqueous solution or reactive plasma. There is a dry etching method. For example, etching using silicon by a wet method is a high-concentration and high-temperature alkali metal or alkaline earth metal hydroxide such as lithium, sodium, potassium, rubidium, cesium, magnesium, calcium, strontium, or barium hydroxide. To aqueous solution,
When a single crystal of silicon is dipped and etched, the etching rate of the (111) orientation, which is the crystal orientation of silicon, is remarkably slower than that of (110) or (100). Then, for example, when the thermal oxide film is patterned on the (100) substrate in the (110) direction as an etching mask, the etching is stopped in the (111) direction, and micron-precision machining is possible.
The etching mechanism does not change even if the crystal orientation of the substrate is (110), and the etching solution is a trace additive such as alcohol such as methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, and 2-butanol, There is also a method of changing the etching rate ratio by adding a surfactant. In addition, gallium / arsenic is etched by a mixed solution of sulfuric acid and hydrogen peroxide, and other single crystal materials also have an etching aqueous solution capable of anisotropic etching.

【0011】また回路を形成する導電層は、銅、アルミ
ニウム、金、銀、酸化錫や酸化インジウム・錫合金の透
明導電膜、イットリウム系焼結体や金属超伝導合金膜な
どが利用できる。さらに半導体例えばシリコンへほう素
等のイオン打ち込み、拡散等を使った導電化方法もあ
る。
As the conductive layer forming the circuit, a transparent conductive film of copper, aluminum, gold, silver, tin oxide or an indium oxide / tin alloy, a yttrium-based sintered body, a metal superconducting alloy film, or the like can be used. Further, there is also a method of electrical conductivity using ion implantation of boron or the like into a semiconductor such as silicon and diffusion.

【0012】[0012]

【作用】本発明の実装方法は、突起電極を基板へ形成す
るため、半導体素子への突起電極形成プロセスが省け、
実装後の信頼性を向上することができる。さらに異方性
エッチング技術を突起電極の加工方法として用いること
で、より狭い径の突起電極が形成でき、実装密度が向上
できるものである。
In the mounting method of the present invention, since the protruding electrode is formed on the substrate, the process of forming the protruding electrode on the semiconductor element can be omitted.
The reliability after mounting can be improved. Furthermore, by using the anisotropic etching technique as a method of processing the protruding electrodes, it is possible to form protruding electrodes having a narrower diameter and improve the packaging density.

【0013】[0013]

【実施例】以下実施例に基づいて、本発明の効果を説明
する。
EXAMPLES The effects of the present invention will be described below based on examples.

【0014】(実施例1)図1は、本実施例の回路基板
の斜視図である。
(Embodiment 1) FIG. 1 is a perspective view of a circuit board of this embodiment.

【0015】図2は、本実施例の工程別断面図である。
この図に沿って、本実施例を説明する。
FIG. 2 is a sectional view of each step of this embodiment.
This embodiment will be described with reference to this figure.

【0016】まず図2(a)のように厚さ約600ミク
ロンの表面研磨された(100)方位のシリコン基板1
を熱酸化し、約1ミクロンの酸化膜2を形成する。
First, as shown in FIG. 2 (a), a surface-polished (100) -oriented silicon substrate 1 having a thickness of about 600 μm.
Is thermally oxidized to form an oxide film 2 of about 1 micron.

【0017】次に図2(b)のようにフォトリソグラフ
ィー法及びエッチング法で約20ミクロン角の突起が約
60ミクロンピッチでできるよう、酸化膜をエッチング
し、摂氏80度、40g/lの水酸化カリウム水溶液で
シリコン(111)方位結晶面3が露出するように20
ミクロンエッチング加工した。
Next, as shown in FIG. 2B, the oxide film is etched by photolithography and etching so that projections of about 20 μm square are formed at a pitch of about 60 μm, and water at 80 ° C. and 40 g / l is used. The potassium oxide aqueous solution was used to expose the silicon (111) oriented crystal plane 3 to 20
Micron etching processing was performed.

【0018】次に図2(c)のように酸化膜4による絶
縁層を形成した後、導電層としてアルミニウム層5をめ
っきして、回路をフォトリソグラフィー法により形成し
た。最後に突起部分へ半導体素子のアルミニウム合金電
極を直接または異方性導電膜または異方性導電接着剤を
用いて接続した。
Next, as shown in FIG. 2C, an insulating layer made of an oxide film 4 was formed, and then an aluminum layer 5 was plated as a conductive layer to form a circuit by photolithography. Finally, the aluminum alloy electrode of the semiconductor element was connected to the protrusion directly or by using an anisotropic conductive film or an anisotropic conductive adhesive.

【0019】この接続は、電気的に良好であった。This connection was electrically good.

【0020】(実施例2)図3は、本実施例の工程別断
面図である。この図に沿って、本実施例を説明する。
(Embodiment 2) FIGS. 3A to 3C are sectional views showing the steps of this embodiment. This embodiment will be described with reference to this figure.

【0021】まず図3(a)のような厚さ約600ミク
ロンの(100)方位のガリウム・ひ素基板6へクロム
層7、金層8をスパッタする。
First, a chromium layer 7 and a gold layer 8 are sputtered on a gallium / arsenic substrate 6 of (100) orientation having a thickness of about 600 microns as shown in FIG.

【0022】次に図3(b)のようにフォトリソグラフ
ィー法及びエッチング法で約20ミクロン角の突起が約
60ミクロンピッチでできるよう、クロム層7、金層8
をエッチングし、硫酸1部、過酸化水素水8部、純水5
0部のエッチング水溶液でガリウム・ひ素(111)結
晶面9が露出するよう20ミクロンエッチング加工し
た。
Next, as shown in FIG. 3B, the chrome layer 7 and the gold layer 8 are formed so that projections of about 20 μm square can be formed at a pitch of about 60 μm by photolithography and etching.
By etching, 1 part of sulfuric acid, 8 parts of hydrogen peroxide solution, 5 parts of pure water
A 20 micron etching process was performed so that the gallium / arsenic (111) crystal plane 9 was exposed with 0 part of the etching aqueous solution.

【0023】次に図3(c)のように絶縁層10を形成
した後、導電層としてアルミニウム層11をめっきし
て、回路はフォトリソグラフィー法により形成した。
Next, after forming the insulating layer 10 as shown in FIG. 3C, an aluminum layer 11 was plated as a conductive layer, and a circuit was formed by a photolithography method.

【0024】最後に突起部分へ半導体素子のアルミニウ
ム合金電極を直接または異方性導電膜または異方性導電
接着剤を用いて接続した。
Finally, the aluminum alloy electrode of the semiconductor element was connected to the protrusion directly or by using an anisotropic conductive film or an anisotropic conductive adhesive.

【0025】この接続は、電気的に良好であった。This connection was electrically good.

【0026】(実施例3)実施例1のアルミニウム層を
クロム、金の積層へ変更した以外、実施例1と同様の方
法により回路基板を製造し、突起部分へ半導体素子のア
ルミニウム合金電極を接触させ接続した。
Example 3 A circuit board was manufactured in the same manner as in Example 1 except that the aluminum layer in Example 1 was changed to a laminated layer of chromium and gold, and the aluminum alloy electrode of the semiconductor element was brought into contact with the protruding portion. And connected.

【0027】この接続は、電気的に良好であった。This connection was electrically good.

【0028】(実施例4)実施例1と同様に厚さ600
ミクロンの(100)方位のシリコン単結晶基板をフォ
トリソグラフィー法及び水酸化カリウムを用いたエッチ
ング法で約20ミクロンエッチング加工した。
(Embodiment 4) A thickness of 600 as in Embodiment 1
A silicon single crystal substrate having a micron (100) orientation was etched by about 20 microns by a photolithography method and an etching method using potassium hydroxide.

【0029】次に抵抗、半導体、コンデンサ等の電子素
子を従来の半導体装置の製造方法により形成し、実施例
1と同様に導電層としてアルミニウム層をめっきして、
回路をフォトリソグラフィー法により形成した。
Next, electronic elements such as resistors, semiconductors and capacitors are formed by a conventional method for manufacturing a semiconductor device, and an aluminum layer is plated as a conductive layer in the same manner as in Example 1,
The circuit was formed by the photolithography method.

【0030】最後に突起部分へ半導体素子のアルミニウ
ム合金電極を直接または異方性導電膜または異方性導電
接着剤を用いて接続した。
Finally, the aluminum alloy electrode of the semiconductor element was connected to the protrusion directly or by using an anisotropic conductive film or an anisotropic conductive adhesive.

【0031】この接続は、電気的に良好であった。This connection was electrically good.

【0032】(実施例5)図4は、本実施例の断面図で
ある。
(Embodiment 5) FIG. 4 is a sectional view of this embodiment.

【0033】この図4のように、実施例1と同様のエッ
チング加工を行なったシリコン基板12へ、フォトリソ
グラフィー法及びほう素イオンの打ち込みにより突起部
を含む選択的な導電領域13を形成する。次にこの導電
領域に半導体素子を直接または異方性導電膜または異方
性導電接着剤を介して接触させ、電気的接続を実現し
た。
As shown in FIG. 4, a selective conductive region 13 including a protrusion is formed on a silicon substrate 12 which has been subjected to the same etching process as that of the first embodiment by a photolithography method and implantation of boron ions. Next, a semiconductor element was brought into contact with this conductive region directly or through an anisotropic conductive film or an anisotropic conductive adhesive to realize electrical connection.

【0034】この接続は、電気的に良好であった。This connection was electrically good.

【0035】(実施例6)図5は、本実施例の工程別断
面図である。この図に沿って、本実施例を説明する。
(Embodiment 6) FIGS. 5A to 5C are cross-sectional views of this embodiment in steps. This embodiment will be described with reference to this figure.

【0036】この図5(a)のように、シリコン基板1
4の中へ酸化膜15をシリコンと酸化膜付きシリコンの
接合、または酸素イオン打ち込みにより形成した基板を
用い、実施例1と同様の方法で、突起形状の加工を行っ
た。
As shown in FIG. 5A, the silicon substrate 1
In the same manner as in Example 1, the protrusion shape was processed by using the substrate in which the oxide film 15 was bonded to silicon and the silicon with oxide film was formed by implantation of oxygen ions.

【0037】そして図5(b)のように、突起形状上へ
アルミニウム層16をめっきした。この上へ半導体素子
を直接または異方性導電膜または異方性導電接着剤を介
して接触させ接続した。
Then, as shown in FIG. 5B, an aluminum layer 16 was plated on the protrusions. The semiconductor element was connected to this directly or via an anisotropic conductive film or an anisotropic conductive adhesive.

【0038】この接続は、電気的に良好であった。This connection was electrically good.

【0039】(比較例1)図6は、本比較例の工程別断
面図である。この図に沿って、本比較例を説明する。
(Comparative Example 1) FIG. 6 is a sectional view of each step of this comparative example. This comparative example will be described with reference to this figure.

【0040】まず図6(a)のように、約600ミクロ
ンの鏡面研磨されたシリコン基板17へ、酸化膜18及
びアルミニウム層19と金層20を形成する。
First, as shown in FIG. 6A, an oxide film 18, an aluminum layer 19 and a gold layer 20 are formed on a mirror-polished silicon substrate 17 of about 600 microns.

【0041】次に図6(b)のように、フォトリソグラ
フィー法により、アルミニウム層19と金層20を配線
し、約1ミクロンのネガ型感光性樹脂21を使い金層2
0を約60ミクロンピッチでシリコン上へ選択的な導電
層領域22を形成する。
Next, as shown in FIG. 6 (b), the aluminum layer 19 and the gold layer 20 are wired by the photolithography method, and the negative photosensitive resin 21 of about 1 micron is used to form the gold layer 2.
Selective conductive layer regions 22 are formed on the silicon at a pitch of about 60 microns.

【0042】次に図6(c)のように、次のような公知
の亜硫酸金塩を含む液で電解めっき法により導電層領域
22上へ金層23を約20ミクロン厚付けした。
Next, as shown in FIG. 6 (c), a gold layer 23 having a thickness of about 20 μm was formed on the conductive layer region 22 by an electrolytic plating method using the following known liquid containing a gold sulfite salt.

【0043】 (めっき液組成) 亜硫酸金ナトリウム 12 g/l 亜硫酸ナトリウム 50 g/l クエン酸ナトリウム 50 g/l 四ほう酸ナトリウム 10 g/l (めっき条件) 温度 摂氏40 度 電流密度 0.3 A/dm2 この時、突起電極同士は、横方向へのめっき成長により
電気的に接触した。
(Plating Solution Composition) Sodium gold sulfite 12 g / l Sodium sulfite 50 g / l Sodium citrate 50 g / l Sodium tetraborate 10 g / l (Plating conditions) Temperature 40 degrees Celsius Current density 0.3 A / dm2 At this time, the bump electrodes were electrically contacted by plating growth in the lateral direction.

【0044】(比較例2)比較例1のネガ型感光性樹脂
21の膜厚を約20ミクロンに代えた以外、比較例1と
同様に導電層領域を形成した。そして電解金めっきを行
ったが、感光性樹脂と導電層領域の径との比が約1のた
め、感光性樹脂が導電層領域上に残り、金を積層するこ
とができなかった。
Comparative Example 2 A conductive layer region was formed in the same manner as Comparative Example 1 except that the film thickness of the negative photosensitive resin 21 of Comparative Example 1 was changed to about 20 μm. Then, electrolytic gold plating was performed, but since the ratio of the photosensitive resin to the diameter of the conductive layer region was about 1, the photosensitive resin remained on the conductive layer region and gold could not be laminated.

【0045】以上のように実施例の接続は、電気的に良
好であったが、比較例は電気的短絡やめっき不能のよう
に、突起電極製造時点で良好な品物が得られなかった。
As described above, the connection of the example was electrically good, but in the comparative example, a good product could not be obtained at the time of manufacturing the protruding electrode, such as electrical short circuit or plating failure.

【0046】また実施例1から6の接続済み回路基板へ
エポキシ樹脂を接続部分に塗布し、長期信頼性へ投入評
価した。その結果を表1に示す。
Epoxy resin was applied to the connected portions of the circuit boards that had been connected in Examples 1 to 6 and evaluated for long-term reliability. The results are shown in Table 1.

【0047】[0047]

【表1】 [Table 1]

【0048】このように狭い突起電極の径でも実施例
は、接続信頼性が良好であった。
In this example, the connection reliability was good even with such a narrow protruding electrode diameter.

【0049】尚、本実施例のアルミニウム層は、銅、
金、銀、酸化錫や酸化インジウム・錫合金の透明導電
膜、イットリウム系焼結体や金属超伝導合金膜、タング
ステンなどでも、本発明の効果に変わりなく、その形成
方法は、スパッタ、蒸着、CVD、電気めっき、無電解
めっき等でもよい。また厚付けする金層は、銀、銅、ニ
ッケル合金、コバルト合金、パラジウム合金でもよい。
The aluminum layer in this embodiment is copper,
Even transparent conductive films of gold, silver, tin oxide or indium oxide / tin alloy, yttrium-based sintered bodies, metal superconducting alloy films, tungsten, etc. do not change the effect of the present invention, and the forming method is sputtering, vapor deposition, CVD, electroplating, electroless plating, etc. may be used. The thick gold layer may be silver, copper, nickel alloy, cobalt alloy, or palladium alloy.

【0050】さらにシリコンやガリウム・ひ素以外にイ
ンジウム・リンや石英でも本発明の効果に変わりがなか
った。
Further, in addition to silicon, gallium, and arsenic, indium, phosphorus, and quartz did not change the effect of the present invention.

【0051】またシリコンの異方性エッチングは、結晶
方位を(110)にしてもよく、そのエッチング液を水
酸化カリウムの他に水酸化ナトリウム、水酸化リチウ
ム、水酸化セシウム等のアルカリ及び微量添加物として
メタノール、エタノール、1−プロパノール、2−プロ
パノール、1−ブタノール、2−ブタノール、弗素系界
面活性剤等へ代えても、効果に変わりがなかった。また
CF4ガス等のプラズマを用いた異方性エッチング技術
によっても効果に変わりなかった。
In the anisotropic etching of silicon, the crystal orientation may be set to (110), and the etching solution may be alkali hydroxide such as sodium hydroxide, lithium hydroxide or cesium hydroxide, or a trace amount thereof in addition to potassium hydroxide. Even if the substance was replaced with methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, 2-butanol, a fluorine-based surfactant or the like, the effect was not changed. Further, the effect was not changed even by the anisotropic etching technique using plasma such as CF4 gas.

【0052】[0052]

【発明の効果】以上述べたように本発明の突起電極構造
は、回路基板へ突起電極を異方性エッチング法を用いて
形成するため、実装密度を向上できる効果を有する。ま
たバンプ付き半導体素子を用いた実装方法に比べ、半導
体素子側のバンプ製造工程を必要としない。そのため実
装コストの低減が可能で、また半導体素子の製造工程が
短くなり、信頼性の改善が図れる。さらに回路基板へ他
の電子素子が形成できるため、回路としての実装密度が
向上できる効果を有する。
As described above, the bump electrode structure of the present invention has the effect of improving the packaging density because the bump electrodes are formed on the circuit board by the anisotropic etching method. Further, as compared with a mounting method using a semiconductor element with bumps, a bump manufacturing process on the semiconductor element side is not required. Therefore, the mounting cost can be reduced, the manufacturing process of the semiconductor element can be shortened, and the reliability can be improved. Further, since another electronic element can be formed on the circuit board, there is an effect that the packaging density as a circuit can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明における実施例1の回路基板の斜視
図。
FIG. 1 is a perspective view of a circuit board according to a first embodiment of the present invention.

【図2】 本発明における実施例1の工程別断面図。FIG. 2 is a sectional view of each step of Embodiment 1 of the present invention.

【図3】 本発明における実施例2の工程別断面図。3A to 3C are cross-sectional views according to steps of a second embodiment of the present invention.

【図4】 本発明における実施例5の断面図。FIG. 4 is a sectional view of a fifth embodiment of the present invention.

【図5】 本発明における実施例6の工程別断面図。5A to 5C are cross-sectional views according to steps of a sixth embodiment of the present invention.

【図6】 本発明における比較例の工程別断面図。6A to 6C are cross-sectional views according to steps of a comparative example of the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 酸化膜 3 シリコン(111)方位結晶面 4 酸化膜 5 アルミニウム層 6 ガリウム・ひ素基板 7 クロム層 8 金層 9 ガリウム・ひ素(111)結晶面 10 絶縁層 11 アルミニウム層 12 シリコン基板 13 導電領域 14 シリコン基板 15 酸化膜 16 アルミニウム層 17 シリコン基板 18 酸化膜 19 アルミニウム層 20 金層 21 感光性樹脂 22 導電層領域 23 金層 1 Silicon Substrate 2 Oxide Film 3 Silicon (111) Oriented Crystal Plane 4 Oxide Film 5 Aluminum Layer 6 Gallium / Arsenic Substrate 7 Chromium Layer 8 Gold Layer 9 Gallium / Arsenic (111) Crystal Plane 10 Insulating Layer 11 Aluminum Layer 12 Silicon Substrate 13 Conductive region 14 Silicon substrate 15 Oxide film 16 Aluminum layer 17 Silicon substrate 18 Oxide film 19 Aluminum layer 20 Gold layer 21 Photosensitive resin 22 Conductive layer region 23 Gold layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 電子素子と回路基板を電気的接続する突
起電極の構造において、前記回路基板上に形成され、単
結晶材料を異方性エッチング法で加工した突起形状体
と、該突起形状体上に絶縁層と、該絶縁層上に導電層と
から構成されていることを特徴とする突起電極の構造。
1. In a structure of a projection electrode for electrically connecting an electronic element and a circuit board, a projection-shaped body formed on the circuit board and processed by a single crystal material by an anisotropic etching method, and the projection-shaped body. A structure of a bump electrode, comprising: an insulating layer on the insulating layer; and a conductive layer on the insulating layer.
【請求項2】 電子素子と回路基板を電気的接続する突
起電極の構造において、前記回路基板上に形成され、絶
縁層と、該絶縁層上に単結晶材料を異方性エッチング法
で加工した突起形状体と、該突起形状体上に導電層とか
ら構成されていることを特徴とする突起電極の構造。
2. In a structure of a protruding electrode for electrically connecting an electronic element and a circuit board, an insulating layer formed on the circuit board and a single crystal material processed on the insulating layer by an anisotropic etching method. A structure of a projection electrode, comprising a projection-shaped body and a conductive layer on the projection-shaped body.
【請求項3】 請求項1記載の単結晶材料がシリコンま
たはガリウム・ひ素であることを特徴とする突起電極の
構造。
3. The structure of the bump electrode, wherein the single crystal material according to claim 1 is silicon or gallium arsenide.
【請求項4】 請求項2記載の回路基板と突起形状体が
シリコン単結晶材料で、絶縁層が酸化膜を付けたシリコ
ン単結晶材料の高温張り合わせまたは酸素イオンの拡散
により形成することを特徴とする突起電極の製造方法。
4. The circuit board according to claim 2, wherein the projection-shaped body is made of a silicon single crystal material, and the insulating layer is formed by high-temperature bonding of a silicon single crystal material with an oxide film or diffusion of oxygen ions. Method for manufacturing bump electrode.
JP28875691A 1991-11-05 1991-11-05 Structure of bump electrode and its manufacture Pending JPH05129304A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28875691A JPH05129304A (en) 1991-11-05 1991-11-05 Structure of bump electrode and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28875691A JPH05129304A (en) 1991-11-05 1991-11-05 Structure of bump electrode and its manufacture

Publications (1)

Publication Number Publication Date
JPH05129304A true JPH05129304A (en) 1993-05-25

Family

ID=17734302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28875691A Pending JPH05129304A (en) 1991-11-05 1991-11-05 Structure of bump electrode and its manufacture

Country Status (1)

Country Link
JP (1) JPH05129304A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7387945B2 (en) 2004-05-11 2008-06-17 Seiko Epson Corporation Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same
JP2017128020A (en) * 2016-01-20 2017-07-27 セイコーエプソン株式会社 Mems device, liquid jet head, liquid jet device, and manufacturing method for mems device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7387945B2 (en) 2004-05-11 2008-06-17 Seiko Epson Corporation Semiconductor chip, semiconductor device and electronic equipment including warpage control film, and manufacturing method of same
JP2017128020A (en) * 2016-01-20 2017-07-27 セイコーエプソン株式会社 Mems device, liquid jet head, liquid jet device, and manufacturing method for mems device

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