JPH05128015A - Method for testing delay - Google Patents

Abstract

PURPOSE:To attain the dynamic test of a pass including a memory by switching the reading addresses of a memory and checking whether the value of reading data read out from the switched address is changed within a certain time after the switching or not. CONSTITUTION:An input pass 18 from the input pin 12 of a circuit 10 to be tested up to the address input terminal of a memory 14 built in the circuit 10 and an output pass 24 from the data output terminal 20 of the memory 14 up to the output pin 22 of the circuit 10 are secured 100. An address in the memory 14 is switched 102 from the input pin 12 through the input pass 18. Whether the signal value of the output pin 22 is changed up to the lapse of a previously set time after the switching of the reading address of the memory 14 or not is judged 104. Thereby even when a memory exists in the pass of the circuit, a delay failure in the pass can be detected by testing the pass.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay test method for performing a delay test of a path in a circuit.

When a gate or path in the circuit has a delay fault, an operation error occurs when this circuit is incorporated in an actual product.

Therefore, a test of this kind has been carried out. Especially, with regard to LSI, with the increase in integration and speed,
An AC test to check the delay characteristics and a delay test to check the overdelay of internal gates and paths are essential.

[0004]

2. Description of the Related Art A conventional device for performing this type of test is based on the premise that only a basic gate, a latch, and a flip-flop exist on the path of a circuit to be tested, and therefore, a RAM or a ROM. The path where is present was not subject to the test.

Therefore, conventionally, a memory portion is cut out by an additional circuit, and a functional test is performed on this memory portion alone.

[0006]

In the functional test of the memory unit, the memory portion is cut out from the circuit to be tested, so the path in which the memory is actually used is not tested.
Moreover, since the test content is limited to static ones such as stuck-at faults, dynamic faults such as delay faults could not be detected.

Therefore, it is impossible to completely guarantee the operation of the product by performing a dynamic test on the address input, data input, data output and control input paths of the memory.

The present invention has been made in view of the above conventional circumstances, and an object of the present invention is to provide a method capable of dynamically testing a path including a memory.

[0009]

First invention: In FIG. 1, from an input pin 12 of a circuit 10 to be tested to an address input terminal 16 of a memory 14 built in the circuit 10.
To the input path 18 and the data output terminal 2 of the memory 14
An output path 24 from 0 to the output pin 22 of the circuit 10 is secured (step 100), and the memory is provided from the input pin 12 of the circuit 10 to the address input terminal 16 of the internal circuit memory 14 via the input path 18. The read address is switched (step 102), and it is checked whether or not the signal value of the output pin 22 has changed before the preset time elapses after the read address of the internal circuit memory 14 is switched (step 104). ..

Second invention: In FIG. 2, an address input path 38 from the first input 32 of the circuit 30 to be tested to an address input terminal 36 of a memory 34 built in the circuit 30 and the circuit 30 of the circuit 30. From the second input 40 to the memory 3
Data write input path 4 to data write input 42
4 (step 200), and the first of the circuits 30
A fixed memory write address is applied to the address input terminal 36 of the circuit built-in memory 34 from the input 32 via the address input path 38 (step 202), and the second input 40 of the circuit 30 inputs the data write input path 44. The data write operation is performed to the data write input 42 of the circuit built-in memory 34 at a preset timing (step 204), and the data output terminal 46 of the circuit built-in memory 34 is executed.
To the output pin 48 of the circuit 30 (step 206) and whether the expected value is output from the data output terminal 46 of the circuit internal memory 34 via the output path 50 is determined by the circuit. The signal value taken from the output pin 48 of 30 is checked (step 208).

[0011]

The first invention is premised on that different values are written in advance in the read addresses to be switched,
The read address of the memory 14 is switched to check whether the value of the read data changes within a fixed time after the switching.

According to a second aspect of the present invention, a write operation is performed at the same address at a predetermined timing and it is checked whether or not the write is normally performed. Each of write data, write enable signal and chip select signal is input. You can test your pass.

FIG. 3 shows a block configuration of a general RAM (400). The RAM 400 shown in FIG.
00, 302, driver 304, selector 306, RA
It is composed of an M block 308 and a controller.

The decoders 300 and 302 have n address signal lines (AD0 to ADn-1), and the controller 310 has m data input signal lines (DI0 to Dm-1).
Write enable signal line (WE), chip select signal line (CS), m data output signal lines (D00 to D0m-
1) is connected.

FIG. 4 illustrates the input / output function of the RAM 400 in the form of a truth table, and FIGS. 5 and 6 show timing charts during writing and reading.

FIG. 7 illustrates the address switching test of the first aspect of the invention, in which the input address of the RAM 400 is changed and different values (0, 1) are written in advance.

Then, the address in which the value is written is switched, and it is checked whether or not the output value of the RAM 400 normally changes (0 → 1) within a fixed time (access time TACC + delay amount of input / output path).

8 and 9 are for explaining the second invention. In FIG. 8, a data input setup test and a hold test are performed, and in FIG. 9, a chip select setup test and a release time test are performed. ..

In the setup test of FIG. 8, the data value (DIi) of the same address is switched, and the data value (DIi) after switching is changed by the trailing edge change of the write enable (WE).
Is checked in the RAM 400.

For example, after writing the initial value "0" to a certain address of the RAM 400, the data value is switched to write the value "1", and the write enable signal is pulse-changed at a timing considering the setup time of the RAM 400.

At this time, if there is a delay fault in the path portion on the data write side, the change of the write data is delayed, and the write enable signal (WE) is reached at the time of the value "0".
Since the trailing edge change is input to the RAM 400, the value of the same address remains "0".

If no delay fault exists in the path portion on the data writing side, the write enable signal (WE) changes after the write data value changes to "1".
Since the trailing edge change is input to the RAM 400, the value of the same address changes to '1'.

Therefore, after the above operation is performed, the value of the address is read out and whether the value is "0" or "1" is checked to determine whether or not there is a delay fault in the data write path portion. It becomes possible to judge.

On the other hand, in the hold test shown in the figure, the same data writing as in the above-mentioned setup test is performed, but the write enable is pulse-changed in consideration of the hold time of the RAM 400 at the time of writing.

For example, after writing the data of value "0" to a certain address of the RAM 400, the data value is switched to rewrite it to the value of "1", and the write enable signal (WE) is changed at a timing considering the hold time of the RAM 400. ) Pulse change.

At this time, if there is a delay fault in the path portion of the write enable input, the write enable signal (WE) is delayed for rewriting the data, so the data value of the same address remains "0". ..

Also, if there is no delay fault in the path portion of the write enable input, the rewrite data of the value "1" is input to the RAM 400 after the change of the write enable signal (WE). The address value is'
Change to 1 '.

Therefore, after the above operation is performed, the value of the above address is read and it is checked whether the value is "0" or "1" to determine whether or not there is a delay fault in the path portion of the write enable input. It is possible to determine whether or not.

In FIG. 9, the presence / absence of a delay fault in the path portion of the chip select input is examined. In the setup test of FIG. 9, in order to write the value “1” after writing “0” to a certain address of the RAM 400. ,
The chip select signal (CS) is changed to DOWN (change to a value for selecting a RAM chip).

Further, the write enable (WE) is pulse-changed in consideration of the setup time, and then the value of the same address is read.

When the read value is "1", it is confirmed that the pass portion of the chip select input is normal with respect to the DOWN change of the chip select signal (CS), but the read value is "1". If it is 0 ', a delay fault in the path portion is detected.

In the release time test shown in the figure, the chip select signal (CS) is changed by UP, and the write enable signal (WE) is changed by pulse in consideration of the release time.

Then, the value of the same address is read out, and if the value is "0", it is confirmed that the path portion of the chip select is normal to the UP change of the chip select signal (CS). However, if the read value is "1", it can be determined that a delay fault exists in the path portion.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 10 shows the configuration of a delay tester, and a delay test of an LSI 1002 is started by a tester main body 1004 according to an instruction input from a keyboard 1000.

In this example, the LSI 1002 has a RAM 100
6, the test result of the LSI 1002 is output from the tester main body 1004 to the display 1008,
Displayed to the operator of the testing machine.

FIG. 11 shows an LSI 1002 in which only a RAM 1006 is incorporated. In FIG.
D0, IAD1, IDI, IWE, and ODO are LSI10
No. 02, the first address input, the second address input, the data input, the write enable input, the data output terminal or its signal are shown, and AD0, AD1, D
I, WE, and DO respectively indicate a first address input terminal, a second address input terminal, a data input terminal, a write enable input terminal, a data output terminal or their signals provided in the RAM 1006.

Further, TAD, TDT, TWE and TDO are terminals IA.
Between DO and AD0, between terminals IDI and DI, terminals IWE and W
Path delays between E and terminals DO and ODO are shown.

Below, the address switching test (see FIG. 7), the setup test and the hold test (see FIG. 8) are shown in FIG.
And will be sequentially described with reference to FIGS. 13 and 14.

/ * Address test * / In FIG. 12, the signal IADO is "0" and IDA1 is "0".
1 ', IDI is' 0 ', IWE is'N' 1st pattern "0, 1, 0, negative pulse (1 → 0 → 1)"
N ”is input to the LSI 1002, and the value“ 0 ”is written to the address (0,1) B of the RAM 1006 (as a result, R
The value of the AM output signal DO and the LSI output signal ODO is "0".
Will be).

Next, the second pattern "1, 1, 1, N" is set to L.
Input to SI1002 and write the value '1' to address (1,1) B of RAM1006 (resulting in RAM
The values of the output signal DO and the LSI output signal ODO are "1").

Further, the third pattern "0, 1, 1, 1"
Input to LSI1002 and pass IADO → AD0 → R
AM1006 → DO → ODO is activated, address (0,1) B is read, and the value of the path output is set to “0”.

Finally, the fourth pattern "1,1,1,1"
Is input to the LSI 1002 to read the address (1, 1) B, and the value of the path output is set to “1” (above, steps 100 and 102: path securing and address switching).

Then, the measurement of the time at which the value change (“0” → “1”) of the path output occurs after the address switching is started,
Predetermined time T (= TAD + TACC + TDO, TACC: RAM1
If the change occurs before the access time (006), it is confirmed that the above-mentioned path delay fault does not exist.

If there is no change in the path output value ('0' → '1') within a predetermined time, it can be confirmed that a delay fault exists in the path (the above steps are performed). 104).

The time T is preset by operating the keyboard 1000. Further, this test is also effective for the ROM, and in that case, a pair of addresses in which different values are written are determined and both are switched.

/ * Setup test * / In FIG. 13, first, the first pattern of "0, 0, 0, N" is input to the LSI 1002, and the address (0, 0) B is input.
Write the data of value "0" to.

Then, the second pattern of "0,0,0,1" is input to the LSI 1002 to activate the path portions IDI → DI and IWE → WE.

Further, the third pattern of "0, 0, 1, N" is input to the LSI 1002, the value of the address (0, 0) B is rewritten ("0" → "1"), and the signal IW.
Pulse change E (WE) (above, step 20
0,202,204).

Here, in the RAM 1006, the signal DI
The settling time for the signal WE of TRST is expressed by TRST, and the positive correction time at which the set-up is possible in the normal state and the set-up fails in the case of a delay failure is ΔtRS
Expressed as T, the change time of the pulse trailing edge of the signal IWI is defined as the time when the time of TS = TDT + TRST-TWE + ΔtRST elapses after the signal IDI is switched (actually, the variation of the element is taken into consideration. It is preferable that this value be input from the keyboard 1000).

Therefore, when the setup is successful, the data of the value "1" is output from the address (0,0) B of the RAM 1006, and when the setup is unsuccessful (the path part IDI → DI is delayed. Data having a value of "0" is output.

Therefore, the fourth pattern of "0, 0, 1, 1" is finally input to the LSI 1002, and the RAM data at the address (0, 0) B is input from the terminal DO to the terminal ODO.
Read out.

The value of the data read at that time is "1".
When is, the path part of the data write input (IDI → DI)
It can be confirmed that there is no delay failure in the data input. Also, when the value of the read data is '0', the setup failed, so there is a delay in the data write input path (IDI → DI). It can be confirmed that a failure exists.

/ * Hold test In the / * hold test, the same patterns (first to fourth) as in the setup test are applied to the LSI 1002.

However, in the hold test, the change of the signal DI which should not be taken in originally is delayed in the RAM 10 with the delay of the signal WE.
The purpose of this test is to check whether or not there is a malfunction that 06 takes in. Therefore, the signal I in the third pattern is
The change time of the trailing edge of the pulse of WE is defined as after the time TH has elapsed since the change of the signal IDI.

Assuming that the time TH is the hold time of the RAM 1006 with respect to the signal WE of the signal DI, and the positive correction time ΔTRHD is the positive hold time that the reliable hold can be performed in the normal state and the hold fails in the delay failure, = TDT-TRHD-TWE-ΔtRHD, which is set in advance by operating the keyboard 1000.

Therefore, the fourth pattern is the LSI100.
When input to 2, the pass part (I
When there is no delay fault in (WE → WE), the data of value “0” is output from the terminal ODO.

If there is a delay fault in the path portion (IWE → WE), the data of value “1” is output from the terminal ODO.

/ * More specific test / * FIG. 15 shows an LSI 1002 in which flip-flops 1500 and 1502 are provided on the input side and the output side of the RAM 1006. Therefore, these flip-flops 1500 and 1502 are included in the LSI 1002. Clock input terminals CLK1 and CLK2 of 1502 are added.

Inputs CLK1 and CL of this LSI 1002
FIG. 16 shows K2, IAD0, IAD1, IDI, and IWE.
The first pattern to the eighth pattern are sequentially input, and when the first pattern to the fourth pattern are input, (0, 0) B and (0,
1) The values "0" and "1" are written to the B address.

Then, with the input of the fifth pattern, the initial value of the flip-flop 1500 is set to "0", and the value ("1") when the value of the signal D0 changes from "0" to "1" is set to the flip-flop. The initial value of the flip-flop 1502 is set to “0” by the input of the sixth pattern so that the flip-flop 1502 can be loaded into the chip 1502.

Further, the path to be tested (CLK1 → flip-flop 1500 → AD0 → RAM1006 → D0
→ flip-flop 1502 → DT) is activated by the input of the seventh pattern.

Next, the eighth pattern is input to the LSI 1002 to pulse-change the signals CLK1 and CLK2, and the data value change ('0' → '1') of the path is taken into the flip-flop 1502.

Here, the delay of the path part (CLK1 → flip-flop 1500 → AD0) is TAD, the delay TD0 of the path part (DO → flip-flop 1502 → DT), the path part (CLK2 → flip lop 1502 →
CK) delay is TCK2, and the setup time of the flip-flop 1502 for the data clock is TFS
When the positive correction time at which the T and flip-flop 1502 are normal can be set up, and the delay is a failure, the positive correction time is represented by ΔtFST.
The trailing edge of the pulse of K2 is TC = TAD + TACC + TDO + TFST-TCK2 + ΔtF after the trailing edge of the pulse of the signal CLK1 changes.
It is defined as the time when the time ST has elapsed (time TC is set by operating the keyboard 1000).

Finally, the ninth pattern is input to the LSI 1002 and the output of the flip-flop 1502 is input to the terminal ODO.
And the value of the flip-flop output is "1".
Check if it is '0'.

For example, when the signal value extracted from the terminal ODO is "0", there is a delay fault in the path (CLK1 → flip-flop 1500 → AD0 → RAM1006 → DO → flip-flop 1502 → DT). Can be confirmed.

As described above, even if the memory (RAM or ROM) exists on the path in the LSI 1002, the delay test of the path can be performed.
It is possible to guarantee the dynamic operation of the product and significantly increase the reliability of the product.

[0067]

As described above, according to the present invention, even when the memory exists on the path in the circuit,
This path can be tested to detect the delay failure, so by using the static function test mentioned above,
It is possible to dramatically improve the reliability of the product by simultaneously performing the dynamic operation guarantee and the static operation guarantee of the circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the first invention.

FIG. 2 is a diagram illustrating the principle of the second invention.

FIG. 3 is a block diagram of a RAM.

FIG. 4 is an explanatory diagram of an input / output function of a RAM.

FIG. 5 is a timing chart when writing to a RAM.

FIG. 6 is a timing chart when reading a RAM.

FIG. 7 is an explanatory diagram of an address switching test.

FIG. 8 is an explanatory diagram of a data input system setup / hold test.

FIG. 9 is an explanatory diagram of a chip select setup / release time test.

FIG. 10 is an explanatory diagram of the configuration of the embodiment.

FIG. 11 is an explanatory diagram of an LSI configured only with RAM.

FIG. 12 is an explanatory diagram of an address switching test.

FIG. 13 is an explanatory diagram of a setup test.

FIG. 14 is an explanatory diagram of a hold test.

FIG. 15 is an explanatory diagram of an LSI in which a flip-flop is provided on the input / output side of a RAM.

FIG. 16 is an explanatory diagram of an address switching test of an LSI provided with a flip-flop on the input / output side of a RAM.

[Explanation of symbols]

 1000 keyboard 1002 LSI 1004 tester main body 1006 RAM 1008 display 1500 flip-flop 1502 flip-flop

Claims (2)

[Claims] 1. A memory (1) built in a circuit (10) to be tested from an input pin (12) of the circuit (10).
4) Input path (1) to the address input terminal (16)
8) and the input path (2) from the data output terminal (20) of the memory (14) to the output pin (22) of the circuit (10).
4) and (100), and from the input pin (12) of the circuit (10) to the input path (1
The memory read address applied to the address input terminal (16) of the internal circuit memory (14) via (8) is switched (102), and a preset time has elapsed since the read address of the internal circuit memory (14) was switched. It is checked whether the signal value of the output pin (22) has changed by the time (10
4), A delay test method characterized by the above. 2. A memory (3) built into the circuit (30) from a first input (32) of the circuit (30) to be tested.
4) Address input path (38) to the address input terminal (36) and data write from the second input (40) of the circuit (30) to the data write input (42) of the memory (34). An input path (44) is secured (200), and the first input (32) of the circuit (30) is connected to the address input terminal (36) of the internal circuit memory (34) through the address input path (38). A fixed memory write address is given (202), and the data write input (42) of the circuit built-in memory (34) is input from the second input (40) of the circuit (30) through the data write input path (44). ) Is written at a preset timing (204), and an output path (50) from the data output terminal (46) of the circuit built-in memory (34) to the output pin (48) of the circuit (30). ) Secure ( 06), whether or not the expected value is output from the data output terminal (46) of the circuit built-in memory (34) via the output path (50) is fetched from the output pin (48) of the circuit (30). A delay test method characterized by checking with a signal value (208).