JPH05127982A - Electronic equipment - Google Patents

Abstract

PURPOSE:To provide electronic equipment capable of detecting easily and surely the difference of memory hardware even in the case that write-in to a memory can not be executed. CONSTITUTION:A chip select signal to select one of a ROM 30, a RAM 40, and an EEP ROM 50 is generated by an address decoder 21 in response to the addressing of a CPU 10. A discrimination signal generation circuit 22 outputs a signal corresponding to the chip classification of the ROM 30, the RAM 40, and the EEP ROM 50 in response to this chip select signal. The discrimination signal generation circuit 22 is assigned to prescribed memory addresses, and the CPU 10 can input the information of the chip classification by reading the memory address of the discrimination signal generation circuit 22 just after memory access if necessary. In the case that the classification of the memory elements 30 to 50 is changed, the discrimination signal generation circuit 22 is exchanged in accordance with this.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic equipment, especially CPU.
And an electronic device having a predetermined memory element built therein, the CPU identifying the type of the memory element and performing control according to the identification result.

[0002]

2. Description of the Related Art Conventionally, various electronic devices using a microcomputer (hereinafter referred to as CPU) such as a word processor, a personal computer and various home electric appliances have been known. In this type of device, the peripheral devices surrounding the CPU are diversified depending on the purpose of use of each device, the configuration of the control input / output function of the CPU, and the physical difference in the storage system. Is progressing.

For example, a kanji ROM is installed in a certain model of a personal computer for domestic use in Japan, but when this model is shipped overseas, the kanji ROM is not installed and a RAM or an EEPROM is installed at the address. I have something to do.

On the other hand, the software (OS etc.) for controlling such a device often has the same hardware configuration, and therefore the basic structure of the control software tends to be common. Such control software often performs a hardware configuration search process in the initialization process in order to grasp the difference in the physical configuration of the hardware to be controlled.

For example, as a part of initialization processing of the control logic circuit of the device itself, in order to grasp the memory configuration in which the CPU controls and manages, the memory search process of the device is executed and mounted in the device. A memory configuration list is created, and subsequent control processing is executed based on this memory configuration list.

In a general computer system, a search is performed in advance based on a device mounting list (device list) prepared in advance according to a device configuration assumed in advance (at the time of design), and a match is found with the device list. Take the method of adopting the contents of the device list.

[0007]

However, in the above-mentioned conventional method, when the hardware is identified and the installed hardware is very similar, the type cannot be identified only by the search process. The current situation is that there are none.

[0008] For example, a device has a product specification
It is assumed that there may be different memory spaces as shown on the left and right of FIG.

In the case of the conventional memory search method, the control software of this device writes / reads to / from the RAM space and creates a memory list while confirming the matching of the data.

However, when there are devices having different device configurations as shown in FIG. 1, it is not possible to determine the difference between the two with respect to the memory space only by matching the write data, from the characteristics of the storage elements. In the case of FIG. 1, address C000
Both H and FFFFH (hexadecimal number) are readable and writable, so RAM and EEP-ROM cannot be distinguished.

As in the case of the right side of FIG. 1, the EEP
-Most of the devices that use ROM store semi-permanent data that is reluctant to rewrite in EEP-ROM, so it is easy to back up the contents unless it is guaranteed. Search processing by writing / reading should not be performed.

The object of the present invention is to solve the above problems by
An object of the present invention is to provide an electronic device that can easily and reliably detect a difference in memory hardware even when writing to a memory cannot be performed such as when an EP-ROM is mounted.

[0013]

In order to solve the above problems, in the present invention, a CPU and a predetermined memory element are built in, the CPU identifies the type of the memory element, and controls according to the identification result. In an electronic device that performs the above, an address decoder that generates a chip select signal that selects a mounted memory element according to the addressing of a CPU, and a type of memory element that is selected according to the chip select signal output from the address decoder The identification information according to
C has a discriminating means for outputting to a predetermined address space of PU, and
The PU outputs a predetermined address to access the memory element to the address decoder, and then reads a predetermined address space assigned to the identifying means, so that the type identifying information of the memory element output by the identifying means. The configuration to input is adopted.

[0014]

According to the above configuration, the CPU can input the type identification information of the memory element by accessing the address of the target memory element and then reading the predetermined address space.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings.

FIG. 2 shows the structure of an electronic device adopting the present invention. The CPU 10 has a CPU bus including an address bus, a data bus, and other control lines, and the CPU 10 has a PAL 20, a ROM 30, and a RAM via the CPU bus.
40 and EEPROM 50.

A PAL (Programmable Array Logic) 20 is composed of two parts, an address decoder 21 and an identification signal generating circuit 22. The address decoder 21 has the same function as a normal one, and from the address value supplied from the CPU 10 via the address bus, the ROM 30, RA
A chip select signal CS (CS-rom, CS-ram, CS-eeprom) is generated to select either the M40 or the EEPROM 50. ROM30, RAM40 and EEPROM
Necessary low-order parts of the address bus are connected to 50, which are 0000H, B000H, and C, respectively.
Address decoder 2 to have an address from 000H
1 is set.

The identification signal generation circuit 22 is constructed as a ROM, and the identification signal generation circuit 22 is an IO of the CPU.
It is assigned to the address space (or of the main memory), and by reading this address (hereinafter referred to as F0H for example), the CPU 10 causes the identification signal generating circuit 2
2 output data can be input.

The identification signal generating circuit 22 includes a ROM 30, R
By the chip select signal CS (CS-rom, CS-ram, CS-eeprom) of the AM 40 and the EEPROM 50, data indicating the type of the accessed chip is output.

The identification signal generating circuit 22 includes ROM, R
In order to identify the chip type such as AM, EEPROM,
For example, the following data including 2 bits (b1, b0) is output.

[0021] Here, at least four types of memory chips can be identified by 2 bits. Allocate more bits,
A larger number of memory chip types may be identified.

In the identification signal generating circuit 22, the CPU 10 reads R
When any one of the OM 30, the RAM 40 and the EEPROM 50 is accessed, a signal for identifying the chip type is output based on the chip select signal output by the address decoder 21.

The identification signal generating circuit 22 includes a ROM 30, R
When chips of different types are mounted at the positions of the AM 40 and the EEPROM 50, the identification signal generating circuit 22 is replaced so as to output different data accordingly.

FIG. 3 is a timing chart for explaining the operation of the above configuration. In the illustrated example, the CPU 10
Identifies the chip type of the EEPROM 50. CPU1
For 0, first, an access is made to read a predetermined address (its head address in the illustrated example) of the EEPROM 50. This read access may be a dummy operation, and C
The PU 10 does not necessarily need to use the read data.

The address decoder 21 outputs a chip select signal for selecting an appropriate chip from the output address of the CPU 10. In this case, since the access is to the EEPROM 50, the chip select signal CS-eeprom is valid.

The identification signal generating circuit 22 receives the chip select signal CS-eeprom of the address decoder 21 from the EEPRO.
The “01” data representing M is output.

The CPU 10 can input this identification data by reading the IO address F0H in the next cycle.

According to the present embodiment, if the identification signal generating circuit 22 is provided with a device for outputting appropriate identification data according to the combination of the mounted memory elements, the CPU 10 does not perform the memory writing operation. The memory type can be identified only by the read operation.

After the target memory address is accessed (the dummy read operation is sufficient), the CPU reads the predetermined address assigned by the identification signal generation circuit 22 to easily and quickly identify the identification information of the memory element type. Can be entered in. If the identification information of the type of the memory element is not needed, it is not necessary to read the address of the identification signal generation circuit 22, and the change of the control program is the minimum necessary.
There is no problem that the speed of other processing is affected by the identification of the memory element type.

Further, according to the present embodiment, the EEPROM
Even in a device that adopts, the memory type can be determined without destroying the already written data.

Further, according to the present embodiment, since each device type depends on the hardware, it is possible to share software resources in similar systems having different storage elements. In addition to cost efficiency, high productivity can be expected in terms of quality.

The present invention can be implemented in various electronic devices such as word processors, personal computers, and various home appliances.

[0033]

As is apparent from the above, according to the present invention, an electronic device having a CPU and a predetermined memory element built therein, the CPU discriminating the type of the memory element and performing control according to the discrimination result. , An address decoder for generating a chip select signal for selecting a mounted memory element according to the addressing of the CPU, and identification information according to the type of the memory element selected according to the chip select signal output from the address decoder To a predetermined address space of the CPU, the CPU outputs a predetermined address to the memory device to access the memory element, and then reads the predetermined address space assigned to the identification means. Therefore, the configuration for inputting the type identification information of the memory element output by the identification means is adopted.

Therefore, the CPU can input the type identification information of the memory element by accessing the address of the target memory element and then reading the predetermined address space. The memory device can be accessed by a read operation, and therefore, the memory device can be easily identified without writing to the memory, and software assets can be shared in similar systems having different storage devices. It is possible to achieve high efficiency in terms of time or cost in system development, and it is possible to expect high productivity in terms of quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a problem of a conventional device.

FIG. 2 is a block diagram of a main part of an electronic device adopting the present invention.

FIG. 3 is a timing chart showing the operation of the device shown in FIG.

[Explanation of symbols]

 10 CPU 20 PAL 21 Address Decoder 22 Identification Signal Generation Circuit 30 ROM 40 RAM 50 EEPROM

Claims (1)

[Claims] 1. A CPU and a predetermined memory device are built-in,
In an electronic device in which a CPU identifies a type of a memory element and performs control according to the identification result, an address decoder that generates a chip select signal that selects a mounted memory element according to an address designation of the CPU; Has identification means for outputting identification information according to the type of the memory element selected according to the chip select signal output by the CPU to a predetermined address space of the CPU, and the CPU provides a predetermined address to access the memory element. An electronic device characterized in that, after being output to the address decoder, the type identification information of the memory element output by the identifying unit is input by reading a predetermined address space assigned to the identifying unit.