JPH05127932A - Data processor - Google Patents

Abstract

PURPOSE:To prevent the free-running of a data processing 10 a processing panel on a data processor composed of a CPU panel loading CPU and the processing panel executing the prescribed data processing in accordance with control by means of CPU. CONSTITUTION:In the data processor which is constituted by the CPU panel 1 that loads CPU 10 and that is installed to a main body in freely attachably and detachably, and the processing panel 3 which is installed to the main body in freely attachably and detachably and which executes the data processing in accordance with control by CPU, and which gives the notice of the abnormal state of CPU to the processing panel 3 when abnormality occurs in CPU, a detection means 20 detecting the unloaded state of the CPU panel 1 is provided on the processing panel 3 or a detection panel 2 which is separately provided, and an OR means 31 outputting CPU abnormal information when the detection means 20 detects the unloaded state of the CPU panel 1 or when the abnormal state of CPU 10 is detected is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CP equipped with a CPU.
The present invention relates to a data processing device including a U panel and a processing panel that executes prescribed data processing under the control of a CPU, and more particularly to a data processing device that can reliably prevent self-running of data processing of the processing panel. Is.

As a data processing device, it is composed of a CPU panel which is equipped with a CPU and is detachably mounted on the main body, and a processing panel which is detachably mounted on the main body and executes prescribed data processing under the control of the CPU. There are things. When adopting such a configuration, it is necessary to prevent the data processing of the processing panel from moving independently of the control of the CPU.

[0003]

2. Description of the Related Art Conventionally, in a data processing device composed of a CPU panel and a processing panel, in order to prevent self-running of data processing of the processing panel, a CPU abnormality such as a watchdog timer circuit for detecting an abnormality of the CPU. CP detection circuit
When the CPU abnormality detection circuit is configured to be provided on the U panel and the CPU abnormality is detected, the CPU stop signal is output to the CPU to stop the operation of the CPU and the CPU stop. By outputting a signal to the processing panel, a CPU abnormality is notified to the processing panel to prevent self-run of the data processing.

[0004]

However, in such a conventional technique, when the CPU panel is pulled out from the main body, the connection between the CPU panel and the processing panel is cut off. On the other hand, the CPU stop signal for instructing the stop of the data processing is not supplied. From now on, there is a problem that the data processing of the processing panel is self-propelled and the arbitrary data processing is executed.

The present invention has been made in view of the above circumstances, and in a data processing device including a CPU panel having a CPU mounted thereon and a processing panel for executing prescribed data processing under the control of the CPU, the CPU It is an object of the present invention to provide a new data processing device capable of preventing self-running of data processing of a processing panel even if the panel is pulled out from the main body.

[0006]

FIG. 1 illustrates the principle configuration of the present invention. In the figure, 1 is a CPU panel which is detachably attached to the data processing apparatus main body, 2 is a detection panel which is detachably attached to the data processing apparatus main body, and 3 is a processing panel which is detachably attached to the data processing apparatus main body Is. The detection panel 2 may be provided as a part of the processing panel 3 instead of being provided separately from the processing panel 3.

Reference numeral 10 is a CP provided on the CPU panel 1.
U, which controls the entire data processing device, 1
Reference numeral 1 denotes a CPU abnormality detecting means provided on the CPU panel 1 for detecting an abnormal state of the CPU 10.

Reference numeral 20 is a detection means provided on the detection panel 2 for detecting whether or not the CPU panel 1 is mounted on the main body of the data processing apparatus, and 21 is preferably a memory provided on the detection panel 2. Means, CP
It stores the program data to be decoded and executed by U10.

Reference numeral 30 is a data processing means provided on the processing panel 3, which executes prescribed data processing under the control of the CPU 10, and 31 is a logical sum means provided on the processing panel 3, for example, a CPU. When the abnormality detecting means 11 detects an abnormal state of the CPU 10 or when the detecting means 20 detects an unmounted state of the CPU panel 1, the data processing means 30 is notified of that fact.

[0010]

In the present invention, the CPU abnormality detecting means 11 is the CP
When the abnormality of U10 is detected, the CPU stop signal is output to the CPU to stop the operation of the CPU, and the CPU stop signal is sent to the logical sum means 31. On the other hand, when the detecting means 20 detects the unmounted state of the CPU panel 1, it notifies the logical sum means 31 of that fact.

In this way, the OR means 31 makes the CP
When the CPU stop signal is received from the U abnormality detecting means 11,
When the data processing means 30 is instructed to stop the execution of the data processing, and when the detection means 20 receives the unmounted state notification of the CPU panel 1, the data processing means 30 is instructed to stop the data processing execution.

According to the process of issuing the execution stop instruction, C
In addition to the case where the abnormality occurs in the PU 10, the self-running of the data processing unit 30 can be reliably prevented even when the CPU panel 1 is not mounted.

When the memory means 21 is provided on the detection panel 2, the CPU 10 can be operated even when the detection panel 2 itself is not attached to the main body of the data processing apparatus.
When the CPU abnormality detection means 11 sends a CPU stop signal to the OR means 31, the data processing means 30 can be prevented from running.

[0014]

EXAMPLES The present invention will be described in detail below with reference to examples. FIG. 2 illustrates one embodiment of the present invention. In the figure,
The same components as those described in 1 are indicated by the same symbols.

Reference numeral 11a is a watchdog timer circuit provided on the CPU panel 1, which detects whether the CPU 10 is normal or abnormal, and outputs a low level value when the CPU 10 is normal, and the CPU 10 outputs the low level value. When it is abnormal, it operates so as to output a high level value. Reference numeral 12 denotes an open collector output type inverter circuit provided on the CPU panel 1, which receives the output value of the watchdog timer circuit 11a as its input value. Is a ground fault circuit provided on the CPU panel 1 and operates to ground the signal line 14 connected to the detection panel 2.
Here, the watchdog timer circuit 11a operates in accordance with the high level value output to the inverter circuit 12
The process of 0 is stopped.

Reference numeral 22 is a pull-up resistor provided on the detection panel 2, and a DC voltage (for example, 5) is applied to the signal line 23 connected to the signal line 14 provided on the CPU panel 1.
V), 24 is a detection panel 2
An open collector output type inverter circuit provided above, which receives a potential value of a connection point (hereinafter, referred to as a connection point A) between the pull-up resistor 22 and the signal line 23, and inverts and outputs the input value. It works like this.

Reference numeral 30a is a controller provided on the processing panel 3 for executing a prescribed control processing under the control of the CPU 10. Reference numeral 31a is a wired OR circuit for outputting the output value of the inverter circuit 12 and the inverter circuit 24. It operates so as to supply the electric potential value at the connection point with the output value to the controller 30a.

Next, the operation processing of the embodiment configured as described above will be described. CPU panel 1 and detection panel 2
When the CPU 10 is operating normally, the watchdog timer circuit 11a outputs a low level value to the inverter circuit 12, and The inverter circuit 12 receives the value input and the wired OR circuit 3
It outputs a high level value to 1a. On the other hand, at this time, since the signal line 14 of the CPU panel 1 and the signal line 23 of the detection panel 2 are connected, the inverter circuit 24
The low-level potential value of the connection point A is input to
Upon receiving this low level value input, the inverter circuit 24
Outputs a high level value to the wired OR circuit 31a.

The wired OR circuit 3 receives the high-level output processing of the two inverter circuits 12 and 24.
1a outputs a high level value to the controller 30a, and in response to this output, the controller 30a changes the CP
Both the U panel 1 and the detection panel 2 are attached to the data processing apparatus main body, and it is determined that the CPU 10 is operating normally and the prescribed control processing is executed.

In this way, when an abnormality occurs in the CPU 10 during normal operation, the watchdog timer circuit 11a detects this abnormality and detects the abnormality in the CPU 10.
Operation of the inverter circuit 12
To the wired OR circuit 31a, the inverter circuit 12 outputs a low level value to the wired OR circuit 31a. Then, receiving this low level value input, the wired OR circuit 31a
Outputs a low level value to the controller 30a, and in response to this output, the controller 30a causes the CPU
When it is determined that an abnormality has occurred on the 10 side, execution of the control process is stopped.

When an abnormality occurs in the CPU 10 in accordance with this operation, the controller 30a immediately stops the control processing without running on its own. If the CPU panel 1 is not attached to the main body of the data processing device at the time of normal operation, the potential value of the connection point A is set to a high level value, and the high level value input is received. Then, the inverter circuit 24 outputs a low level value to the wired OR circuit 31a. Then, receiving this low level value input, the wired OR
The circuit 31a outputs a low level value to the controller 30a, receives this output, and receives the output from the controller 30a.
Determines that an abnormality has occurred on the CPU 10 side and stops the execution of the control process.

According to these operations, when the CPU panel 1 is not mounted, the controller 30a immediately stops the control process without running on its own.

In the embodiment of FIG. 2, CP
If the memory for storing the program data decoded by the U10 is mounted on the detection panel 2, even if the detection panel 2 itself is not attached to the main body of the data processing device, the watchdog is stopped due to the operation stop of the CPU 10. Since the timer circuit 11a detects the abnormality of the CPU 10, the controller 30a can stop the execution of the control process according to the above process.

In this way, it is possible to reliably prevent the self-running of the controller 30a even when the detection panel 2 is not mounted in addition to when the CPU 10 has an abnormality.

Although the illustrated embodiment has been described, the present invention is not limited to this. For example, in the example,
Although the detection panel 2 is disclosed as being provided separately from the processing panel 3, it may be integrally provided with the processing panel 3. Further, in the embodiment, the wired OR circuit 3
Although the logical sum configuration according to 1a is disclosed, it may be configured using a normal logical sum gate.

[0026]

As described above, according to the present invention,
In a data processing device including a CPU panel equipped with a CPU and a processing panel that executes prescribed data processing under the control of the CPU, when the CPU panel becomes unmounted in addition to when the CPU has an abnormality In addition, it is possible to prevent self-running of data processing on the processing panel.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is an example of the present invention.

[Explanation of symbols]

 1 CPU panel 2 Detection panel 3 Processing panel 10 CPU 11 CPU abnormality detection means 20 Detection means 21 Memory means 30 Data processing means 31 Logical sum means

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Satoru Tsushima 2-1-1, Jomi, Chuo-ku, Osaka-shi, Osaka Twin 21 MID Tower within Fujitsu Kansai Digital Technology Co., Ltd. (72) Inventor Kenichi Kuwako, Osaka-shi, Osaka Chuo-ku Jomi 2-61-1, Twin 21 MID Tower, within Fujitsu Kansai Digital Technology Co., Ltd. (72) Inventor Yukio Shima 2-61, Jomi, Chuo-ku, Osaka City, Osaka Twin 21 MID Tower Fujitsu Kansai Digital Technology Within the corporation

Claims (2)

[Claims] 1. A CPU panel (1) which is equipped with a CPU and is detachably attached to a main body, and a processing panel (3) which is detachably attached to the main body and executes prescribed data processing under the control of the CPU. In the data processing device configured to notify the abnormal state of the CPU to the processing panel (3) when an abnormality occurs in the CPU, the unmounted state of the CPU panel (1) is detected. Detection means
(20) is provided on the processing panel (3) or on the detection panel (2) which is provided separately from the CPU panel (1) and the processing panel (3) and is detachably attached to the main body. And, when the detection means (20) detects the unmounted state of the CPU panel (1) or when the abnormal state of the CPU is detected, the logical sum means (31) for outputting the CPU abnormal information A data processing apparatus comprising: a processing panel (3), wherein the processing panel (3) is configured to stop a data processing operation when the logical sum means (31) outputs CPU abnormality information. 2. The data processing apparatus according to claim 1, wherein when the detection means (20) is provided on the detection panel (2),
A memory means (21) for storing program data required by the CPU is provided on the detection panel (2), whereby an abnormality occurs in the CPU when the detection panel (2) is not mounted. A data processing device characterized by being configured as described above.