JPH05122503A - Image reader - Google Patents

Abstract

PURPOSE:To reduce quantizing error in case of converting picture element density, to suppress the lowering of image quality and to shorten time required for converting the picture element density by calculating the average value of delayed pixel data and undelayed pixel data. CONSTITUTION:The output of a CCD image sensor 101 is converted to a stepwise signal for each picture element by a sample/hold circuit 102 and outputted to a shading correction circuit 103. The shading-corrected image signal is inputted to a phase conversion circuit 104, delayed by a clock pulse from a clock generation circuit 107 and transmitted to an average circuit 105. The circuit 105 transmits the average value of the output from the circuit 103 and the output from the circuit 104 to an A/D converter 106. Then, the average value output is converted to the signal of 8 bits and outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading device for reading an original image by using an image sensor such as CCD.
More specifically, the present invention relates to an image reading device that converts pixel density using an analog image signal that is taken out from an image sensor and sequentially transferred.

[0002]

2. Description of the Related Art An image reading apparatus applied to a digital copying machine, a facsimile apparatus, etc.
The image is read by converting it into an electric signal using an image sensor such as (Charge Coupled Devices). The reading of an original image in such an image reading apparatus is generally performed by irradiating the original image with light from a light source, reducing the reflected light from the original image with a lens and forming an image on a CCD image sensor (main line). Images in the (scanning direction) are read, and scanning in the sub-scanning direction is performed by moving the light source or the document.

The CCD image sensor accumulates charges corresponding to the brightness of the reflected light from the original image, and the accumulated charges are sequentially transferred and taken out as an analog image signal. The extracted analog image signal is digitized after being subjected to processing such as shading correction.

The pixel density and linear density read by the image reading device (hereinafter collectively referred to as reading density) are generally determined by the photosensitive element of the image sensor, and the linear density is the sub-scanning direction. Depends on the scanning speed of. Therefore, the linear density conversion can be performed by changing the scanning speed in the sub-scanning direction, but the pixel density conversion cannot change the density of the photosensitive element. Therefore, the apparent pixel density conversion is performed. ing.

A conventional pixel density conversion will be described below. FIG. 5 shows a block diagram of the structure of a conventional image reading device, in which a CCD is read by dividing an original image into pixels.
Image sensor 501 and CCD image sensor 501
A sample that holds the output (image signal) from
Hold circuit 502 and sample and hold circuit 502
A shading correction circuit 503 that performs shading correction on the image signal output from the A / D converter 504 that digitizes the image signal that has been subjected to the shading correction, and stores the digitized image signal for each pixel. It is composed of a memory 505 and an arithmetic circuit 506 that reads out and operates according to the pixel density for converting the pixel data stored in the memory 505.

The operation of the above configuration will be described. An output sequentially taken out from the photosensitive element (not shown) of the CCD image sensor 501 is converted into a stepwise signal for each pixel by holding the sampling and holding circuit 502 between sampling points, and then is output to the shading correction circuit 503. Is output. The shading correction circuit 503 performs shading correction on the input image signal (pixel data) and outputs it to the A / D converter 504, and the A / D converter 504 digitizes the image signal.

The image signal digitized by the A / D converter 504 is temporarily stored in the memory 505. The arithmetic circuit 506 reads the pixel data stored in the memory 505 and calculates the arithmetic result according to the pixel density, for example,
When converting the pixel density of two adjacent pixels on one line into one pixel, the pixel density conversion is performed by outputting the average value of these two pixel data.

[0008]

However, according to the conventional image reading apparatus, since the pixel density is converted by using the digitized image signal (pixel data),
There is a problem that the quantization error becomes large and the image quality may deteriorate. In particular, the smaller the number of levels used in quantization, the larger the quantization error, which may lead to a significant deterioration in image quality.

Further, since it is necessary to temporarily store the image signal in the memory, it takes a long time to convert the pixel density.

The present invention has been made in view of the above, and reduces the quantization error when converting the pixel density, suppresses the deterioration of the image quality due to the quantization error, and is required for the conversion of the pixel density. The purpose is to reduce the time.

[0011]

In order to achieve the above object, the present invention is an image reading apparatus for reading an original image by using an image sensor such as a CCD, and an analog image taken out from the image sensor and sequentially transferred. It is an object of the present invention to provide an image reading apparatus provided with a delay means for delaying and outputting a signal and an average value output means for outputting an average value of an input and an output of the delay means.

Further, it is desirable that the delay means has a clock pulse output means, and delays the output by using the clock pulse outputted by the clock pulse output means in the previous period. Further, it is preferable that the delay means has a plurality of delay circuits for delaying the analog image signal, and each delay circuit delays the analog image signal by using the clock pulse output from the clock pulse generating means.

Further, it is desirable that the clock pulse output means can change the frequency of the clock pulse to be output. Further, it is desirable that the clock pulse output means can output a plurality of clock pulses whose phases are shifted.

[0014]

In the image reading apparatus according to the present invention, the sequentially transferred analog image signals (pixel data) are delayed by the delay means according to the conversion of the pixel density, and the delayed pixel data and the undelayed pixels are delayed. The pixel density is converted by outputting the average value of the data. The delay means delays the image signal by using the clock pulse, and converts the pixel density with high accuracy.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of the configuration of the image reading apparatus of the first embodiment, in which a CCD image sensor 101 for reading an original image by dividing it into pixels and a zero-order hold of an output (image signal) from the CCD image sensor 101. Sample and hold circuit 102 and shading correction circuit 10 for performing shading correction on an image signal
3 and a phase conversion circuit 10 for delaying and outputting an image signal
4, an averaging circuit 105 that outputs an average value of a plurality of (delayed or undelayed) image signals according to the pixel density to be converted, and an image signal output from the averaging circuit 105 is digitized. A / D converter 106,
It is composed of a clock generation circuit 107 that outputs a clock pulse to the phase conversion circuit 104.

The operation of the above configuration will be described. An output sequentially taken out from a photosensitive element (not shown) of the CCD image sensor 101 is converted into a staircase-shaped signal for each pixel by holding a sampling and holding circuit 102 between sampling points, and then is output to a shading correction circuit 103. Is output. The shading correction circuit 103 performs shading correction on the input image signal (pixel data) and outputs it to the phase conversion circuit 104. The phase conversion circuit 104 uses the clock pulse input from the clock generation circuit 107 to output the image signal. Is delayed and output to the averaging circuit 105. Here, the frequency of the clock pulse output by the clock generation circuit 107 is changed by a predetermined control signal.

The averaging circuit 105 outputs the average value of the output from the shading correction circuit 103 and the output from the phase conversion circuit 104 to the A / D converter 106. A
The / D converter 106 converts this average value output into an 8-bit digital signal (image signal) and outputs it.

FIG. 2 shows a circuit diagram of the phase conversion circuit 104 and the averaging circuit 105. As shown, the phase conversion circuit 1
Reference numeral 04 is composed of an operational amplifier 104a, a capacitor C1, and a switch S1 which is opened / closed by a clock pulse. The averaging circuit 105 includes operational amplifiers 105a and 105a.
05b and resistors R1, R2, R3, R4, and R5.

In the above configuration, the operation will be described by taking the case of doubling the pixel density as an example. FIG. 3 shows a timing chart when the pixel density is doubled.

When the pixel density is doubled as shown in FIG. 3, the clock generation circuit 107 synchronizes with the image signal and outputs a clock pulse whose cycle is equal to the transfer time per pixel. The switch S1 is controlled to be opened / closed so that it is opened when the clock pulse is HIGH and closed when the clock pulse is LOW. Since the charge stored in the capacitor C1 when the switch S1 is closed is released when the switch S1 is opened, the image signal is delayed by half a pixel with respect to the input and then output.

The input and output of the phase conversion circuit 104 are input to the inverting terminal of the operational amplifier 105a of the averaging circuit 105 via resistors R1 and R2, respectively. Resistors R1 and R
The resistance values of 2 and R3 are equal, and therefore the output of the operational amplifier 105a has a value obtained by adding the voltage values applied to the resistors R1 and R2. The output of the operational amplifier 105a is further input to the non-inverting terminal of the operational amplifier 105b via the resistor R4. The resistance value of the resistor R4 is twice the resistance value of the resistor R1 and the resistance value of the resistor R5 is Since the resistance value is equal to the resistance value of the resistor R1, the operational amplifier 105b outputs half the value of the input, that is, the value obtained by averaging the input and output of the phase conversion circuit 104 (see FIG. 3). In this way, the pixel density can be doubled, but if the frequency of the clock pulse is set to 1/2 the frequency when the pixel density is doubled, the pixel density can be converted to 1/2. You can If the pixel density is not converted, the switch S
1 should be closed.

Quantization error occurs when converting analog data into digital data, but when digital data is used to perform arithmetic processing, the quantization error in the arithmetic result becomes even larger. However, like the present invention, if the pixel density is converted using analog data and then digitized, the quantization error is not increased and the deterioration of the image quality due to the conversion of the pixel density can be suppressed.
Further, since the output analog image signals are sequentially processed, it is possible to prevent the processing speed from being lowered due to once being stored in the memory as in the conventional case. Further, since the pixel density conversion is performed by opening / closing the switch S1 by using the clock pulse, the pixel density conversion can be performed with high accuracy, and one delay circuit can provide a plurality of pixel density conversions. The conversion can be done.

Next, a second embodiment will be described. The second embodiment is different from the first embodiment in that the phase conversion circuit 1
04, averaging circuit 105, and clock generation circuit 10
It is a modification of 7. FIG. 4 shows the configuration of this modified part, which includes two phase conversion circuits 401 and 402,
Input of phase conversion circuit 401 and phase conversion circuits 401 and 4
An averaging circuit 403 that inputs the output of 02 and outputs an average value thereof, and a clock generation circuit 404 that can output a clock pulse by shifting the phase at the same frequency with respect to the phase conversion circuits 401 and 402 are provided. ..

The structure of the phase conversion circuits 401 and 402 is as follows.
It is similar to the phase conversion circuit 104 in the first embodiment, but the configuration of the averaging circuit 403 is slightly different from the averaging circuit 105. This different main part will be described with reference to FIG. 2. The input and output of the phase conversion circuit 401 and the output of the phase conversion circuit 402 can be input to the inverting terminal of the operational amplifier 105a. That is, the resistor R4 is a volume resistor whose resistance value is variable, which is a part different from the averaging circuit 105.

In the above configuration, the operation of the second embodiment will be described by taking as an example the case where the pixel density is tripled. The clock pulse output from the clock generation circuit 404 has a cycle of 1/2 of the transfer time of data for one pixel, and this clock pulse is shifted to the image signal by 1/3 cycle and output to the phase conversion circuit 401. , Phase conversion circuit 4
It is output after being shifted by 2/3 cycle with respect to 02. As a result, the output of the phase conversion circuit 401 is delayed by 1/3 cycle with respect to the input, and the output of the phase conversion circuit 402 is delayed by 2 with respect to the input.
/ 3 cycle delay.

The input of the phase conversion circuit 401, the output of the phase conversion circuit 401, and the output of the phase conversion circuit 402 are input to the averaging circuit 403, and the averaging circuit 403 outputs the average value of these inputs. Thus, the pixel density is tripled. To output the average value, referring to FIG. 2, the volume resistance (corresponding to the resistance R4) of the averaging circuit 403 is set to a value three times the resistance value of the resistance R1.

In the second embodiment, in addition to converting the pixel density to 3 times, the pixel density is 1/2 times, 1/3 times,
It can be doubled. When the pixel density is converted to double (or 1/2), for example, the phase conversion circuit 40
It is possible to make 2 unused (at this time, the resistance value of the volume resistance of the averaging circuit 403 is also converted and converted). When the pixel density is converted to 1/3, a clock pulse whose cycle is 1/2 of the transfer time of data for one pixel is applied to the phase conversion circuits 401 and 402 in synchronization with the image signal. At this time, the input of the phase conversion circuit 402 may be the output of the phase conversion circuit 401.

As described above, in the first embodiment, only two kinds of pixel density conversion, that is, 1/2 or double, are added. However, as in the second embodiment, another phase conversion circuit is added. By doing so, four types of conversion will be possible. If another phase conversion circuit is added (three in total), six types of conversion (1/4, 1/3, 1/2, 2, 3, and 4 times) can be performed.

The present invention can also be used as a smoothing filter because it can output the average value of adjacent or neighboring pixel data. At this time, by controlling the number of phase conversion circuits used and the delay amount of each phase conversion circuit,
The degree of smoothing can be adjusted.

[0030]

As described above, the image reading device of the present invention is an image reading device for reading an original image using an image sensor such as a CCD, and delays the analog image signal taken out from the image sensor and sequentially transferred. Since the delay means for outputting the output and the average value output means for outputting the average value of the input and the output of the delay means are provided, the quantization error in converting the pixel density is reduced, and the image quality due to the quantization error is reduced. Can be suppressed and the time required for conversion of pixel density can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an image reading apparatus according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a phase conversion circuit and an averaging circuit according to the first embodiment.

FIG. 3 is a timing chart showing a case where the pixel density is doubled.

FIG. 4 is an explanatory diagram showing a configuration of a second embodiment.

FIG. 5 is an explanatory diagram showing a configuration of a conventional image reading apparatus.

[Explanation of symbols]

104 phase conversion circuit 104a operational amplifier 105 averaging circuit 105a operational amplifier 105b operational amplifier 107 clock generation circuit 401 402 phase conversion circuit 403 averaging circuit 404 clock generation circuit S1 switch C1 capacitors R1 to 5 resistors

Claims (5)

[Claims] 1. An image reading apparatus for reading an original image using an image sensor such as a CCD, delaying means for delaying and outputting analog image signals taken out from the image sensor and sequentially transferred; An image reading apparatus comprising: an average value output means for outputting an average value of input and output. 2. The image reading apparatus according to claim 1, wherein the delay unit has a clock pulse output unit, and delays the output by using the clock pulse output from the clock pulse output unit in the previous period. 3. The delay means has a plurality of delay circuits for delaying an analog image signal, and each delay circuit delays the analog image signal by using a clock pulse output from the clock pulse generating means. The image reading apparatus according to claim 1 or 2, wherein: 4. The image reading apparatus according to claim 2, wherein the clock pulse output means can change the frequency of the clock pulse to be output. 5. The image reading apparatus according to claim 2, wherein said clock pulse output means is capable of outputting a plurality of clock pulses whose phases are shifted.