JPH05121685A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce chip size by burying wiring for supplying power and wiring for grounding in a semiconductor substrate. CONSTITUTION:Wiring 3 and wiring 4 are formed on an N-type well 2 formed in a P-type silicon substrate 1 and on the region except the N-type well 2. An N-type well 2a is formed in a P-type silicon layer 6 formed on the surface containing the wiring 3 and the wiring 4, so as to conform with the N-type well 2, and the wiring 3 is electrically isolated from the wiring 4. A MOS transistor is formed on each of the N-type well 2a and the P-type silicon layer 6, and connected with the wiring 3 and the wiring 4 in the substrate. Thereby chip size is reduced, and, at the same time, a signal line can be freely arranged on elements. Electric potential of the well and the substrate is stabilized in virture of existance of the wiring 3 and the wiring 4, so that latch-up can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit,
In particular, it relates to a semiconductor integrated circuit having a CMOS transistor.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional semiconductor integrated circuit is provided with an N-type well 2 provided on a P-type silicon substrate 1 and a P-type silicon substrate 1 including the N-type well 2 to form an element. The P-type diffusion layer 9 provided in the N-type well 2 and the N-type diffusion layer 10 provided in the P-type silicon substrate 1 in alignment with the field oxide film 7 that divides the region and the gate electrode 8 provided on the element formation region. And an interlayer insulating film 11 provided on the surface including the gate electrode 8 and a power supply provided by being connected to each of the P-type diffusion layer 9 and the N-type diffusion layer 10 through a contact hole provided in the interlayer insulating film 11. The wiring 15, the GND wiring 16, and the signal wiring 12 are provided.

[0003]

In this conventional semiconductor integrated circuit, the power supply wiring and the GND wiring are mixedly formed on the same wiring layer as the general signal wiring.

At present, due to the complexity and scale of the structure of microcomputers and the like, the area occupied by the wiring connecting elements to each other and the power supply wiring for supplying power to the elements and the GND wiring is larger than the size of the transistor element itself. The area of the chip is determined, which is a bottleneck in improving the degree of integration. As a measure against this, by making the wiring layer multilayer,
A method of reducing the load per layer is generally adopted. In this method, however, as the wiring layer becomes the upper layer, the connection to the lower diffusion layer / gate electrode becomes more difficult.
In addition, the contact area required for connection becomes large, so that there is a problem in that the degree of integration cannot always be improved.

[0005]

According to another aspect of the present invention, there is provided a semiconductor integrated circuit including a first well of opposite conductivity type provided on one main surface of a semiconductor substrate of one conductivity type, the first well and the first well other than the first well. A wiring for power supply or GND provided on each of the regions, and a semiconductor layer of one conductivity type provided on the surface including the wiring,
The wiring provided in the one conductivity type semiconductor layer in alignment with the first well and provided on the first well is electrically separated from the wiring provided on a region other than the first well. A second well of opposite conductivity type and a MOS transistor provided in each of the second well and the one conductivity type semiconductor layer and connected to the wiring embedded in the respective regions are provided.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

1A and 1B are a sectional view and a cutaway perspective view for explaining a first embodiment of the present invention.

As shown in FIG. 1A, first, an N-type well 2 is formed by ion-implanting N-type impurities into one main surface of a P-type silicon substrate. Next, a metal layer such as aluminum or tungsten is deposited on the surface including the N-type well 2 and patterned by using the photolithography technique to form the power supply wiring 3 and the GND wiring 4. After forming the PSG film 5 on the surface including the wirings 3 and 4, the PSG film 5 is buried between the wirings 3 and 4 by polishing until the wirings 3 and 4 are exposed, and the P-type silicon layer 6 is formed thereon. It is grown by the epitaxial method. Next, the N-type well 2a is formed in the P-type silicon layer 6 in alignment with the N-type well 2 to form the power supply wiring 3 and the GN.
The D wiring 4 is electrically separated. Next, the N-type well 2a
The surface of the P-type silicon layer 6 containing P is selectively oxidized to form a field oxide film 7 for partitioning the element formation region, and the N-type well 2 is aligned with the gate electrode 8 provided on the element formation region.
A P-type diffusion layer 9 is formed in a, and an N-type diffusion layer 10 is formed in the P-type silicon layer 6 in a region other than the N-type well 2a.
Here, a diffusion layer selectively reaching the wirings 3 and 4 is deeply formed in each of the P-type diffusion layer 9 and the N-type diffusion layer 10 to connect the wiring 3 and the P-type diffusion layer 9 to each other. It is connected to the N-type diffusion layer 10. Next, an interlayer insulating film 11 is deposited on the surface including the gate electrode 8 to form a contact hole, and P
Signal wiring 1 connected to the type diffusion layer 9 and the N type diffusion layer 10
Form 2.

As shown in FIG. 1B, the power supply wiring 3 and the GND wiring 4 are arranged such that the P-channel transistor region and the N-channel transistor region formed on the semiconductor substrate are separated from each other. Each transistor group is arranged so that potentials from the power supply terminal 20 and the GND terminal 21 can be supplied to the group without crossing each other. In this state, if the power supply wiring 3 and the GND wiring 4 buried under the diffusion layer described above are connected to the diffusion layer of each transistor, the power supply to each transistor or the GND
Since the potential can be supplied from directly below the diffusion layer, the signal wiring can be freely arranged on the diffusion layer, and the contact area for the signal line to cross the power supply wiring or the 062 line is not required. There is an advantage that the chip size can be reduced more than the area corresponding to the area occupied by the power supply wiring 3 and the GND wiring 4.

FIG. 2 is a sectional view for explaining the second embodiment of the present invention.

As shown in FIG. 2, the N-type well 2 is formed on one main surface of the P-type silicon substrate 1 by the same process as in the first embodiment, and the power supply wiring 3 is formed on the N-type well 2. And the GND wiring 4 is formed in the regions other than the N-type well 2. Next, a P-type silicon layer 6 is formed on the surface including the wirings 3 and 4 to form an N-type well 2a matching the N-type well 2, and the wiring 3 and the wiring 4 are electrically separated. Then the first
The P-type diffusion layer 9 is aligned with the gate electrode 8 in the same manner as in the above embodiment.
And the N-type diffusion layer 10 is formed. Next, an interlayer insulating film 11 is deposited on the surface including the gate electrode 8 to form contact holes for the P-type diffusion layer 9 and the N-type diffusion layer 10, the wiring 3,
4 are formed, and a metal layer of aluminum or the like is deposited on the surface including these contact holes and patterned to connect the signal wiring 12 and the wiring 3 and the wiring 13 and the wiring 4 to each other. And N-type diffusion layer 1
Each of the wirings 14 for connecting to 0 is formed.

Here, electrical isolation between the wiring 3 and the wiring 4 is realized only by the PN junction surface of the N-type wells 2 and 2a.
The process can be simplified, and the wirings 3, 4 and the diffusion layers 9, 10 can be simplified.
Since it is connected with a metal wiring, there is an advantage that a low resistance connection can be made.

[0013]

As described above, according to the present invention, the wiring layer which is emitted from the power supply terminal and is included in the N-type well region and buried under the diffusion layer is included in the P-type substrate region which is emitted from the GND terminal. By having the wiring layer buried under the diffusion layer, the chip size corresponding to the region occupied by the power supply line and the GND line and the region where the signal line straddles the power supply line or the GND line can be reduced.

Further, since the power supply wiring and the GND wiring which are electrically connected to the substrate and the well directly with low resistance are provided over the entire surface of the chip, the power supply and the GND potential can be stabilized, and latch-up and the like can be achieved. It has an effect that it is difficult to occur.

[Brief description of drawings]

FIG. 1 is a sectional view and a cutaway perspective view for explaining a first embodiment of the present invention.

FIG. 2 is a sectional view for explaining a second embodiment of the present invention.

FIG. 3 is a sectional view for explaining a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 P-type silicon substrate 2, 2a N-type well 3, 4, 12, 13, 14, 15, 15, 16 Wiring 5 PSG film 6 P-type silicon layer 7 Field oxide film 8 Gate electrode 9 P-type diffusion layer 10 N-type diffusion layer 11 Interlayer insulation film

Claims (2)

[Claims] 1. A first well of opposite conductivity type provided on one main surface of a one conductivity type semiconductor substrate, and a power supply or GN provided on each of the first well and a region other than the first well.
Wiring for D, semiconductor layer of one conductivity type provided on the surface including the wiring, wiring provided in the semiconductor layer of one conductivity type aligned with the first well and provided on the first well A second well of opposite conductivity type that electrically separates a wiring provided on a region other than the first well, and the second well and the one conductivity type semiconductor layer, and Connected to the wiring embedded in the region
A semiconductor integrated circuit having a transistor. 2. The semiconductor integrated circuit according to claim 1, wherein the wiring is a metal layer of aluminum, tungsten or the like.