JPH05121404A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To evenly deposit a metal film in a fine interlayer connection hole in a semiconductor device having a multilayer wiring structure. CONSTITUTION:The first conductive layer 5 and an insulating film 6 are farmed an interlayer insulating film 4 and then an interlayer connecting hole 8 is formed by selectively removing them. Then, the second conductive film 7 is applied and selectively removed so as to form only the second conductive film 7 on the internal wall of the interlayer connecting hole 8. Further, using the insulating film 6 as a mask, a plating film 9 is formed only in the interlayer connecting hole 8 by applying plating-current through the first and second conductive films. As a result, a metal film is buried in the fine interlayer connecting hole 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming multi-layer wiring.

[0002]

2. Description of the Related Art In recent semiconductor devices, the thickness of an interlayer insulating film has to be fixed because the opening dimension of an interlayer connecting hole is reduced with the miniaturization of a device accompanying high integration.
The ratio between the depth of the interlayer connection hole and the opening size becomes large. In such an interlayer connection hole, it is difficult to uniformly deposit a metal film in the hole, which is an obstacle to miniaturization of multilayer wiring.

As a countermeasure, various methods of burying interlayer connection holes have been proposed.

For example, as a method for improving and developing a manufacturing apparatus, IEEE IEDM No. 9.5, 1987,
Tungsten CVD method described in J. Ele
ctrochem. Soc. Vol. 123, No,
6, the bias sputtering method and the like.
Further, as a semiconductor device improvement, there is a method of reducing the ratio between the depth of the interlayer connection hole and the opening size by tapering the shape of the interlayer connection hole.

[0005]

These conventional forming methods rely on manufacturing equipment. Therefore, it is necessary to newly develop and introduce the device in order to apply it to settlement. or,
In the method of reducing the depth-to-opening ratio of the interlayer connection hole by tapering the shape of the interlayer connection hole, there is a limit to miniaturization of the interlayer connection hole, which is an obstacle to high integration of the semiconductor device.

[0006]

The semiconductor device of the present invention comprises:
First step of forming a first wiring pattern on a semiconductor substrate, and then sequentially forming an interlayer insulating film, a first conductive film, and an insulating film; and forming an opening on the first wiring pattern. Then, a step of depositing a second conductive film and leaving the second conductive film only on the side surface of the opening by anisotropic etching, and then using the insulating film as a mask, The method further includes the step of selectively forming an electrolytic plated film in the opening of the interlayer insulating film, using the conductive film and the second conductive film as a plating current path.

[0007]

The present invention will be described below with reference to the drawings.

1 to 6 are process sectional views showing a first embodiment of the present invention.

FIG. 1: A wiring pattern composed of an aluminum film 2 and a titanium film 3 is formed on a semiconductor substrate 1 covered with a silicon oxide film. The formation method here is that a wiring pattern is formed by depositing an aluminum film 2 having a thickness of 0.5 μm and a titanium film 3 having a thickness of 0.2 μm by a normal sputtering technique and selectively etching by a lithography technique. It Next, an oxide film 4 which is an interlayer insulating film is deposited and formed by the CVD method.

Subsequently, the titanium film 5 (first conductive film) is formed with a thickness of 0.
The entire surface is deposited to a thickness of 2 μm by the sputtering method. Then, the oxide film 6 (insulating film) is formed to a thickness of 0.2 μm by the CVD method.
To the thickness of.

FIG. 2: Next, using the photoresist pattern (not shown) as a mask, the oxide film 6, the titanium film 5, and the oxide film 4 are sequentially removed by etching to form an opening 8.

FIG. 3: After removing the photoresist pattern, a titanium film 7 (second conductive film) is formed on the entire surface to a thickness of 0.2 μm.

Next, anisotropic etching is performed to leave the titanium film 7 (second conductive film) only on the inner wall of the opening 8. As a result, the titanium film 3 and the titanium film 5 are electrically connected via the titanium film 7.

FIG. 4: Next, using the titanium film 3, the titanium film 5, and the titanium film 7 as a plating current path and the oxide film 6 as a mask,
A gold plating film 9 is selectively formed in the opening 8. The plating current is supplied to the titanium film 5 from the back surface of the semiconductor substrate through the portion penetrating the semiconductor substrate. The thickness of the gold plating film 9 is set so that the opening 8 is buried. The opening 8 is filled with a gold plating film 9 in order to grow isotropically as a characteristic of the plating film. FIG. 5: Subsequently, the oxide film 6 is entirely removed by Freon-based plasma etching. Further, the exposed titanium film 5 is similarly removed.

FIG. 6: Next, a multilayer wiring is formed by forming an aluminum wiring pattern 10 which is an upper layer film.

Next, a second embodiment of the present invention will be described. 7 to 8 are process cross-sectional views showing the second embodiment of the present invention.

FIG. 7 is a sectional view when the oxide film 6 (insulating film) is selectively removed after the filling of the opening 8 according to the above-described embodiment is completed. This is because the resist pattern 11 is formed along the upper wiring pattern formation region, and the oxide film 6 (insulating film) is selectively removed by Freon-based plasma etching using the resist pattern 11 as a mask to remove the titanium film 5. Part of the (first conductive film) is exposed. Next, as shown in FIG. 8, the resist pattern 11 is removed, the titanium film 5 (first conductive film) is used as a plating current path, and the oxide film 6 (insulating film) is used as a mask to expose the exposed titanium. On the film 5, a gold-plated film 12 to be an upper wiring pattern is selectively formed.

In this embodiment, since the upper wiring pattern is formed in a self-aligning manner, the dimensional alignment margin can be reduced, which is effective for miniaturization.

[0019]

As described above, according to the present invention, it is possible to embed a conductive film in an interlayer connection hole provided at an arbitrary position without newly developing and introducing a manufacturing apparatus. A semiconductor device having an interlayer connection hole can be realized.

[Brief description of drawings]

FIG. 1 is a process sectional view of a first embodiment of the present invention.

FIG. 2 is a process sectional view of the first embodiment of the present invention.

FIG. 3 is a process sectional view of the first embodiment of the present invention.

FIG. 4 is a process sectional view of the first embodiment of the present invention.

FIG. 5 is a process sectional view of the first embodiment of the present invention.

FIG. 6 is a process sectional view of the first embodiment of the present invention.

FIG. 7 is a process sectional view of a second embodiment of the present invention.

FIG. 8 is a process sectional view of a second embodiment of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 aluminum film 3 titanium film 4 oxide film (interlayer insulating film) 5 titanium film (first conductive film) 6 oxide film (insulating film) 7 titanium film (second conductive film) 8 opening 9 gold plating film 10 Aluminum wiring film 11 Resist pattern 12 Gold plating film

Claims (2)

[Claims] 1. A step of forming a first wiring pattern on a semiconductor substrate and then sequentially forming an interlayer insulating film, a first conductive film, and an insulating film, and an opening portion on the first wiring pattern. And then depositing a second conductive film and leaving the second conductive film only on the side surface of the opening by anisotropic etching, and then using the insulating film as a mask. 1
2. A method of manufacturing a semiconductor device, comprising the step of selectively forming an electrolytic plated film in the opening of the interlayer insulating film by using the conductive film and the second conductive film as a plating current path. 2. A second wiring pattern, which is connected to the first wiring pattern through the electrolytic plating film in the opening, is formed on the interlayer insulating film after removing the first conductive film and the insulating film. The method for manufacturing a semiconductor device according to claim 1, further comprising: