JPH05120378A - Method for predictive wiring length calculation of integrated circuit - Google Patents

Abstract

PURPOSE:To improve the precision by adding a constant term, a term obtained by multiplying the half peripheral length of the area of a group that the block of a network belongs to by a constant, and a term obtained by multiplying a value obtained by raising the half peripheral length to 0.5th power by a fan- out minus one and a constant. CONSTITUTION:Predictive wiring length brought under the consideration of the area size (half peripheral length) of the group that the block connected to the network belongs to can be calculated by using L=A+BXH+ CXH<0.5>X(f-1), where L is the predictive wiring length of the network, A, B, and C constants determined by a chip, H the half peripheral length of the area of the group that the block connected to the network belongs to, and f the fan-out of the network. Here, the straight line of a graph varies as the half peripheral length of the group area varies. Namely, the predictive wiring length 13 of the network in a group 9 is short and the predictive wiring length 14 of the network in a group 10 is long, thereby obtaining the predictive wiring length corresponding to the half peripheral length of the group area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for calculating a predicted wiring length of an integrated circuit, and more particularly to a method for calculating a predicted wiring length of a large scale integrated circuit.

[0002]

2. Description of the Related Art Conventionally, in the method of calculating the predicted wiring length of an integrated circuit of this type, the predicted wiring length of a net is calculated by using the first equation while the wiring length per fanout of the net is uniform. .

L = α + β × f ## EQU1 ## Here, L is the predicted wiring length of the net, α and β are constants determined by the semiconductor substrate (hereinafter referred to as a chip), and f is the fanout number of the net. .

FIG. 2 shows an example of a change in the predicted wiring length of the net calculated by using the first equation according to the fanout number.
When the predicted wiring length of a net is calculated using the conventional predicted wiring length calculation method, the predicted wiring length of a net is uniform on the same chip due to the fanout number.

FIG. 3 is a layout diagram after arrangement on the chip and wiring. The blocks arranged in the chip 7 are connected by wiring. Further, there are several groups in the chip 7, and blocks belonging to the same group are arranged close to each other so as to fit within the group area. The net 11 is connected only to blocks belonging to the group 9 having a small area, and the net 12 is connected only to blocks belonging to the group 10 having a large area. In the conventional method of calculating the predicted wiring length, the net 11 and the net 12 both have the same fan-out number of 2, so that the predicted wiring length is also the same. However, since the size of the area of group 9 is much smaller than that of group 10, the net 11
There is a high possibility that the wiring length will be much shorter than that of the net 12. Therefore, the net 11 must have a shorter predicted wiring length than the net 12. As described above, the conventional predicted wiring length calculation method cannot perform highly accurate predicted wiring length calculation.

[0006]

In the above-mentioned conventional method of calculating the predicted wiring length, the predicted wiring length of the net is calculated uniformly by the fanout number. In this case, if the net having a short wiring length and the net having a long wiring length have the same fan-out number, the predicted wiring length will be the same, and it is not possible to perform highly accurate predicted wiring length calculation.

[0007]

According to the method of calculating a predicted wiring length of an integrated circuit of the present invention, a predicted wiring length of an integrated circuit is calculated before a wiring pattern of the integrated circuit is formed by computer processing. In the method, a constant term, a term obtained by multiplying the half circumference of the area of the group to which the block connected to the net belongs by a constant, and the half circumference of the term to the power of 0.5 "the fan-out number of the net-1" and a constant The value obtained by adding the terms multiplied by is the predicted wiring length.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a flow chart showing the outline of a system using the predicted wiring length calculation method of the present invention. As shown in FIG. 1, the flow of the system using such a predicted wiring length calculation method includes a processing step 1 for grouping blocks based on block group information 4 and a processing step 1 based on block size information 5. It is composed of a processing step 2 for calculating the half circumference of the created group area and a processing step 3 for calculating the predicted wiring length of the net using the group area half circumference calculated in the processing step 2.

The second formula is a predicted wiring length calculation formula used in the predicted wiring length calculation method of the present invention.

L = A + B × H + C × H ^0.5 × (f−1) (2) Here, L is the predicted wiring length of the net, A, B and C are constants determined by the chip, and H is connected to the net. Is the half circumference of the area of the group to which this block belongs, and f is the number of fan-outs of the net.

By using the second equation, it is possible to calculate the predicted wiring length in consideration of the area size (half circumference) of the group to which the block connected to the net belongs.

FIG. 4 shows an example of a change in the predicted wiring length of the net calculated by using the second equation according to the fanout number.
The straight line of the graph changes as the half circumference of the group area changes. The predicted wiring length 13 of the net in the group 9 in FIG. 3 is short, and the predicted wiring length 14 of the net in the group 10 is long, so that the predicted wiring length corresponding to the half circumference of the group area can be obtained.

FIG. 5 is a flow chart of a delay time simulation system using the predictive wiring length calculation method of the present invention.
It is composed of a processing step 15 for calculating a predicted wiring length of a net, and a processing step 16 for performing a delay time simulation using the predicted wiring length calculated in the processing step 15. By using the predicted wiring length calculation method of the present invention in a delay time simulation system, a highly accurate delay time simulation can be performed.

FIG. 6 is a flow chart of a logic synthesis system using the predicted wiring length calculation method of the present invention. It is composed of a processing step 17 for performing logic synthesis, and a processing step 18 for calculating a predicted wiring length of a net in parallel therewith. By using the predicted wiring length calculation method of the present invention in a logic synthesis system, more optimal logic synthesis can be performed.

[0016]

As described above, the method for calculating the predicted wiring length of an integrated circuit according to the present invention calculates the predicted wiring length of a net before forming a wiring pattern by computer processing.
A constant term, a term obtained by multiplying the half perimeter of the area of the group to which the block connected to the net belongs by a constant, and the half perimeter to the power of 0.5 were multiplied by the "net fanout number-1" and a constant. By setting the value obtained by adding the terms as the predicted wiring length, it is possible to perform highly accurate predicted wiring length calculation.

[Brief description of drawings]

FIG. 1 is a flowchart based on the basic idea of the present invention.

FIG. 2 is a diagram showing a change according to a predicted wiring length fanout number by a conventional predicted wiring length calculation method.

FIG. 3 is a layout diagram on a chip.

FIG. 4 is a diagram showing changes in the predicted wiring length according to the fanout number according to the predicted wiring length calculation method of the present invention.

FIG. 5 is a flowchart of a delay time simulation system using the predicted wiring length calculation method of the present invention.

FIG. 6 is a flow chart of a logic synthesis system using the predicted wiring length calculation method of the present invention.

[Explanation of symbols]

 1 block grouping processing 2 group area half circumference calculation processing 3 net predicted wiring length calculation processing 4 block group information file 5 block size information file 6 net predicted wiring length 7 chips 8 blocks 9,10 groups 11, 12 nets 13 Predicted wiring length of nets in group 9 14 Predicted wiring length of nets in group 10 15 Predicted wiring length calculation processing for nets 16 Delay time simulation processing 17 Logic synthesis processing 18 Predicted wiring length calculation processing for nets

Claims (1)

[Claims] 1. A constant term and a group to which a block connected to a net belongs in a predictive wiring length calculation method of an integrated circuit for calculating a predicted wiring length of a net before forming a wiring pattern of the integrated circuit by computer processing. The value obtained by adding the term obtained by multiplying the half circumference of the area of (1) by a constant and the term obtained by multiplying the half circumference by the power of 0.5 to the "net fanout number -1" and a constant is used as the predicted wiring length. A method for calculating the expected wiring length of a featured integrated circuit.