JPH05120212A - Use right reservation system for system bus - Google Patents

Abstract

PURPOSE:To perform the coincidence processing of a cache memory by temporarily reserving the right to use the system bus at a request from a device which can not follow up the performance of the system bus. CONSTITUTION:A bus use right reservation signal is newly supplied to the system bus 6. Further, the cache update control circuit 12 of a central processing unit 1 outputs the bus use right reservation signal to the system bus 6 when judging that the cache memory can not be updated following up the system bus performance. Consequently, a system controller 3 temporarily reserves the allocation of the system bus use right with the bus use right reservation signal. Consequently, a cache circuit 13 can performs the cache memory coincidence processing following up the system bus performance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system bus usage right reservation system, and more particularly to the use of a system bus for temporarily holding the system bus usage right grant at the request of a device that cannot follow the system bus performance. Regarding the rights reservation system.

[0002]

2. Description of the Related Art Conventionally, this type of information processing system is connected to a system bus capable of transmitting a bus use right request, a bus use permission, an address, a bus command, data, and a fault report signal, and the system bus. , Connected to the central processing unit for executing various processes and the system bus,
It consists of main memory and other devices.

In such an information processing system, system bus usage right allocation has been a method of suspending the usage right allocation until the completion of the instruction depending on the contents of the instruction execution on the system bus.

Therefore, due to the convenience of the device under the control of the system bus, the control of temporarily suspending the allocation of the system bus usage right has not been performed. Also, in order to avoid such a temporary hold, investment was made in hardware that could follow the system bus performance.

In recent years, even in small and medium-sized systems,
The demand for improved performance has increased significantly. In order to improve the system performance, a multi-CPU configuration is often adopted, and in order to prevent the decrease of the multi-coefficient, the system bus performance is also significantly improved.

On the other hand, the demand for such performance improvement extends to small and medium-sized systems as well, and in this case, there is also a demand for cost reduction and a demand for the cost of a single CPU as low as possible. Further, with respect to performance improvement, as in the case of higher-ranking models, there is a trend toward using multiple CPUs.

As described above, in the conventional technique, various measures have been taken in order to improve the performance.

[0008]

By the way, cache memory update control is one of the controls that is difficult to follow the performance improvement of the system bus as described above. In particular, it is necessary to reflect the memory update state of another device in the cache memory, and for this reason, the address stacker is often provided in accordance with the performance of the system bus. However, such an address stacker has a problem in that the hardware investment increases and the cost increases.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a system bus right-of-use reservation system capable of performing cache memory matching processing in accordance with system bus performance. ..

[0010]

In order to achieve the above-mentioned object, the system bus right-of-use reservation system according to the present invention includes a bus right-of-use request, a bus right-of-use permission, an address, a bus command, data, and a fault. From a system bus that can transmit a report signal, a central processing unit that is connected to the system bus and executes various processes, and a main storage device, a system control unit, and other devices that are connected to the system bus In the information processing system
Enables the bus to transmit a bus usage right hold signal that temporarily holds the grant of the bus usage right for the system bus usage right request, and allows the central processing unit to have the cache memory update performance follow the system bus performance. In case of failure, it is equipped with a cache update control circuit that outputs a bus use right hold signal to the system bus for temporarily holding the grant of the bus use right to the request for the right to use the system bus. System by signal
The feature is that the bus usage right allocation is temporarily suspended.

Here, the central processing unit has a bus control circuit for accessing and communicating with various devices, a cache memory, and a cache circuit for performing cache matching, reading, and updating, and other devices. Monitor the main memory update command on the system bus and
It is preferable that the stacker is configured with a cache update control circuit that determines the usage status of the stacker and outputs the bus usage right suspension signal because the update performance of the cache memory cannot follow the system bus performance before it becomes full.

Further, it is preferable that the system controller monitors whether or not the value of the bus use right hold signal is valid, and if the value is valid, temporarily suspends the assignment of the use right of the system bus.

According to the present invention, a bus use right request suspension signal is newly added to the signal group constituting the conventional system bus so that a large number of stages of the address stacker for updating the cache memory are not required. The assignment of the system bus usage right can be controlled by the bus usage right holding signal according to the usage status of the address stacker.

[0014]

The present invention will now be described with reference to the illustrated embodiments.

FIG. 1 is a block diagram of a system for realizing an embodiment of a system bus usage right reservation system according to the present invention.

The system bus usage right reservation system shown in FIG. 1 includes a central processing unit (CPU) 1, a main memory unit (MMU) 2, a system control unit (SCU) 3, and a maintenance unit (SVP) 4. And an input / output control unit (IOP) 5
And the system bus 6. In this embodiment, C
Although only one PU1 and one IOP5 are displayed, there may be a plurality of PU1 and IOP5.

Here, the CPU 1 is the system of the present invention.
It is a partial component of an embodiment of a bus use right reservation system. The MMU 2 stores various data. SCU3
Performs arbitration control in response to a bus use request from each device. The IOP 5 controls an input / output device (not shown) connected to the lower level. The system bus 6 is a bus right request,
It can transmit bus use permission, address, bus command, data, fault report signal, and bus use right hold signal.

The CPU 1 includes a bus control circuit 11, a cache update control circuit 12, a cache circuit 13, and an arithmetic circuit 1.
4. It has a micro-sequence circuit 15. The arithmetic circuit 14 receives the bus control circuit 11 via the internal bus 16.
, Cache circuit 13, and micro-sequence circuit 1
5 is connected to. The bus control circuit 11 controls the system bus 6 for MM access and inter-processor communication. The cache update control circuit 12 monitors and detects a main memory update instruction from another device on the system bus 6, and controls the reset of the cache registration valid bit by detecting a cache match. Cache circuit 1
Reference numeral 3 has a cache memory, and performs cache coincidence reference, read, and update. The arithmetic circuit 14 performs various arithmetic operations. The micro sequence circuit 15 controls the entire CPU 1 via the internal bus 16.

The operation of the system thus configured will be described with reference to FIG.

Generally, the cache memory update process accompanying the update of the main memory of another device is a cache match process which is a reference process of whether the content of the main memory update address is registered in the cache memory, and a cache memory registration valid bit. Two timings, the update process and the reset process, are required.

On the other hand, as a result of the improved performance of the system bus 6, the main memory can be updated at one timing interval, and the more devices under the system bus, the more
There are more opportunities to update the main memory at timing intervals.

It is not practical to have an address stacker for updating the cache memory that follows all the memory updating opportunities in this one timing interval in terms of cost and realization on hardware.

Therefore, the CPU 1 has the bus use right request hold signal (IHT) 20 newly added to the system bus 6.
For 0, as a result of the use status of the address stacker in the cache update control circuit 12, the IHT 200
Make a request to validate.

The SCU 3 temporarily suspends the allocation of the right to use the system bus 6 if the value of the IHT 200 is valid,
The cache memory matching process is executed according to the value shown in the address stacker.

The cache update control circuit 12 uses the IHT2
As a result of the cache memory matching process when 00 is valid, the IHT 20
Lowering the request to 0, SCU3 grants the pending system bus entitlement request.

[0026]

As described above, according to the present invention, a bus use right suspension signal is newly added to the conventional system bus, and the update of the cache memory cannot be processed following the system bus performance. In this case, by enabling the bus usage right hold signal to temporarily hold the allocation of the system bus usage right, it is possible to perform cache memory matching processing by following the system bus performance. is there.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1 CPU (Central Processing Unit) 2 MMU (Main Memory) 3 SCU (Input / Output Control Unit) 4 SVP (Maintenance Unit) 5 IOP (Input / Output Control Unit) 11 Bus Control Circuit 12 Cache Update Control Circuit 13 Cache Circuit 14 Arithmetic Circuit 15 Micro sequence circuit 16 Internal bus

Claims (3)

[Claims] 1. A system bus capable of transmitting a bus use right request, a bus use permission, an address, a bus command, data, and a fault report signal, and a system bus connected to the system bus,
A central processing unit that executes various processes, and the system
In an information processing system including a main storage device, a system control device, and other devices connected to a bus, the system bus is a bus usage right for temporarily suspending grant of a bus usage permission for a system bus usage right request. The central processing unit makes it possible to transmit a hold signal, and the central processing unit temporarily holds the grant of the bus use permission to the request for the use right of the system bus when the update performance of the cache memory cannot follow the system bus performance. A cache update control circuit for outputting a signal to the system bus, wherein the system control device is configured to temporarily suspend the assignment of the usage right of the system bus by the bus usage right suspension signal. Bus right reservation system. 2. The central processing unit has a bus control circuit for accessing and communicating with various devices and a cache memory, and a cache circuit for performing cache matching, reading, and updating, and other devices. The main memory update command is monitored on the system bus, the usage status of the address stacker is determined, and the cache memory update performance cannot follow the system bus performance before it becomes full. 2. The system bus usage right holding system according to claim 1, further comprising a cache update control circuit which outputs a usage right holding signal. 3. The system control device is configured to monitor whether or not the value of the bus use right hold signal is valid, and if it is valid, temporarily hold the use right assignment of the system bus. A system bus right-of-use reservation system according to item 1.