JPH0512012A - Interruption control system for delay branch - Google Patents

Abstract

PURPOSE:To simplify an interruption handling in the same manner as the interruption handling of a computer which is not provided with a delay branching mechanism. CONSTITUTION:The compter provided with the delay branching mechanism to execute a delay instruction following a branching instruction to branch a program is provided with a means which detects the current instruction as a delay branching instruction (2) and stores it. When the delay branching instruction (2) is detected by this detecting and storage means, an interruption (3) detected at the time of the end of the delay branching instruction (2) is held till the end of execution of a next delay instruction (4) and is executed at the time of the end of the delay instruction (4).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control system for a computer having a delay branch mechanism. With the recent demand for high-speed branch processing in computer systems, a delayed branch mechanism is becoming common.

FIG. 4 is a diagram for explaining a difference between a normal branch and a delayed branch. (A) schematically shows the operation of the normal branch, and (b) schematically shows the operation of the delayed branch. Shows. The delay branch mechanism is a mechanism that prevents the pipeline from being disturbed by a branch instruction.

Normally, if instruction fetch / decode and execution are pipelined, when a branch instruction is executed, the address of the next instruction to be executed is not fixed until the execution is completed. Therefore, fetching and decoding of the next instruction can be performed only after the execution of the current branch instruction is completed and the branch address is determined. {See Fig. 4 (a)} Then, in the delayed branch,
As shown in FIG. 4 (b), in parallel with the execution of the delayed branch instruction, the instruction next to the delayed branch instruction (which is called a delayed instruction) is fetched and decoded, and the delayed branch instruction is executed. After completion, the delay branch mechanism is a mechanism for fetching / decoding the branch destination instruction at the branch address m in parallel with the execution of the delay instruction.

In a computer having such a delay branch mechanism, if an external interrupt occurs during execution of the delay branch instruction, there is a problem that the interrupt processing becomes complicated. Therefore, the interrupt processing is provided with the delay branch mechanism. There is a need for an interrupt control method that can be as simple as a computer that does not.

[0005]

2. Description of the Related Art FIGS. 5 and 6 are diagrams for explaining a conventional interrupt control system, and FIG. 5 shows a conventional interrupt processing system when an external interrupt occurs immediately after execution of a delayed branch instruction. FIG. 6 shows another conventional interrupt processing method when an external interrupt occurs immediately after execution of a delayed branch instruction.

In the interrupt processing routine shown in FIG. 5, (1) the next instruction address (n + 1) and the next instruction address (= branch destination address m) are saved.

(2) The interrupt processing body is executed. (3) Restore the next instruction address (n + 1) to the next address (n + 1)
Executes the delay instruction of singly.

(3) The instruction (branch destination instruction) address (m) is restored one after another, and the operation returns to the address. The above processing is performed.

However, in this processing method, as shown in FIG. 5, it is necessary to save two instruction addresses (address n + 1 and address m) for return, which causes an increase in the amount of hardware. There is. In addition, it is necessary to devise to execute the delay instruction at the next address (n + 1) independently before returning from the interrupt processing.

FIG. 6 shows another interrupt processing method when an external interrupt occurs immediately after the execution of a branch instruction. That is, in the interrupt processing routine in this case, (1) the next instruction address (n + 1) and the fact that an external interrupt has occurred immediately after the execution of the branch instruction (set as the B flag) are saved.

(2) The main body of interrupt processing is executed. (3) Restore the next instruction address (n + 1) to the next address (n + 1)
Executes the delay instruction of singly.

(4) If the B flag is off, the program returns to the address (n + 2), but if the B flag is on, the delayed branch instruction at the address n is read. The branch destination address (m) is calculated. Return to instruction address (m) one after another The above processing is performed.

However, even in this processing method, it is necessary to independently execute the delayed instruction at the next address (n + 1) before the return from the interrupt processing. Furthermore, an external interrupt is generated immediately after the execution of the branch instruction. When the effect (B flag) is "ON", it is necessary to read the branch instruction at address n and calculate the branch destination address in the interrupt processing routine.

[0014]

Therefore, according to the conventional interrupt processing method, the following are required: -Remember a plurality of return addresses, or a flag indicating an interrupt immediately after a delayed branch instruction (the above-mentioned B flag).
Need to remember. -Before returning from interrupt processing, it is necessary to devise to execute the delayed instruction at the next address (n + 1) independently. -In the interrupt processing routine, it is necessary to read the delayed branch instruction and calculate the branch destination address (m). That is, there is a drawback that the interrupt processing routine becomes complicated.

In view of the above-mentioned conventional drawbacks, the present invention provides a computer equipped with a delay branch mechanism for executing and branching a delay instruction subsequent to a delay branch instruction without complicating external interrupt processing in the delay branch. An object of the present invention is to provide an interrupt control method in a delay branch that can be simplified similarly to the interrupt processing of a computer that does not have a delay branch mechanism.

[0016]

FIG. 1 illustrates the principle of the present invention. The above problem is solved by the delay branch interrupt control system configured as follows.

In a computer equipped with a delay branch mechanism for executing a delayed instruction next to a branch instruction and branching, a means (9) for detecting and storing the current instruction as a delayed branch instruction is provided, and the detection is performed. When the memory means 9 detects a delayed branch instruction, the interrupt detected at the end point (T1) of the delayed branch instruction is suppressed until the execution end point (T2) of the next delayed instruction Control to interrupt at the end point (T2).

[0018]

That is, in the interrupt control method in the delay branch of the present invention, a mechanism that does not accept an external interrupt during execution of a delayed branch instruction, specifically, does not accept an interrupt at the end point T1 of the delayed branch instruction. By providing a mechanism for accepting the external interrupt at the end time T2 of the next delay instruction, the interrupt processing can be started at the time T2 when the execution of the delay branch instruction and the delay instruction is completed. As a result, the interrupt processing is as follows: (1) Next instruction address (address of branch destination instruction at address m)
To save.

(2) The main body of interrupt processing is executed. (3) Restore the next instruction address (m) and return to address m. The process is simplified.

Such an interrupt process is equivalent to the interrupt process in an ordinary computer that does not have the delay branch mechanism, and has the effect of simplifying the interrupt process.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. The above-mentioned FIG. 1 is a diagram for explaining the principle of the present invention.
FIG. 3 is a diagram showing an embodiment of the present invention, FIG. 2 shows a configuration example, and FIG. 3 shows an operation time chart.

According to the present invention, in a computer having a delay branch mechanism for executing and branching a delay instruction next to a branch instruction, means 9 for detecting and storing the current instruction as a delayed branch instruction is provided. Is provided with the detection / storage means, 9
When a delayed branch instruction is detected, a means for suppressing the interrupt detected at the end point (T1) of the delayed branch instruction until the execution end point (T2) of the next delayed instruction is to implement the present invention. It is a necessary means. The same reference numerals denote the same objects throughout the drawings.

The operation of the interrupt control system in the delay branch according to the present invention will be described below with reference to FIG. 2 while referring to FIG. First, in the present embodiment, for simplicity, a two-stage pipeline of instruction fetch / decode and execution is assumed.

In FIG. 2, reference numeral 1 is a memory, which stores instructions and data. 2 is a central processing unit (hereinafter referred to as CPU). 3 is a memory bus, and the above memory 1 and CPU 2
Used to transfer instructions and data between The CPU 2 fetches an instruction from the memory 1 and decodes it, an instruction fetch & decode unit 4, an instruction execution unit 5 that executes each instruction according to the instruction decoding result, and an external interrupt (E
Interrupt processing unit 6 that determines whether or not (XINT) can be accepted
Composed of and. Reference numeral 7 is the external interrupt request signal (EXINT) to the CPU 2. Reference numeral 8 is a control signal (DCBRN) indicating that the next instruction to be executed is a delayed branch instruction (the branch instruction is in the fetch / decode cycle). From the instruction fetch & decode unit 4 to the interrupt processing unit It is output to 6, and becomes "off" at the time when the fetch / decode cycle of the delayed branch instruction is completed.

A latch (EXBRN) 9 is a control flag (B) indicating that a delayed branch instruction is being executed (the delayed branch instruction is in an execution cycle), and while the flag (B) is "on", the external Interrupt request signal (EXINT) 7 is ignored.

In the interrupt processing unit 6, the external interrupt request {that is, the external interrupt request signal (EXINT) 7 is "ON"} and the control flag (B) 9 is "OFF". At the time T1 when the execution of the delayed branch instruction is completed, a signal (INT) indicating that this request can be accepted is output to the instruction execution unit 5.

Therefore, the external interrupt request signal (EXINT)
7 is sent to the instruction execution unit 5 at the time T2 when the execution of the next delay instruction is completed, and operates so as to start the actual interrupt processing.

An operation time chart at this time is shown in FIG. As is clear from this figure, the external interrupt request signal (EXINT) 7 turns on in cycle 3, but since the branch instruction is being executed (latch (EXBRN) 9 above is on) in this cycle, The interrupt request is not accepted and the instruction execution unit 5 is notified of the interrupt in the next cycle 4.

Therefore, as described above, the interrupt processing is as follows: (1) Next instruction address (address of branch destination instruction at address m)
To save. (2) Execute the interrupt processing body.

(3) Restore the next instruction address (m),
Return to address m. Processing is enough. in this way,
In the present invention, in a computer having a delay branch mechanism for executing and branching a delay instruction next to a delay branch instruction, means for detecting that the current instruction is a delay branch instruction and storing the means, 9 is provided. , When the delay branch instruction is detected by the detecting / storing means 9, the external interrupt (EXINT) detected at the end point (T1) of the delay branch instruction until the execution end point (T2) of the next delay instruction The feature is that it was deterred.

[0031]

As described above in detail, in the interrupt control system by delay branching of the present invention, the current instruction is executed in the computer having the delay branching mechanism for executing the branching instruction next to the delaying branching instruction and branching it. Is provided as a delayed branch instruction, and means for storing the same is provided, and when the delayed branch instruction is detected by the detecting / storing means, the interrupt detected at the end point (T1) of the delayed branch instruction is The execution of the delay instruction is stopped until the end time (T2) of the delay instruction, and the interrupt is executed at the end time (T2) of the delay instruction. There is an effect that the processing can be simplified to the same processing as the interrupt processing of a computer not provided.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention (No. 1).

FIG. 3 is a diagram showing an embodiment of the present invention (part 2).

FIG. 4 is a diagram explaining a difference between a normal branch and a delayed branch.

FIG. 5 is a diagram for explaining a conventional interrupt control system (No. 1)

FIG. 6 is a diagram for explaining a conventional interrupt control system (part 2).

[Explanation of symbols]

1 memory 2 central processing unit (CPU) 3 memory bus 4 instruction fetch & decode unit 5 instruction execution unit 6 interrupt processing unit 7 external interrupt request signal (EXINT) control signal (DCBRN) delayed branch instruction delayed instruction

Front page continuation (72) Inventor Kazuyasu Nonomura 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Toru Watanabe 1015, Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa

Claims (1)

Claim: What is claimed is: 1. A computer equipped with a delay branch mechanism for executing a delayed instruction next to a branch instruction to branch, and stores the current instruction as a delayed branch instruction (). Means to do
When the delayed branch instruction () is detected by the detecting / storing means (, 9) by providing (, 9), the interrupt () detected at the end of the delayed branch instruction () An interrupt control method in a delayed branch, which is characterized in that the execution is stopped until the end of execution of () and the interrupt is controlled at the end of the delayed instruction ().