JP2007188527A - Interruption processing method for information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interruption processing method capable of eliminating the occurrence of problem by a simple method when an interruption is accepted just after delay in a CPU of a pipeline system which processes an instruction with a delay slot. <P>SOLUTION: The interruption processing method has an instruction decoder 1 which decodes instructions and a flag register 2 which can be set by the instructions in the CPU which performs pipeline processing to a delay instruction with the delay slot and switches the interruption just after the delay instruction to valid or invalid by a state of the flag register 2. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an interrupt processing method in a pipeline type information processing apparatus that processes an instruction having a delay slot.

  In an information processing apparatus (hereinafter referred to as a CPU) such as a computer, single-step execution of instructions is performed for debugging work.

  In order to realize single step execution, a method in which the CPU supports a single step interrupt in hardware is generally used. This is realized by preparing an operation mode in which the CPU performs single-step execution, and generating an interrupt every time one instruction is executed in this mode.

  However, there are cases where it is not possible to interrupt each instruction, such as when a delay slot is provided and pipeline processing is performed. There are two possible solutions for this case.

  The first method is a means for providing support by hardware so as not to cause a contradiction even when an interrupt is inserted between a delay instruction and a delay slot, and to be able to return completely. That is, it is possible to execute from the instruction in the delay slot when returning. This method has no restrictions on the instructions to be programmed, and is ideal for debugging by single-step execution. However, an increase in hardware cost for realizing this function is inevitable, and in some cases the operating frequency is A decrease in power consumption and an increase in power consumption during operation are also conceivable.

  The second method is a method in which no interrupt is accepted immediately after the delay instruction. With this method, the hardware cost is also small, and only the delayed instruction does not become a single step. However, if the frequency of the delayed instruction is not high, it hardly becomes an obstacle to debugging.

  However, in the first method, the hardware cost becomes a problem as described above. Adoption is difficult in a system where cost is the most important, and there are also possible negative aspects such as a decrease in operating frequency and an increase in power consumption.

  In the second method, when the frequency of appearance of delayed instructions is high, there is a problem in debugging work. For example, if several delay instructions are consecutive, interrupts are prohibited during processing of the instruction group, and single-step execution cannot be performed. Therefore, the ease of debugging during that time is significantly reduced.

  The second method described above is also promising from the viewpoint of hardware cost, but the problem is that the single-step execution mode should be every instruction when delayed instructions appear continuously. Therefore, the information during the execution of several instructions is interrupted, and debugging is hindered.

  The present invention has been made in view of the above-described conventional problems, and in a pipelined CPU that processes an instruction having a delay slot, when an interrupt is received immediately after the delay, a problem occurs in a simple manner. Provide an interrupt handling method to eliminate.

  The interrupt processing method according to the present invention has at least one flag register that can be set by an instruction in an information processing apparatus that pipelines a delay instruction having a delay slot. It is characterized by switching the interrupt to enable or disable.

  According to the configuration described above, the programmer can be given a selection right by enabling the instruction to select whether to enable or disable the interrupt immediately after the delay instruction. Since the programmer can select either method according to his / her convenience, conditions that are advantageous to the programmer can always be prepared.

  Further, according to the present invention, there is provided a first delay instruction that disables the immediately following interrupt regardless of the state of the flag register, and a second that can switch enable / disable of the immediately following interrupt by a flag stored in the flag register. The delay instruction is preferably provided.

  According to the above configuration, there are two types of delay instructions: a delay instruction that can switch enable / disable of the immediately following interrupt by a flag and a delay instruction that disables the immediately following interrupt regardless of the state of the flag. . In other words, delay processing that imposes a significant hardware burden on the implementation of an interrupt immediately after delay, for example, a special register such as a delayed branch instruction has a special register because the branch destination address and return address are different. For such instructions, the immediately following interrupt acceptance is prohibited regardless of the flag state, and for the delayed instructions that do not incur a hardware cost, the immediately following interrupt can be enabled / disabled depending on the flag state. As a result, it becomes possible to perform single step execution even for a part of instructions that could not be executed in single step in the prior art without increasing the hardware, thereby improving the ease of debugging.

  Also, according to the interrupt processing method of the present invention, in an information processing apparatus that pipelines a delay instruction having a delay slot, a first delay instruction that unconditionally disables the immediately following interrupt, a delay instruction and a delay slot And a second delay instruction capable of switching between enabling and disabling of the immediately following interrupt according to the combination of the arranged instructions.

  According to the above configuration, since it is possible to automatically determine whether or not to permit interruption, it is not necessary to require knowledge and effort from the programmer. Further, even if a program has a possibility of occurrence of a hazard and a case in which no hazard is present, it is not necessary to uniformly disable interrupts, so that debugging accuracy is improved.

  Further, the present invention has a comparator for checking the coincidence of operands of two consecutive instructions in the pipeline stage, and reflects the result of the comparator to combine the delay instruction and the instruction arranged in the delay slot. Therefore, it is preferable to enable or disable the immediately following interrupt.

  According to the above configuration, the possibility of a hazard is checked at the operand level. Therefore, even in the case of a combination of a delayed instruction and a subsequent instruction that may cause a hazard, a hazard does not occur due to a mismatch of operands. In some cases, it is not necessary to prohibit the operation, so that the accuracy of debugging is further improved.

  As described above, according to the present invention, it is possible to give the programmer a selection right by enabling the instruction to select whether to enable or disable the interrupt immediately after the delay instruction. Since the programmer can select either method according to his / her convenience, conditions that are advantageous to the programmer can always be prepared.

  In addition, according to the present invention, a delay instruction that imposes a significant hardware burden on the realization of an interrupt immediately after the delay is classified as prohibiting the acceptance of the interrupt immediately after the flag state, and does not incur a hardware cost. Instructions are classified as enabling / disabling the next interrupt depending on the flag status, so that even single-step instructions that could not be executed in a single step can be single-ended without increasing hardware. It becomes possible to perform step execution, and the ease of debugging can be improved.

   Embodiments of the present invention will be described below with reference to the drawings. FIG. 5 shows an operation timing chart of pipeline processing of a delayed instruction according to one embodiment of the present invention. Here, in order to simplify the explanation, a simple pipeline structure is used.

  This CPU has a three-stage pipeline structure of “fetch”, “execution”, and “memory access”. “Fetch” is a process of reading instructions in order from the memory storing the instructions. “Execution” is a step of performing processing such as calculation according to an instruction and storing the result in a desired register. “Memory access” is a process that exists only in an instruction that accesses a memory such as load or store. In the case of load, data is read from a desired address and stored in a desired register.

FIG. 5 shows the operation of each process when the following program is executed. Here, “instruction A” is a load instruction of “LD (mem), R1”, reads data at address (mem) on the memory, and stores it in register R1. “Instruction B” is an addition instruction of “ADD R1, R2”, adds the contents of register R1 and register R2, and stores the result in register R2. "Instruction C" is "ADD
R1, R3 "addition instruction, adds the contents of the registers R1 and R3, and stores the result in the register R3.

  Here, the contents of the register R1 handled by the “instruction B” are different from the contents of the register R1 handled by the “instruction C”. This is because, as shown in FIG. 5, the update of the register R1 by “instruction A” is not reflected in “instruction B” but is reflected in “instruction C”. That is, “instruction B” uses the contents of register R1 before execution of “instruction A”, whereas “instruction C” stores the contents read out by “instruction A”, that is, at the (mem) address on the memory. Will use the content.

  This is an architectural feature of the CPU, and programmers program it after understanding it.

  FIG. 6 shows a case where this is debugged by single step execution. In single-step execution, since each instruction is executed independently, there are several unrelated cycles of “instruction A” and “instruction B” as shown in FIG. Then, when “instruction B” is executed, the contents of the register R1 are updated with “instruction A”. Therefore, the calculation is performed for the contents different from the original execution time, and there is no meaning of debugging.

  Therefore, when such a problem (generally called a hazard) may occur, single-step execution cannot be performed. In this example, since “instruction A” corresponds to a delayed instruction, an interrupt such as a single step should not be accepted between “instruction A” and “instruction B”.

  If it is possible to accept, it is necessary to devise such as holding / restoring the contents of the register in the middle of the instruction processing by processing using special hardware so that the above problem does not occur. These have already been established as conventional techniques.

  However, if an interrupt is received immediately after a delay instruction, a problem (hazard) does not necessarily occur. In the case of the example of FIG. 5, when “instruction B” is an instruction that does not use the register R 1, “instruction A” and “instruction B” are not related, and “instruction A” and “instruction B” are not related. No hazard will occur even if an interrupt occurs. Whether or not a hazard occurs due to an interrupt is determined by an operand (generally a register in many cases) specified by an instruction, and can be grasped at the stage of programming by a programmer.

  The present invention has been made in consideration of the above points. In the present invention, when an interrupt is received immediately after a delay instruction, two developments are prepared according to problems that may occur.

  The first of the above two cases is a case where an interrupt is received immediately after the delay instruction causes an obstacle in the control of the CPU. This is a case where the delay instruction is an instruction such as a branch instruction and cannot be interrupted immediately before the delay slot (immediately after the delay instruction) without special hardware. Control is performed so that no interrupt is accepted immediately after the delay instruction corresponding to this case.

  The second of the above two cases is a case where the control of the CPU is not affected. In other words, this means an instruction that can cause a data hazard. When this type of delayed instruction causes a data hazard, it is not a normal instruction itself but a hazard that occurs because an operand in which data is stored is designated by preceding and following instructions. Therefore, in the present invention, it is noted that in this second case, it is not necessary to uniformly prohibit the acceptance of the immediately following interrupt as a delay instruction. If it has been secured, a mode is provided to allow acceptance of interrupts. With this, even if the operands of the delayed instruction are carefully arranged, debugging work can be executed without causing a problem hazard even if single stepping is performed.

Next, specific processing of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic diagram of a block to which the interrupt processing method of the present invention is applied. In the figure, 1 is an instruction decoder (DEC) for decoding an instruction, and 2 is a flag register (FLAG) operable by the instruction. When a delay instruction is issued from the instruction decoder 1, a signal (LOC) indicating that a delay instruction is detected is output to the signal line 10. The flag register 2 outputs the contents of the B flag of the flag register 2 to the signal line 20. This B flag sets the B flag in the flag register 2 when a hazard occurs when an interrupt occurs, that is, when the interrupt is invalidated.

  The signal lines 10 and 20 are connected to the AND gate 5, and the LOC signal and the B flag signal are supplied to the AND gate 5. The AND gate 5 outputs an output signal to the output signal line 30 in response to both signals. When the LOC signal and the B flag signal are given to the AND gate 5, an interrupt inhibition signal (NSS) is generated and output.

  As described above, in the first processing method of the present invention, when the delayed instruction is detected by the instruction decoder 1 and the LOC signal is output, and the B flag of the flag register 2 is set, the AND gate 5 An interrupt disable signal (NSS) is generated, and the immediately following interrupt is invalidated.

  When the delay instruction is detected by the instruction decoder 1 and the LOC signal is output and the B flag of the flag register 2 is in the reset state, the interrupt disable signal (NSS) is not generated from the AND gate 5 and immediately after. Enable interrupts.

  Further, even when a delay instruction is not detected by the instruction decoder 1 and the B flag of the flag register is set, an interrupt disable signal (NSS) is not generated from the AND gate 5 and the immediately following interrupt is valid. And

  When the instruction decoder 1 does not detect a delayed instruction and the B flag of the flag register 2 is in the reset state, the interrupt disable signal (30NSS) is not generated from the AND gate 5 and the immediately following interrupt is valid. To do.

  As described above, in the first processing method of the present invention, the programmer can select valid / invalid of the interrupt immediately after the delay instruction by manipulating the contents of the B flag of the flag register 2.

  FIG. 2 is a schematic diagram of a block to which the second interrupt processing method of the present invention is applied. In addition, the same code | symbol is attached | subjected about the same structure as FIG.

  When the instruction decoder 1 detects the first type of delay instruction, a signal (LOCA) indicating that the first type of delay instruction is detected is output to the signal line 11. When the instruction decoder 1 detects the second type delay instruction, a signal (LOCB) indicating that the second type delay instruction is detected is output to the signal line 12.

  Further, the flag register (FLAG) 2 outputs the contents of the B flag of the flag register 2 to the signal line 20. The B flag is set in the flag register 2 when a hazard occurs when an interrupt occurs.

  The signal lines 12 and 20 are connected to the logic gate 6, and the LOCB signal and the B flag signal are supplied to the AND gate 6. An intermediate signal corresponding to both signals is generated from the AND gate 6.

  The AND gate 6 outputs an intermediate signal for invalidating the immediately following interrupt when the LOCB signal and the B flag are given. This signal is given from the signal line 13 to the OR gate 7.

  The OR gate 7 generates an interrupt inhibition signal (NSS) based on the LOCA signal that detects the intermediate signal from the AND gate 6 or the first type of delay instruction given from the instruction decoder 1, and outputs the output signal line 30. Output to.

  Here, the first type of delay instruction detected by the instruction decoder 1 is an instruction for invalidating the immediately following interrupt regardless of the state of the B flag. The second type of delay instruction detected by the instruction decoder 1 is an instruction for selecting whether to enable / disable the next interrupt depending on the state of the B flag.

  In the second processing method of the present invention, when the first type of delay instruction is detected by the instruction decoder 1 and the LOCA signal is output, the OR gate 7 interrupts regardless of the state of the B flag of the flag register 2. A prohibition signal (NSS) is generated and the immediately following interrupt is invalidated.

  When the instruction decoder 1 does not detect the first type of delay instruction, the instruction decoder 1 detects the second type of delay instruction, the LOCB is applied to the signal line 12, and the flag register 2 B When the flag is in the set state, an interrupt disable signal (NSS) is generated from the OR gate 7 and the immediately following interrupt is invalidated.

  Further, when the first type of delay instruction is not detected by the instruction decoder 1, the second type of delay instruction is detected by the instruction decoder 1, LOCB is applied to the signal line 12, and B of the flag register 2 is detected. When the flag is in the reset state, the interrupt disable signal (NSS) is not generated from the OR gate 7 and the immediately following interrupt is validated.

  Further, when the instruction decoder 1 does not detect the first type of delayed instruction, the instruction decoder 1 does not detect the second type of delayed instruction, and the B flag of the flag register 2 is in the set state, the logic The interrupt disable signal (NSS) is not generated from the sum gate 7, and the immediately following interrupt is validated.

  When the instruction decoder 1 does not detect the first type of delayed instruction, the instruction decoder 1 does not detect the second type of delayed instruction, and the B flag of the flag register 2 is in the reset state. The interrupt disable signal (NSS) is not generated from the sum gate 7, and the immediately following interrupt is validated.

  In the first processing method described above, both means for enabling and disabling the interrupt immediately after the delay instruction must be provided, and hardware cost becomes a problem. It is difficult to adopt in a system where cost is the most important, and there are also possible negative aspects such as a decrease in operating frequency and an increase in power consumption. However, in this second processing method, the first type of delay instruction that disables the immediately following interrupt regardless of the state of the B flag and the second type that can switch the immediately following interrupt valid / invalid by the B flag. Two types of delay instructions are prepared. Then, delay processing that imposes a significant hardware burden on the implementation of an interrupt immediately after delay, such as a special register such as a delayed branch instruction, because the branch destination address and return address are different, and so on. For such instructions, the immediately following interrupt acceptance is prohibited regardless of the flag state, and for the delayed instructions that do not incur a hardware cost, the immediately following interrupt can be enabled / disabled depending on the flag state. With this configuration, it becomes possible to perform single step execution even for a part of instructions that could not be executed in a single step in the past without causing an increase in hardware, thereby improving the ease of debugging.

  FIG. 3 is a schematic diagram of a block to which the third interrupt processing method of the present invention is applied. In the figure, 1 is an instruction decoder (DEC) for decoding an instruction, and 3 is a predecoder (PDEC). The predecoder (PDEC) 3 handles an instruction immediately after being handled by the instruction decoder 1. That is, the instruction sent to the instruction decoder 1 in the next stage is handled.

  When the instruction decoder 1 detects the first type of delay instruction, it outputs a LOCA signal to the signal line 11, and when it detects the second type of delay instruction, it outputs a LOCB signal to the signal line 12.

  The predecoder 3 outputs an INST signal to the signal line 21 as a result of detecting an instruction that may cause a hazard if executed immediately after the second type delay instruction.

  The signal lines 12 and 21 are connected to an AND gate 61. The AND gate 61 is supplied with a LOCB signal and an INST signal, and the AND gate 61 generates an intermediate signal. This intermediate signal is applied from the signal line 14 to the OR gate 7. The logical gate 7 is supplied with the LOCA signal from the instruction decoder 1.

  The above intermediate signal generates an interrupt inhibition signal (NSS) by the LOCA signal and the OR gate 7 and outputs it to the output signal line 30. Since the LOCB signal, the INST signal, and the AND gate 61 need to be combined only for the second instruction type, there may be a plurality of LOCB signals, INST signals, and AND gates 61. In the example of FIG. 3, two examples are shown.

  Here, the first type of delay instruction detected by the instruction decoder 1 is an instruction for invalidating the immediately following interrupt regardless of the subsequent instruction, and the second type of delay instruction detected by the instruction decoder 1 Is an instruction that switches between enabling and disabling the next interrupt depending on the type of subsequent instruction.

  In the third processing method, when the first type of delay instruction is detected by the instruction decoder 1, an interrupt disable signal (NSS) is generated from the OR gate 7 regardless of the type of the subsequent instruction, and the interrupt immediately after Is invalid.

  When the instruction decoder 1 does not detect the first type of delayed instruction, the instruction decoder 1 detects the second type of delayed instruction, and there is an interrupt immediately after the instruction detected by the instruction decoder 1. When a succeeding instruction that may cause a hazard is detected, an interrupt disable signal (NSS) is generated from the OR gate 7 and the immediately following interrupt is invalidated.

  Further, when the instruction decoder 1 does not detect the first type of delay instruction and the instruction decoder 1 does not detect the second type of delay instruction, the interrupt disable signal (NSS) is not generated from the OR gate 7. The interrupt immediately after is made valid.

  When the instruction decoder 1 does not detect the first type of delayed instruction, the instruction decoder 1 detects the second type of delayed instruction, and there is an interrupt immediately after the instruction detected by the instruction decoder 1. When the predecoder 3 does not detect a succeeding instruction that may cause a hazard, an interrupt disable signal (NSS) is not generated from the OR gate 7 and the immediately following interrupt is validated.

  With the configuration as described above, it is possible to automatically determine whether or not to permit interruption, so that knowledge and effort are not required from the programmer. Further, even if a program has a possibility of occurrence of a hazard and a case in which no hazard is present, it is not necessary to uniformly disable interrupts, so that debugging accuracy is improved.

  FIG. 4 is a schematic diagram of a block to which the fourth interrupt processing method of the present invention is applied. In the figure, 1 is an instruction decoder (DEC) for decoding an instruction, and 3 is a predecoder (PDEC). The predecoder (PDEC) 3 handles an instruction immediately after being handled by the instruction decoder 1. That is, the instruction sent to the instruction decoder 1 in the next stage is handled.

  When the instruction decoder 1 detects the first type of delay instruction, it outputs a LOCA signal to the signal line 11, and when it detects the second type of delay instruction, it outputs a LOCB signal to the signal line 12.

  Further, the instruction decoder 1 outputs an OPA signal to the signal line 22 when detecting operand information that may cause a hazard specified in the second type of delay instruction. When the predecoder 3 detects operand information that may cause a hazard specified in the instruction of the detected subsequent instruction, the predecoder 3 outputs an OPB signal to the signal line 23. The OPA signal and the OPB signal are supplied to the comparator 8. If the OPA signal and the OPB signal coincide with each other, it is known that a hazard is generated by an interrupt immediately after the delay instruction, as in the example shown in FIG. Therefore, the comparator 8 checks whether the OPA signal and the OPB signal match, and outputs the result as an intermediate signal to the signal line 14 to provide an AND gate 62. The logical product gate 62 is supplied with the LOCB signal from the instruction decoder 1.

  An intermediate signal is generated by the logical product of the LOCB signal and the intermediate signal by the logical product gate 62 and applied to the logical sum gate 7 from the signal line 15. This intermediate signal is logically summed by the LOCA from the instruction decoder 1 and the logical sum gate 7 to generate an interrupt inhibition signal (NSS) and output it to the signal line 30.

  In the fourth processing method of the present invention, when the first type of delayed instruction is detected by the instruction decoder 1, an interrupt disable signal (NSS) is generated regardless of the operand of the subsequent instruction, and the immediately following interrupt is disabled. To do.

  When the instruction decoder 1 does not detect the first type of delay instruction, the instruction decoder 1 detects the second type of delay instruction, and the operand (OPA) of the delay instruction detected by the instruction decoder 1 is detected. When the operand (OPB) of the subsequent instruction detected by the predecoder 3 matches, an interrupt inhibition signal (NSS) is generated and the immediately following interrupt is invalidated.

  Further, when the instruction decoder 1 does not detect the first type of delayed instruction and the instruction decoder 1 does not detect the second type of delayed instruction, the interrupt prohibition signal (NSS) is not generated and the next interrupt is Valid.

  When the instruction decoder 1 does not detect the first type of delay instruction, the instruction decoder 1 detects the second type of delay instruction, and the operand (OPA) of the delay instruction detected by the instruction decoder 1 is detected. When the operand (OPB) of the subsequent instruction detected by the predecoder 3 does not match, the interrupt prohibition signal (NSS) is not generated and the immediately following interrupt is validated.

  According to the above method, since the possibility of a hazard is checked at the operand level, even in the combination of a delayed instruction and a subsequent instruction that may cause a hazard, a hazard does not occur due to an operand mismatch and an interrupt occurs. In some cases, it is not necessary to prohibit the operation, so that the accuracy of debugging is further improved.

It is the schematic of the block to which the 1st interrupt processing method of this invention is applied. It is the schematic of the block to which the 2nd interrupt processing method of this invention is applied. It is the schematic of the block to which the 3rd interrupt processing method of this invention is applied. It is the schematic of the block to which the 4th interrupt processing method of this invention is applied. It is an operation | movement timing diagram of the pipeline process of the delay instruction concerning one Embodiment of this invention. It is an operation | movement timing diagram in the case of debugging by single step execution.

Explanation of symbols

1 Instruction decoder 2 Flag register 3 Predecoder 5 AND gate 7 OR gate 8 Comparator 61 AND gate 62 AND gate

Claims (2)

In an information processing apparatus that pipelines a delay instruction having a delay slot, it has at least one flag register that can be set by the instruction, and switches an interrupt immediately after the delay instruction to valid or invalid depending on the state of the flag register. An interrupt processing method in an information processing apparatus. A first delay instruction that disables the immediately following interrupt regardless of the state of the flag register; and a second delay instruction that can switch enable / disable of the immediately following interrupt by a flag stored in the flag register. The interrupt processing method in the information processing apparatus according to claim 1, further comprising:

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