JPH0511889A - Initializing circuit for data processor - Google Patents
Initializing circuit for data processorInfo
- Publication number
- JPH0511889A JPH0511889A JP3163217A JP16321791A JPH0511889A JP H0511889 A JPH0511889 A JP H0511889A JP 3163217 A JP3163217 A JP 3163217A JP 16321791 A JP16321791 A JP 16321791A JP H0511889 A JPH0511889 A JP H0511889A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- switch
- initial setting
- condition
- shift control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は集積回路で構成されるデ
ータ処理装置の初期設定回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initial setting circuit of a data processing device composed of an integrated circuit.
【0002】[0002]
【従来の技術】従来のデータ処理装置における初期設定
は、一般に電源投入時に初期マイクロプログラムロード
後、マイクロプログラムにより装置内条件設定を行う
が、このとき一部の条件は集積回路(LSI)の外に配
置したスイッチの状態を直接にLSI内にとり込み設定
条件としていた。2. Description of the Related Art Generally, initial setting in a conventional data processing apparatus is performed by loading an initial microprogram at power-on and then setting internal apparatus conditions by the microprogram. At this time, some conditions are outside the integrated circuit (LSI). The state of the switch arranged in the above was directly taken into the LSI and used as the setting condition.
【0003】[0003]
【発明が解決しようとする課題】この従来のデータ処理
装置の初期設定方式では、外部配置のスイッチ条件が増
加すると、その分だけLSIの入出力ピンを使用するこ
とになり、ピンリミットでLSIが構成できなくなった
り、より多ピンのLSIを使用せざるを得ずコストが大
幅に上ってしまうという問題点があった。In this conventional data processing device initial setting method, if the externally arranged switch conditions increase, the input / output pins of the LSI are used correspondingly, and the LSI is limited by the pin limit. There is a problem in that the cost cannot be increased or the cost cannot be increased because there is no choice but to use an LSI having more pins.
【0004】又、従来、LSI内の論理ミスが発見され
ると、一般には再設計となるが、特に論理ミスの多い障
害検出機能回りは予め抑止条件等をLTI外から制御で
きるようにしておくことにより回避できるケースが多
く、この場合もLSIのピン増加を必要としていた。Conventionally, when a logic miss in the LSI is found, the design is generally redesigned. However, especially in the fault detection function having many logic misses, it is possible to previously control the deterrent condition from outside the LTI. In many cases, this can be avoided, and in this case as well, it was necessary to increase the pins of the LSI.
【0005】[0005]
【課題を解決するための手段】本発明のデータ処理装置
の初期設定回路は、複数のスイッチから構成されるスイ
ッチ回路と、該スイッチ回路の各スイッチに対応してそ
の状態を保持するスイッチ条件保持回路と、該スイッチ
条件保持回路の出力がシフトパスで接続される初期設定
レジスタと、該初期設定レジスタの出力が入力条件とな
る条件設定回路と、前記スイッチ条件保持回路と初期設
定レジスタのリセット動作及びシフト制御を行うリセッ
ト/シフト制御回路とから構成され、前記初期設定レジ
スタ及び条件設定回路が同一集積回路に含まれることを
特徴とする。An initial setting circuit of a data processing apparatus according to the present invention comprises a switch circuit composed of a plurality of switches, and a switch condition holding unit for holding the state corresponding to each switch of the switch circuit. A circuit, an initial setting register to which the output of the switch condition holding circuit is connected by a shift path, a condition setting circuit in which the output of the initial setting register is an input condition, a reset operation of the switch condition holding circuit and the initial setting register, and A reset / shift control circuit for performing shift control, and the initial setting register and the condition setting circuit are included in the same integrated circuit.
【0006】[0006]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【0007】図1は本発明の一実施例のブロック図であ
る。FIG. 1 is a block diagram of an embodiment of the present invention.
【0008】1はリセット/シフト制御回路で、信号線
101にてスイッチ条件保持回路2及び初期設定レジス
タ5に接続される。2は複数のスイッチから構成される
スイッチ回路で、各スイッチの信号線102がシフトレ
ジスタで構成されるスイッチ条件保持回路3に接続され
る。A reset / shift control circuit 1 is connected to the switch condition holding circuit 2 and the initial setting register 5 via a signal line 101. Reference numeral 2 is a switch circuit including a plurality of switches, and a signal line 102 of each switch is connected to a switch condition holding circuit 3 including a shift register.
【0009】スイッチ条件保持回路3のシフト出力10
3がシフトレジスタで構成される初期設定レジスタ5の
シフトインに接続され、初期設定レジスタ5の出力10
4は条件設定回路6に入力される。The shift output 10 of the switch condition holding circuit 3
3 is connected to the shift-in of the initialization register 5 composed of a shift register, and the output 10 of the initialization register 5
4 is input to the condition setting circuit 6.
【0010】初期設定レジスタ5及び条件設定回路6を
含んで集積回路4が構成され、リセット/シフト制御回
路1は集積回路4に含まれてもよい。The integrated circuit 4 may be configured to include the initial setting register 5 and the condition setting circuit 6, and the reset / shift control circuit 1 may be included in the integrated circuit 4.
【0011】次に動作について説明する。Next, the operation will be described.
【0012】スイッチ回路の各スイッチが予め人手等に
より設定されているとする。装置の電源投入に引きつづ
き、リセット/シフト制御回路1によりスイッチ条件保
持回路3及び初期設定レジスタ5をリセットし、引きつ
づくリセット/シフト制御回路の動作によりスイッチ回
路2の状態がスイッチ条件保持回路3にとり込まれ、更
にリセット/シフト制御回路1の制御によりシフト動作
が起動され、スイッチ条件保持回路3の内容が初期設定
レジスタ5に移送される。It is assumed that each switch of the switch circuit has been set manually in advance. Following the power-on of the device, the reset / shift control circuit 1 resets the switch condition holding circuit 3 and the initialization register 5, and the subsequent operation of the reset / shift control circuit causes the state of the switch circuit 2 to change. The shift operation is activated by the control of the reset / shift control circuit 1, and the contents of the switch condition holding circuit 3 are transferred to the initial setting register 5.
【0013】初期設定レジスタ5の出力104は、他の
各種条件105と合せて条件設定回路6の入力となる。
以降装置はこの条件で動作する。The output 104 of the initial setting register 5 becomes the input of the condition setting circuit 6 together with other various conditions 105.
After that, the device operates under this condition.
【0014】図2は図1に示したスイッチによる外部条
件取込み動作を必要に応じて抑制可能とさせたもので、
図1に対して7で示す付加スイッチ回路を追加し、その
状態信号106がリセット/シフト制御回路1に接続さ
れる構成を有する。FIG. 2 is a diagram in which the external condition taking-in operation by the switch shown in FIG. 1 can be suppressed as necessary.
An additional switch circuit shown by 7 is added to FIG. 1, and the state signal 106 thereof is connected to the reset / shift control circuit 1.
【0015】付加スイッチ回路のスイッチは予め人手等
により設定され、装置の電源投入時にリセット/シフト
制御回路が行う一連の制御動作のうちリセット動作以降
を抑止するよう働く。The switch of the additional switch circuit is set in advance manually or the like, and works to suppress the reset operation and the subsequent steps of the series of control operations performed by the reset / shift control circuit when the power of the apparatus is turned on.
【0016】[0016]
【発明の効果】以上説明したように、本発明はLSIの
外部から与える初期設定条件を一担シフトレジスタにと
り込み、シフト動作によりLSI内に設定することによ
り、LSIの入出力ピンを大幅に削減し、コスト低減に
寄与するという効果を有する。又、論理ミス回避対策を
予めLSI内に入れておきこれを有効に使えるという効
果を有する。As described above, according to the present invention, the initial setting conditions given from the outside of the LSI are fetched into the shared shift register and set in the LSI by the shift operation, so that the input / output pins of the LSI are greatly reduced. However, it has an effect of contributing to cost reduction. Further, there is an effect that a measure for avoiding a logic error is put in the LSI in advance and it can be effectively used.
【図面の簡単な説明】[Brief description of drawings]
【図1】本発明の一実施例のブロック図を示す。FIG. 1 shows a block diagram of one embodiment of the present invention.
【図2】本発明の他の一実施例のブロック図を示す。FIG. 2 shows a block diagram of another embodiment of the present invention.
1 リセット/シフト制御回路 2 スイッチ回路 3 スイッチ条件保持回路 4 集積回路 5 初期設定レジスタ 6 条件設定回路 7 付加スイッチ回路 1 Reset / shift control circuit 2 switch circuits 3 switch condition holding circuit 4 integrated circuits 5 Initial setting register 6 Condition setting circuit 7 Additional switch circuit
Claims (2)
回路と、該スイッチ回路の各スイッチに対応してその状
態を保持するスイッチ条件保持回路と、該スイッチ条件
保持回路の出力がシフトパスで接続される初期設定レジ
スタと、該初期設定レジスタの出力が入力条件となる条
件設定回路と、前記スイッチ条件保持回路と初期設定レ
ジスタのリセット動作及びシフト制御を行うリセット/
シフト制御回路とから構成され、前記初期設定レジスタ
及び条件設定回路が同一集積回路に含まれることを特徴
とするデータ処理装置の初期設定回路。1. A switch circuit composed of a plurality of switches, a switch condition holding circuit that holds the state of each switch of the switch circuit, and an output of the switch condition holding circuit are connected by a shift path. An initial setting register, a condition setting circuit in which the output of the initial setting register is an input condition, a reset operation for performing a reset operation and shift control of the switch condition holding circuit and the initial setting register
And a shift control circuit, wherein the initial setting register and the condition setting circuit are included in the same integrated circuit.
接続され、該リセット/シフト制御回路によるスイッチ
条件保持回路から初期設定レジスタへのシフト動作制御
を抑止する付加スイッチ回路を設けたことを特徴とする
請求項1記載のデータ処理装置の初期設定回路。2. An additional switch circuit, the output of which is connected to a reset / shift control circuit, for suppressing shift operation control from the switch condition holding circuit to the initial setting register by the reset / shift control circuit. The initialization circuit of the data processing device according to claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3163217A JPH0511889A (en) | 1991-07-04 | 1991-07-04 | Initializing circuit for data processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3163217A JPH0511889A (en) | 1991-07-04 | 1991-07-04 | Initializing circuit for data processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0511889A true JPH0511889A (en) | 1993-01-22 |
Family
ID=15769535
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3163217A Pending JPH0511889A (en) | 1991-07-04 | 1991-07-04 | Initializing circuit for data processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0511889A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100721091B1 (en) * | 1999-11-29 | 2007-05-23 | 텍사스 인스트루먼츠 인코포레이티드 | Flexible general-purpose input/output system |
-
1991
- 1991-07-04 JP JP3163217A patent/JPH0511889A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100721091B1 (en) * | 1999-11-29 | 2007-05-23 | 텍사스 인스트루먼츠 인코포레이티드 | Flexible general-purpose input/output system |
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