JPH05114727A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce the off-leakage current by selfmatchingly forming a diffused layer only on the part beneath the gate electrode. CONSTITUTION:An N type silicon substrate 200 is ion-implanted with boron to form a P type well 201 and after the formation of a LOCOS oxide film 202 for element isolation, a gate insulating oxide film 203 is formed. Next, a silicon nitride film 204 is formed; the nitride film 204 in a gate electrode region is removed; the substrate 200 is ion-implanted with boron fluoride to form a punch-through stopper 205. Next, a polysilicon film 206 is deposited on the whole surface and then phosphorus is added to the polysilicon. Furthermore, after processing the polysilicon in the size larger than that of the gate electrode, the silicon nitride film 204 is removed by heated phosphoric acid to be turned into a polysilicon gate electrode 207. Through the procedures, the punch through stopper 205 can be left intact only on the part beneath the gate electrode 207 thereby enabling the off-leakage current to be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a MIS type semiconductor device and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been highly integrated, and MIS type semiconductors widely used therein have been miniaturized one after another, and a short channel device having a channel length of less than 1 μm has been demanded. It has become possible to be.

In recent years, devices used for semiconductor integrated circuits have been required to have such short channels, but the power supply voltage has been reduced by the reduction ratio of the channel size due to market needs. The reality is that there is none.

Due to such shortening of the channel length, the punch through phenomenon becomes a very serious problem in the MIS type semiconductor device.

As a method of suppressing the punch-through phenomenon, (1) a method of taking not only the planar channel length but also the channel length in the substrate depth direction.

(2) Substrate concentration (or well concentration)
A method of increasing the height of the whole structure and suppressing the extension of the depletion layer from the drain.

(3) A method of forming a so-called punch-through stopper by increasing the substrate concentration only in the most extended portion of the depletion layer.

Etc. have been proposed.

However, the method (1) has a drawback in that the steps are complicated and it is difficult to form a device having uniform characteristics on a semiconductor integrated circuit.

With regard to the method (2), the off-leakage current of the MIS transistor is increased due to the increase of the leakage current of the diode formed between the drain and the substrate (well) at the time of reverse bias, and the leakage current of the MIS transistor is increased. It becomes unsuitable for devices for semiconductor integrated circuits. Further, even when used as a device for a logic circuit, the power consumption becomes large, which is not suitable.

For the above reason, it is necessary to suppress the leak current by forming the punch-through stopper shown in (3) to reduce the area where the conductive impurities of high conductivity between the drain and the substrate are in contact with each other.

[0012]

As a method of forming a punch-through stopper, a gate insulating film is formed, and then an ion implantation method is used to form the punch-through stopper at a position about the junction depth of the source / drain contact diffusion layer and the same conductivity type as that of the substrate or well. It was obtained by adding impurities.

However, in recent years, further miniaturization of the device has progressed, and the leak between the punch-through stopper and the drain has become a problematic level. In order to reduce this leak current, the punch-through stopper may be present only on the channel region side. However, due to the progress of device miniaturization, it is at a level that cannot be solved by photolithography technology.

Therefore, it is an object of the present invention to provide a punch-through stopper structure having a smaller off-leakage current than the conventional punch-through stopper, and a technique for forming the punch-through stopper structure by self-alignment.

[0015]

In order to solve the problems, the present invention is characterized in that in a MIS type semiconductor device, a diffusion layer is formed only under the gate electrode in a self-aligning manner.

[0016]

Since the punch-through stopper is formed just below the gate, the off-leakage current can be reduced while maintaining the punch-through suppressing effect of the MIS transistor. Further, the punch-through stopper is self-aligned. Therefore, the element does not become large.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, L shown in FIG.
The structure of the DD type NchMOS transistor and its manufacturing method will be described.

The structure will be described with reference to FIG.
In the P-type well 101 on the silicon substrate 100, L
OCOS oxide film 102, gate insulating film 103, polysilicon electrode 104, P-type punch through stopper 105,
N-type low-concentration source / drain diffusion region 106, sidewall protection film 107, N-type high-concentration source / drain diffusion region 10
8, a transistor including the interlayer insulating film 109, the aluminum electrode 110, and the passivation film 111 is formed.

2 (a) to 2 (f) are sectional views showing the main manufacturing steps of the method of manufacturing the LDD type NchMOS transistor shown in FIG. Figure 2 (a) below
~ One embodiment of the manufacturing method will be described with reference to FIG.

First, as shown in FIG. 2A, the acceleration energy of boron is 50 to 100 KeV and the dose is 5E12 to 5E13 by ion implantation into the N-type silicon substrate 200.
The P-type well 201 is formed under the condition of cm ⁻² , the LOCOS oxide film 202 is formed to a thickness of 300 to 1000 nm for element isolation, and then the oxide film is formed to a thickness of 15 to 3 as the gate insulating film 203.
0 nm is formed.

Next, as shown in FIG. 2B, a silicon nitride film 204 is formed to a thickness of 300 nm by the CVD method, and the nitride film in the gate electrode region is removed by a photolithography process and an etching process (this embodiment). Then, the width of the polysilicon electrode is set to 0.8 μm.), And boron fluoride is accelerated at an energy of 100 to 200 KeV and a dose of 1E12 to 1.
Ion implantation is performed at E13 cm ⁻² to form a punch through stopper 205.

After that, as shown in FIG. 2C, a polysilicon film 206 is deposited to a thickness of 500 nm by a CVD method, and phosphorus is deposited to a sheet resistance of 40 by pre-deposition.
Add to polysilicon to be Ω / □.

Further, as shown in FIG. 2D, the polysilicon is processed by a photolithography process and a dry etching process so as to have a thickness 0.2 μm thicker than the gate electrode.

Then, as shown in FIG. 2E, a photoresist is applied and etched back to remove the protrusions on the sides of the polysilicon, and the silicon nitride film is removed by hot phosphoric acid to form a polysilicon gate electrode 207. To do.

Then, as shown in FIG.
According to the manufacturing process of the DD transistor, phosphorus is used with an acceleration energy of 100 to 150 KeV and a dose of 1E13 to 5E13.
Ion implantation is performed under the condition of cm ⁻² to form a low concentration source / drain diffusion layer region 208, a side wall protective oxide film 209 is formed, and arsenic is accelerated at an energy of 80 KeV and a dose amount of 2E1.
Ion implantation is performed under the conditions of 5 to 1E16 cm ⁻² , and annealing is performed at 900 to 1000 ° C. for 10 to 30 minutes to activate arsenic to form a high concentration source / drain diffusion layer region 210, an interlayer insulating film 211, and aluminum. By forming the electrode 212 and the passivation film 213, a desired LDD type Nch transistor is obtained.

When a punch-through stopper is to be formed directly below the gate electrode by this manufacturing method, it is impossible to realize a transistor having a size of 1 μm or less due to the dimensional alignment accuracy / dimension conversion difference between photolithography and etching. It can be formed by self-alignment.

Further, since the punch-through stopper exists just below the channel, the off-leakage current can be remarkably reduced as compared with the conventional punch-through stopper.

[0028]

According to the present invention, a punch-through stopper formed only in the channel region by self-alignment can be obtained. Therefore, even in a fine device in which the channel length of the device is less than 1 μm, it can be positioned directly under the channel with good positional accuracy. A punch-through stopper can be formed, which makes it possible to reduce the substrate concentration (or well concentration), and the off-leak current can be reduced to about 1/3.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor device of the present invention.

2 (a) to 2 (f) are cross-sectional views for each main step showing one embodiment of the method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

 100. ． ． N-type silicon substrate 101. ． ． P-type well 102. ． ． LOCOS oxide film 103. ． ． Gate insulating film 104. ． ． Polysilicon electrode 105. ． ． P-type punch through stopper 106. ． ． Low concentration source / drain diffusion region 107. ． ． Side wall protection film 108. ． ． High concentration source / drain diffusion region 109. ． ． Interlayer insulating film 110. ． ． Aluminum electrode 111. ． ． Passivation film 200. ． ． N-type silicon substrate 201. ． ． P-type well 202. ． ． LOCOS oxide film 203. ． ． Gate insulating film 204. ． ． Silicon nitride film 205. ． ． Punch-through stopper 206. ． ． Polysilicon film 207. ． ． Polysilicon gate electrode 208. ． ． Low concentration source / drain diffusion region 209. ． ． Side wall protection film 210. ． ． High concentration source / drain diffusion region 211. ． ． Interlayer insulating film 212. ． ． Aluminum electrode 213. ． ． Passivation film

Claims (2)

[Claims] 1. A semiconductor device comprising a MIS type semiconductor device in which a diffusion layer is formed in a self-aligning manner just under a gate electrode. 2. A step of: (A) forming a gate insulating film on a silicon substrate and then forming a mask of a silicon nitride film; and (B) a substrate on which the nitride film mask is formed, which is the same as the first substrate. A step of adding a conductivity type impurity by ion implantation; (C) a step of forming a polysilicon film or an amorphous silicon film; and (D) a step of etching the polysilicon film or the amorphous silicon film into a gate electrode. And a step (E) of removing the silicon nitride film mask with hot phosphoric acid.