JPH05114678A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05114678A
JPH05114678A JP2407686A JP40768690A JPH05114678A JP H05114678 A JPH05114678 A JP H05114678A JP 2407686 A JP2407686 A JP 2407686A JP 40768690 A JP40768690 A JP 40768690A JP H05114678 A JPH05114678 A JP H05114678A
Authority
JP
Japan
Prior art keywords
heat sink
soldering surface
semiconductor device
soldering
outer peripheral
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2407686A
Other languages
Japanese (ja)
Other versions
JP2843684B2 (en
Inventor
Toshinobu Sekiba
利信 関場
Tomoyuki Sugita
智幸 杉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Components Co Ltd
Original Assignee
Toshiba Components Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18517242&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JPH05114678(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Toshiba Components Co Ltd filed Critical Toshiba Components Co Ltd
Priority to JP2407686A priority Critical patent/JP2843684B2/en
Publication of JPH05114678A publication Critical patent/JPH05114678A/en
Application granted granted Critical
Publication of JP2843684B2 publication Critical patent/JP2843684B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To let a strain produced when a heat sink is driven in a heat radiating fin to go off so as to improve the performance of a semiconductor pellet by making the soldering surface of the heat sink higher in level than the upper end section for knurling and the outer peripheral wall of the heat sink higher in level than the soldering surface and, in addition, forming the soldering surface to a projecting shape provided with a groove along its outer periphery. CONSTITUTION:The soldering surface of a heat sink 21 is made higher in level than the upper end section P of a surface 23 for knurling and the outer peripheral wall of the heat sink 21 is made higher in level than the surface 22. In addition, the surface 22 is formed to a projecting shape with a groove 24 along its outer periphery. The projected extent of the soldering surface is minimized, but the insufficiency in the extent is compensated by means of the groove 24 formed along the periphery of the heat sink 21. Therefore, a strain produced when the heat sink 21 is driven in a heat radiating fin 6 can be made to go off and an adverse influence to a semiconductor pellet 4 can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はヒートシンクの半田付面
に半導体ペレットを取り付けた半導体装置に関し、特に
ヒートシンクに改良を施した圧入型ダイオードに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a semiconductor pellet is attached to a soldering surface of a heat sink, and more particularly to a press-fit type diode having an improved heat sink.

【0002】[0002]

【従来の技術】従来、ヒートシンクとしては、例えば図
3(A),(B)、図4(A),(B)に示す構造のも
のが知られている。ここで、図3(B)は同図(A)の
X−X線に沿う断面図、図4(B)は同図(A)のX−
X線に沿う断面図である。
2. Description of the Related Art Conventionally, as a heat sink, one having a structure shown in FIGS. 3A, 3B, 4A, and 4B is known. Here, FIG. 3B is a cross-sectional view taken along line XX of FIG. 3A, and FIG. 4B is X- of FIG.
It is sectional drawing which follows an X-ray.

【0003】図3及び図4において、1は図7に示す如
く外周側面にローレット加工が施されたローレット部で
あり、2は半導体ペレットが取付けられる半田付面であ
る。ここで、図3は半田付面2がローレット加工面1の
上端より低い場合であり、図4は逆に半田付面2がロー
レット加工面1の上端より高い場合である。
In FIGS. 3 and 4, reference numeral 1 is a knurled portion whose outer peripheral side surface is knurled as shown in FIG. 7, and 2 is a soldering surface to which a semiconductor pellet is attached. Here, FIG. 3 shows the case where the soldering surface 2 is lower than the upper end of the knurled surface 1, and FIG. 4 shows the case where the soldering surface 2 is higher than the upper end of the knurled surface 1 conversely.

【0004】図5は、図3のヒートシンク3に半導体ペ
レット4を半田層5aを介して取付けた半導体装置の例を
示す。図5において、6はヒートシンク3の外周部に位
置するアルミ製の放熱フィンである。また、7は半導体
ペレット4に半田層5bを介して接続する銅製リード、8
はシリコン又はエポキシ樹脂からなる保護層である。一
方、図6は、図4のヒートシンク9を半導体ペレット4
を半田層5aを介して取付けた半導体装置の例を示す。
FIG. 5 shows an example of a semiconductor device in which the semiconductor pellet 4 is attached to the heat sink 3 of FIG. 3 via the solder layer 5a. In FIG. 5, reference numeral 6 denotes an aluminum radiation fin located on the outer peripheral portion of the heat sink 3. Further, 7 is a copper lead connected to the semiconductor pellet 4 via the solder layer 5b, 8
Is a protective layer made of silicon or epoxy resin. On the other hand, FIG. 6 shows the heat sink 9 of FIG.
An example of a semiconductor device in which is attached via a solder layer 5a is shown.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来技
術によれば、以下に述べる問題点を有する。
However, the conventional technique has the following problems.

【0006】(1) 図5の半導体装置の場合; 半導体ペレット4が放熱フィン6の打ち込み部に打ち込
まれる際、半導体ペレット4とヒートシンク3を接合し
ている半田層5aに絶えず歪が加わった状態となり、熱疲
労しやすい。このことは、熱疲労テスト(TFT)によ
り明らかであった。
(1) In the case of the semiconductor device of FIG. 5: When the semiconductor pellet 4 is driven into the driving portion of the heat radiation fin 6, the solder layer 5a joining the semiconductor pellet 4 and the heat sink 3 is constantly strained. It is easy to get heat fatigue. This was clear by the thermal fatigue test (TFT).

【0007】(2) 図6の半導体装置の場合; 図6は、図5の装置の問題点である熱疲労を解消するた
めに半導体ペレットの半田付面を凸状にし、放熱フィン
6の打ち込みで発生する歪を逃がした構造のものである
が、下記のような問題点を有する。
(2) In the case of the semiconductor device of FIG. 6; FIG. 6 shows that the soldering surface of the semiconductor pellet is made convex and the heat radiation fin 6 is driven in in order to eliminate the thermal fatigue which is a problem of the device of FIG. However, it has the following problems.

【0008】(イ)保護層9が流れ出ないように外周部
に壁を設ける必要があるが、その壁は高いため、ヒート
シンク9と一体で作ることができない。従って、図6に
示すように樹脂製リング10を別に準備する必要があり、
コスト高を招く。
(A) It is necessary to provide a wall on the outer peripheral portion so that the protective layer 9 does not flow out, but since the wall is high, it cannot be formed integrally with the heat sink 9. Therefore, it is necessary to separately prepare the resin ring 10 as shown in FIG.
Incurs high costs.

【0009】(ロ)上述したように樹脂製リング10を設
けるため、半導体ペレットの大きさが制限される。
(B) Since the resin ring 10 is provided as described above, the size of the semiconductor pellet is limited.

【0010】(ハ)ヒートシンク9の材料使用量が多く
なり、コスト高となる。
(C) The amount of material used for the heat sink 9 increases, resulting in higher cost.

【0011】本発明は上記事情に鑑みてなされたもの
で、ヒートシンクの半田付面をローレット加工面の上端
部より高くし、ヒートシンクの外周部の壁を半田付面よ
り高くし、かつ前記半田付面を外周に溝を有し凸状にす
ることにより、半導体ペレットをヒートシンクに打ち込
む際に発生する歪を逃し、半導体ペレットの性能低下を
抑制しうる半導体装置を提供することを目的とする。
The present invention has been made in view of the above circumstances, in which the soldering surface of the heat sink is higher than the upper end of the knurled surface, the wall of the outer peripheral portion of the heat sink is higher than the soldering surface, and the soldering is performed. An object of the present invention is to provide a semiconductor device in which the surface has a groove on the outer periphery and is convex so that the strain generated when the semiconductor pellet is driven into the heat sink can be released and the performance deterioration of the semiconductor pellet can be suppressed.

【0012】[0012]

【課題を解決するための手段】本発明は、外周側面にロ
ーレット加工を施した銅製円板状ヒートシンクを放熱フ
ィンに設け、更に前記ヒートシンクの半田付面に半導体
ペレットを取付けた半導体装置において、前記半田付面
がローレット加工面の上端部より高いとともに、ヒート
シンクの外周部の壁が半田付面より高く、かつ前記半田
付面は外周に溝を有し凸状になっていることを特徴とす
る半導体装置である。
The present invention provides a semiconductor device in which a copper disk-shaped heat sink having a knurled outer peripheral side surface is provided on a radiation fin, and a semiconductor pellet is attached to a soldering surface of the heat sink. The soldering surface is higher than the upper end of the knurled surface, the outer peripheral wall of the heat sink is higher than the soldering surface, and the soldering surface has a groove on the outer periphery and is convex. It is a semiconductor device.

【0013】[0013]

【作用】本発明においては、ヒートシンクの半田付面部
の突出度合を図4(従来例)の如く高くせず最小限に押
さえ、かつその不足分をその周辺に設けた溝によりカバ
ーすることにより、ヒートシンクを放熱フィンへ打ち込
む際に発生する歪を逃し、半導体ペレットへの悪影響を
防止でき、信頼性の高い半導体装置を得ることができ
る。
In the present invention, the degree of protrusion of the soldering surface portion of the heat sink is minimized without increasing it as shown in FIG. 4 (conventional example), and the shortage is covered by the groove provided around it. The strain generated when the heat sink is driven into the heat radiation fin can be released, the adverse effect on the semiconductor pellet can be prevented, and a highly reliable semiconductor device can be obtained.

【0014】[0014]

【実施例】以下、本発明の一実施例を図1を参照して説
明する。但し、従来と同部材は同符号を付して説明を省
略する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. However, the same members as those of the related art are denoted by the same reference numerals and the description thereof will be omitted.

【0015】本実施例に係る半導体装置は、ヒートシン
ク21に改良を施した点を特徴とする。即ち、ヒートシン
ク21の半田付面22がローレット加工面23の上端部Pより
高く、またヒートシンク21の外周部の壁が半田付面22よ
り高く、更に前記半田付面22は外周に溝24を有し凸状に
なった構成になっている。具体的には、例えばヒートシ
ンク21の外径(D)φ12.8mm、ローレット加工面のロー
レット数78P、半田付面部の径(d)φ7.0mm 、半田付
面22からの溝部の深さ(F)2.1mm 、溝部の底面からの
壁の高さ(H)が3.6mm である。なお、上記ローレット
加工面も図7に示すような形状となっている。
The semiconductor device according to this embodiment is characterized in that the heat sink 21 is improved. That is, the soldering surface 22 of the heat sink 21 is higher than the upper end portion P of the knurled surface 23, the outer peripheral wall of the heat sink 21 is higher than the soldering surface 22, and the soldering surface 22 has a groove 24 on the outer periphery. It has a convex configuration. Specifically, for example, the outer diameter (D) of the heat sink 21 is φ12.8 mm, the number of knurls on the knurled surface is 78 P, the diameter of the soldering surface portion (d) is φ7.0 mm, and the depth of the groove portion from the soldering surface 22 (F ) 2.1 mm, and the height (H) of the wall from the bottom of the groove is 3.6 mm. The knurled surface also has a shape as shown in FIG.

【0016】しかして、上記実施例に係る半導体装置に
よれば、ヒートシンク21について、半田付面部の突出度
合を図4(従来例)の如く高くせず最小限に押さえ、そ
の不足分をその周辺に設けた溝24によりカバーした構成
となっているため、ヒートシンク21を放熱フィン6へ打
ち込む際に発生する歪を逃し、半導体ペレットへの悪影
響を防止できる。
According to the semiconductor device of the above embodiment, however, the protrusion degree of the soldering surface of the heat sink 21 is minimized without increasing it as shown in FIG. Since the structure is covered by the groove 24 provided in the heat sink 21, the strain generated when the heat sink 21 is driven into the heat radiation fin 6 can be released, and the adverse effect on the semiconductor pellet can be prevented.

【0017】事実、図5の半導体装置(従来)の場合、
ヒートシンクの半田付面部の歪を測定したところ、圧縮
歪は1500〜2000μmとかなり大きかった。これに対し、
第1図の半導体装置(本発明)によれば、歪は10〜50μ
mと大幅に小さくなった。また、半導体の特性の熱疲労
テスト(TFT)では、2000〜6000以上と大幅に向上し
た。従って、本発明が従来技術に比べて優れていること
が明らかである。
In fact, in the case of the semiconductor device of FIG. 5 (conventional),
When the strain on the soldering surface of the heat sink was measured, the compressive strain was considerably large, 1500 to 2000 μm. In contrast,
According to the semiconductor device of the present invention shown in FIG. 1, the strain is 10 to 50 μm.
It was significantly reduced to m. Moreover, in the thermal fatigue test (TFT) of the characteristics of the semiconductor, it was significantly improved to 2000-6000 or more. Therefore, it is clear that the present invention is superior to the prior art.

【0018】[0018]

【発明の効果】以上詳述した如く本発明によれば、ヒー
トシンクの半田付面をローレット加工の上端部より高く
し、ヒートシンクの外周部の壁を半田付面より高くし、
かつ前記半田付面を外周に溝を有し凸状にすることによ
り、ヒートシンクの打ち込みで発生する歪を逃し、半導
体ペレットの性能を大幅に向上しうる半導体装置を提供
できる。
As described in detail above, according to the present invention, the soldering surface of the heat sink is made higher than the upper end portion of the knurling, and the wall of the outer peripheral portion of the heat sink is made higher than the soldering surface.
Moreover, by forming the soldering surface to have a convex shape with a groove on the outer periphery, it is possible to provide a semiconductor device in which the strain generated by driving the heat sink can be released and the performance of the semiconductor pellet can be significantly improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に係る半導体装置の断面図。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

【図2】図1の半導体装置に用いられるヒートシンクの
説明図。
FIG. 2 is an explanatory diagram of a heat sink used in the semiconductor device of FIG.

【図3】従来のヒートシンクの説明図。FIG. 3 is an explanatory diagram of a conventional heat sink.

【図4】従来のヒートシンクの説明図。FIG. 4 is an explanatory diagram of a conventional heat sink.

【図5】図3のヒートシンクを用いた半導体装置の断面
図。
5 is a sectional view of a semiconductor device using the heat sink of FIG.

【図6】図4のヒートシンクを用いた半導体装置の断面
図。
6 is a sectional view of a semiconductor device using the heat sink of FIG.

【図7】図3のヒートシンクのローレット部の説明図。FIG. 7 is an explanatory diagram of a knurled portion of the heat sink of FIG.

【符号の説明】[Explanation of symbols]

4…半導体ペレット、5a,5b…半田層、6…放熱フィ
ン、7…銅製リード、8…保護層、21…ヒートシンク、
22…半田付面、23…ローレット加工面。
4 ... Semiconductor pellet, 5a, 5b ... Solder layer, 6 ... Radiating fin, 7 ... Copper lead, 8 ... Protective layer, 21 ... Heat sink,
22… Soldering surface, 23… Knurled surface.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 外周側面にローレット加工を施した銅製
円板状ヒートシンクを放熱フィンに設け、更に前記ヒー
トシンクの半田付面に半導体ペレットを取付けた半導体
装置において、前記半田付面がローレット加工面の上端
部より高いとともに、ヒートシンクの外周部の壁が半田
付面より高く、かつ前記半田付面は外周に溝を有し凸状
になっていることを特徴とする半導体装置。
1. A semiconductor device in which a copper disk-shaped heat sink having a knurled outer peripheral surface is provided on a radiation fin, and a semiconductor pellet is attached to a soldering surface of the heat sink, wherein the soldering surface is a knurled surface. A semiconductor device characterized in that the wall of the outer peripheral portion of the heat sink is higher than the upper end portion and the wall of the outer peripheral portion is higher than the soldering surface, and the soldering surface has a groove on the outer periphery and is convex.
JP2407686A 1990-12-27 1990-12-27 Semiconductor device Expired - Lifetime JP2843684B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2407686A JP2843684B2 (en) 1990-12-27 1990-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2407686A JP2843684B2 (en) 1990-12-27 1990-12-27 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH05114678A true JPH05114678A (en) 1993-05-07
JP2843684B2 JP2843684B2 (en) 1999-01-06

Family

ID=18517242

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2407686A Expired - Lifetime JP2843684B2 (en) 1990-12-27 1990-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2843684B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331730B1 (en) 1998-04-23 2001-12-18 Hitachi, Ltd. Push-in type semiconductor device including heat spreader
US7235876B2 (en) * 2005-09-12 2007-06-26 Denso Corporation Semiconductor device having metallic plate with groove
DE10310067B4 (en) * 2002-03-08 2010-12-16 Hitachi, Ltd. Semiconductor device with a hollow cylindrical housing electrode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331730B1 (en) 1998-04-23 2001-12-18 Hitachi, Ltd. Push-in type semiconductor device including heat spreader
DE10310067B4 (en) * 2002-03-08 2010-12-16 Hitachi, Ltd. Semiconductor device with a hollow cylindrical housing electrode
US7235876B2 (en) * 2005-09-12 2007-06-26 Denso Corporation Semiconductor device having metallic plate with groove

Also Published As

Publication number Publication date
JP2843684B2 (en) 1999-01-06

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