JPH0511415B2 - - Google Patents

Info

Publication number
JPH0511415B2
JPH0511415B2 JP60061693A JP6169385A JPH0511415B2 JP H0511415 B2 JPH0511415 B2 JP H0511415B2 JP 60061693 A JP60061693 A JP 60061693A JP 6169385 A JP6169385 A JP 6169385A JP H0511415 B2 JPH0511415 B2 JP H0511415B2
Authority
JP
Japan
Prior art keywords
oxygen
defects
donor
concentration
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60061693A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61220339A (ja
Inventor
Yoichi Mada
Kazumi Wada
Naohisa Inoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP60061693A priority Critical patent/JPS61220339A/ja
Publication of JPS61220339A publication Critical patent/JPS61220339A/ja
Publication of JPH0511415B2 publication Critical patent/JPH0511415B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10P36/03—

Landscapes

  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
JP60061693A 1985-03-26 1985-03-26 半導体材料特性の制御方法 Granted JPS61220339A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60061693A JPS61220339A (ja) 1985-03-26 1985-03-26 半導体材料特性の制御方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60061693A JPS61220339A (ja) 1985-03-26 1985-03-26 半導体材料特性の制御方法

Publications (2)

Publication Number Publication Date
JPS61220339A JPS61220339A (ja) 1986-09-30
JPH0511415B2 true JPH0511415B2 (cg-RX-API-DMAC10.html) 1993-02-15

Family

ID=13178584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60061693A Granted JPS61220339A (ja) 1985-03-26 1985-03-26 半導体材料特性の制御方法

Country Status (1)

Country Link
JP (1) JPS61220339A (cg-RX-API-DMAC10.html)

Families Citing this family (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6993222B2 (en) 1999-03-03 2006-01-31 Rj Mears, Llc Optical filter device with aperiodically arranged grating elements
GB2385943B (en) 1999-03-05 2003-11-05 Nanovis Llc Mach-Zehnder interferometer with aperiodic grating
JP4659300B2 (ja) 2000-09-13 2011-03-30 浜松ホトニクス株式会社 レーザ加工方法及び半導体チップの製造方法
TWI326626B (en) 2002-03-12 2010-07-01 Hamamatsu Photonics Kk Laser processing method
KR100848408B1 (ko) 2002-03-12 2008-07-28 하마마츠 포토닉스 가부시키가이샤 기판의 분할 방법
TWI520269B (zh) 2002-12-03 2016-02-01 濱松赫德尼古斯股份有限公司 Cutting method of semiconductor substrate
US6958486B2 (en) 2003-06-26 2005-10-25 Rj Mears, Llc Semiconductor device including band-engineered superlattice
US6878576B1 (en) 2003-06-26 2005-04-12 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US7202494B2 (en) 2003-06-26 2007-04-10 Rj Mears, Llc FINFET including a superlattice
US7535041B2 (en) 2003-06-26 2009-05-19 Mears Technologies, Inc. Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7531850B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a memory cell with a negative differential resistance (NDR) device
US7659539B2 (en) 2003-06-26 2010-02-09 Mears Technologies, Inc. Semiconductor device including a floating gate memory cell with a superlattice channel
US7531828B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US7229902B2 (en) 2003-06-26 2007-06-12 Rj Mears, Llc Method for making a semiconductor device including a superlattice with regions defining a semiconductor junction
US7514328B2 (en) 2003-06-26 2009-04-07 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetween
US7531829B2 (en) 2003-06-26 2009-05-12 Mears Technologies, Inc. Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistance
US7045377B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7491587B2 (en) 2003-06-26 2009-02-17 Mears Technologies, Inc. Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layer
US7586116B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Semiconductor device having a semiconductor-on-insulator configuration and a superlattice
US7586165B2 (en) 2003-06-26 2009-09-08 Mears Technologies, Inc. Microelectromechanical systems (MEMS) device including a superlattice
WO2005018005A1 (en) 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice
US7446002B2 (en) 2003-06-26 2008-11-04 Mears Technologies, Inc. Method for making a semiconductor device comprising a superlattice dielectric interface layer
US7598515B2 (en) 2003-06-26 2009-10-06 Mears Technologies, Inc. Semiconductor device including a strained superlattice and overlying stress layer and related methods
US7612366B2 (en) 2003-06-26 2009-11-03 Mears Technologies, Inc. Semiconductor device including a strained superlattice layer above a stress layer
US7227174B2 (en) 2003-06-26 2007-06-05 Rj Mears, Llc Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junction
US7045813B2 (en) 2003-06-26 2006-05-16 Rj Mears, Llc Semiconductor device including a superlattice with regions defining a semiconductor junction
US7517702B2 (en) 2005-12-22 2009-04-14 Mears Technologies, Inc. Method for making an electronic device including a poled superlattice having a net electrical dipole moment
US7700447B2 (en) 2006-02-21 2010-04-20 Mears Technologies, Inc. Method for making a semiconductor device comprising a lattice matching layer
US7781827B2 (en) 2007-01-24 2010-08-24 Mears Technologies, Inc. Semiconductor device with a vertical MOSFET including a superlattice and related methods
US7928425B2 (en) 2007-01-25 2011-04-19 Mears Technologies, Inc. Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methods
US7880161B2 (en) 2007-02-16 2011-02-01 Mears Technologies, Inc. Multiple-wavelength opto-electronic device including a superlattice
US7863066B2 (en) 2007-02-16 2011-01-04 Mears Technologies, Inc. Method for making a multiple-wavelength opto-electronic device including a superlattice
US7812339B2 (en) 2007-04-23 2010-10-12 Mears Technologies, Inc. Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structures
WO2015077580A1 (en) 2013-11-22 2015-05-28 Mears Technologies, Inc. Semiconductor devices including superlattice depletion layer stack and related methods
WO2015077595A1 (en) 2013-11-22 2015-05-28 Mears Technologies, Inc. Vertical semiconductor devices including superlattice punch through stop layer and related methods
WO2015191561A1 (en) 2014-06-09 2015-12-17 Mears Technologies, Inc. Semiconductor devices with enhanced deterministic doping and related methods
US9722046B2 (en) 2014-11-25 2017-08-01 Atomera Incorporated Semiconductor device including a superlattice and replacement metal gate structure and related methods
WO2016187042A1 (en) 2015-05-15 2016-11-24 Atomera Incorporated Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods
WO2016196600A1 (en) 2015-06-02 2016-12-08 Atomera Incorporated Method for making enhanced semiconductor structures in single wafer processing chamber with desired uniformity control
US9558939B1 (en) 2016-01-15 2017-01-31 Atomera Incorporated Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source
TWI723262B (zh) 2017-05-16 2021-04-01 美商安托梅拉公司 包含超晶格作為吸除層之半導體元件及方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5638828A (en) * 1979-09-07 1981-04-14 Sony Corp Manufacture of semiconductor device
JPS5740939A (en) * 1980-08-25 1982-03-06 Fujitsu Ltd P-n junction formation

Also Published As

Publication number Publication date
JPS61220339A (ja) 1986-09-30

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