JPH05111136A - Erroneous operation preventing device for electronic apparatus - Google Patents

Abstract

PURPOSE:To prevent damage to a load by stopping conduction to a load for a specified time or more when a malfunction occurs in a conduction signal due to an erroneous operation in a conduction controller. CONSTITUTION:The erroneous operation preventing device for an which outputs electronic apparatus comprises a time counter circuit G a conduction signal only for a conducting time, and a time monitor circuit F which inputs the signal output from the counter, counts the time at each inputting of the signal add outputs a power stop signal when it counts the time over a preset conduction allowable time. A three-terminal input NOR circuit 44 and a second AND circuit 54 for tuning OFF both a P-N-P transistor 32 and an N-P-N transistor 33 for controlling a conduction of a heat generating resistor of a printing head according to the stop signal output from the monitor F are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a malfunction preventing device for an electronic device which stops energization of a load when an abnormality occurs in an energization signal energized for a set energization time.

[0002]

2. Description of the Related Art In an electronic apparatus such as an ink jet printer, a print head of a cartridge type is designed so that printing is performed by energizing a heating resistor provided in the print head for a predetermined energizing time. It has become.

For example, the one shown in FIG. 3 is known. 1
Is a heating resistor of the print head. A PNP transistor 2 for power supply is provided between the heating resistor 1 and the 25V power supply.
, And an NPN transistor 3 for controlling energization is connected between the heating resistor 1 and the ground. Resistors 4 and 5 are connected between the base terminal and the emitter terminal of the transistors 2 and 3, respectively.
Further, a capacitor 6 for preventing overvoltage on the heating resistor 1 is connected between the connection point of the heating resistor 1 to which the collector terminal of the PNP transistor 2 is connected and the ground.

A power supply control signal (vcont) from the conduction control circuit B is input to the base terminal of the PNP transistor 2 through a series circuit of a first diode 7 and a resistor 8, and the NPN transistor 3 has a base terminal. An energization signal (vout) from the energization control circuit B is input to the base terminal via a series circuit of the second diode 9 and the resistor 10. The second diode 9 and the resistor 10
The intermediate connection point of the series circuit of is connected to the 5V power source through the resistor 11. The above is the configuration of the circuit of the cartridge A.

The energization control circuit B is a control unit body (CPU
(Central processor unit), ROM (read only memo
ry), I / O (input / output), etc. (Not shown)
It operates by inputting the control signal from the control signal, which is the power-on signal (von), power-off signal (voff), clock signal (clk), enable signal (enable), reset signal. (Reset).

The power-on signal is the first inverter circuit 12
Is input to the reset (R) terminal of the first flip-flop circuit 13 via. The power-off signal is input to one input terminal of the first NOR circuit 14. A reset signal is input to the other input terminal of the first NOR circuit 14, and its output terminal is connected to the set (S) terminal of the first flip-flop circuit 13. The clock (C) terminal and the data (D) terminal of the first flip-flop circuit 13 are both connected to a 5V power supply, and the power supply control signal (vcont) is output from its output (negative logic output Q) terminal. .. This power supply control signal is input to the cartridge A via the first buffer circuit (collector open) 15 and, as described above, the P
It is adapted to be input to the base terminal of the NP type transistor 2. The clock signal, the enable signal, and the reset signal are input to the time counting circuit C, and the energization signal (vout) is output from the time counting circuit C.

The time counting circuit C is composed of a second NOR circuit 16, a second flip-flop circuit 17, a counter circuit 18, and an AND circuit 19. The clock signal is input to the clock (CLK) terminal of the counter circuit 18 and is also input to the clock (C) terminal of the second flip-flop circuit 17 via the second inverter circuit 20. The enable signal is input to one input terminal of the AND circuit 19 and
It is input to the second NOR circuit 16 via the third inverter circuit 21. The reset signal is input to the clear (CLR) terminal of the counter circuit 18 and also to the reset (R) terminal of the second flip-flop circuit 17 via the fourth inverter circuit 22. ing. The carry-out (CO) terminal of the counter circuit 18 is connected to the data (D) terminal of the second flip-flop circuit 17, and the other one of the AND circuits 19 is connected via the fifth inverter circuit 23. It is connected to the input terminal. The output (negative logic output Q) terminal of the second flip-flop circuit 17 is connected to the remaining one input terminal of the second NOR circuit 16, and its set (S) terminal is connected to the 5V power source. . The output terminal of the second NOR circuit 16 is connected to the input (LD) terminal of the counter circuit 18. The counter circuit 18 has a first data (D0) terminal,
A second data (D1) terminal, a third data (D2) terminal, and a fourth data (D3) terminal are provided, and the first, second, and fourth data terminals are connected to a 5V power source, The third data terminal is connected to ground. The energization time is set by the wiring settings of these data terminals.

An energization signal (vout) is output from the output terminal of the AND circuit 19, and this energization signal is input to the cartridge A via the second buffer circuit (collector open) 24, as described above. And is input to the base terminal of the NPN transistor 3.

FIG. 4 shows the timing of each signal described above. First, when the reset signal (reset) becomes low level and the power-on signal (von) is output as one pulse, the power supply control signal (vcont) becomes low level and the PNP transistor 2 is turned on and the power-on state is established. become. When one pulse of the power-off signal (voff) is output, the power-supply control signal becomes high level, the PNP transistor 2 is turned off, and the power is turned off.

When the enable signal (enable) is output, the counter circuit 18 and the second flip-flop circuit 17 output a pulse signal for a predetermined time to the counter circuit 18.
Output from the carry-out (CO) terminal of the AND circuit 19, the output pulse signal is input to the other input terminal of the AND circuit 19, and the energization signal (vo
ut) is output. Therefore, the NPN transistor 3 is turned on / off, and the heating resistor 1 is energized for a predetermined energization time.

[0011]

Conventionally, due to a malfunction of the counter circuit 18 of the time counting circuit C or the flip-flop circuit 17, etc., the energizing signal (vout) maintains a high level for a prescribed time or longer, and the heating resistor is When a current is applied to the heat generating resistor 1 for a specified time or longer, there is a problem that the print head including the heat generating resistor 1 is damaged due to excessive heat generation of the heat generating resistor 1.

As shown in the above-mentioned example of the ink jet printer, when the load of the electronic device is energized for a specified time or longer, there is a problem that the load may be damaged due to heat generation or the like.

Therefore, according to the present invention, when an abnormality occurs in the energization signal due to a malfunction in the energization controller, the load is prevented from being damaged by stopping the energization of the load for a predetermined time or longer to prevent the malfunction of the electronic device. The purpose is to provide.

[0014]

SUMMARY OF THE INVENTION The present invention is provided with an energization signal output means for setting an energization time to a load and outputting an energization signal to the load only for the energization time. In a malfunction prevention circuit of an electronic device that stops energizing the load when an abnormality occurs, the energizing signal output from the energizing signal output means inputs the energizing signal and the energizing signal output means outputs the energizing signal. When the energization time is newly exceeded for each input of the energization signal, the energization time monitoring means and the energization time measured by the energization time monitoring means exceed the preset allowable energization time, and the load is energized. An energization stopping means for stopping is provided.

[0015]

In the present invention having such a configuration, the energization signal is output by the energization signal output means for the set energization time. The energization time monitoring means inputs the output energization signal and newly measures the energization time during which the energization signal is output by the energization signal output means every time the energization signal is input. When the energization time measured by the energization time monitoring means exceeds the preset allowable energization time, the energization stopping means stops energization of the load.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to an ink jet printer, and FIG. 1 shows a circuit configuration of a main part around a print head of the ink jet printer.

The circuit configuration of the print head cartridge D is composed of a heat generating resistor 31 of the print head as a load, a PNP transistor 32 for power supply and an NPN transistor 33 for controlling energization. The PNP transistor 32 is connected between the 25V power supply and the NPN transistor 33 is connected between the heating resistor 31 and the ground. Resistors 34 and 35 are connected between the base and emitter terminals of the transistors 32 and 33, respectively. Further, a capacitor 36 for preventing overvoltage on the heating resistor 31 is connected between the ground of the heating resistor 31 to which the collector terminal of the PNP transistor 32 is connected and the ground.

A power control signal (vcont) from the energization control circuit E is applied to the base terminal of the PNP transistor 32.
Is inputted via a series circuit of a first diode 37 and a resistor 38, and a conduction signal (vout) from a conduction control circuit E is supplied to a base terminal of the NPN transistor 33 of the second diode 39 and the resistor 40. It is designed to be input via a series circuit. The intermediate connection point of the series circuit of the second diode 39 and the resistor 40 is connected to the 5V power source via the resistor 41.

The energization control circuit E includes a control unit main body (CPU,
It consists of ROM, I / O, etc. It operates by inputting a control signal from a power-on signal (von) and power-off signal (vof).
f), clock signal (clk), enable signal (enabl
e) and a reset signal (reset).

The power-on signal is supplied to the first inverter circuit 4
2 is input to the reset (R) terminal of the first flip-flop circuit 43. The power-off signal is input to one input terminal of the NOR circuit 44 having a three-terminal input as a means for stopping energization. The reset signal and the power stop signal (vs from the time monitoring circuit F as the energization time monitoring means are supplied to the other input terminals of the NOR circuit 44 for three-terminal input.
Top) is converted to negative logic and the signal is designed to be input. The output terminal of the NOR circuit 44 for three-terminal input is connected to the set (S) terminal of the first flip-flop circuit 43. The clock (C) terminal and the data (D) terminal of the first flip-flop circuit 43 are both connected to a 5V power source, and a power supply control signal (vcont) is output from the output (negative logic output Q) terminal thereof. .. This power supply control signal is the first buffer circuit (collector open)
It is input to the cartridge D via 45 and is input to the base terminal of the PNP transistor 32 as described above. The clock signal, the enable signal and the reset signal are input to the time monitoring circuit F and the time counting circuit G as an energization signal output means.

The time counting circuit G is composed of a second NOR circuit 46, a second flip-flop circuit 47, a first counter circuit 48, and a first AND circuit 49. The clock signal is input to the clock (CLK) terminal of the first counter circuit 48 and is also input to the clock (C) terminal of the second flip-flop circuit 47 via the second inverter circuit 50. There is. The enable signal is input to one input terminal of the first AND circuit 49 and is also input to the second NOR circuit 46 via the third inverter circuit 51. The reset signal is used to clear (C) the first counter circuit 48.
It is also input to the reset (R) terminal of the second flip-flop circuit 47 via the fourth inverter circuit 52.

The carry-out (CO) terminal of the first counter circuit 48 is connected to the data (D) terminal of the second flip-flop circuit 47, and the carry-out (CO) terminal of the second flip-flop circuit 47 is connected via the fifth inverter circuit 53. It is connected to the remaining one input terminal of the AND circuit 49 of 1. The output (negative logic output Q) terminal of the second flip-flop circuit 47 is
It is connected to the remaining one input terminal of the second NOR circuit 46, and its set (S) terminal is connected to the 5V power source. The output terminal of the second NOR circuit 46 is connected to the first terminal.
Of the counter circuit 48 is connected to the input (LD) terminal. The first counter circuit 48 is provided with a first data (D0) terminal, a second data (D1) terminal, a third data (D2) terminal, and a fourth data (D3) terminal. The first, second, and fourth data terminals are connected to the 5V power source, and the third data terminal is connected to the ground. The energization time is set by the wiring settings of these data terminals. The output terminal of the first AND circuit 49 is
It is connected to one input terminal of the second AND circuit 54 as an energization stopping means.

The time monitoring circuit F is composed of a third NOR circuit 55, a third flip-flop circuit 56 and a second counter circuit 57. The clock signal is input to the clock (CLK) terminal of the second counter 57, the enable signal is input via the third inverter circuit 51 of the time counting circuit G, and one of the third NOR circuits 55 is input. It is input to the input terminal. The reset signal is input to the clear (CLR) terminal of the second counter 57 and reset (R) of the third flip-flop circuit 56 via the fourth inverter circuit 52 of the time counting circuit G. It is input to the terminal.

The carry-out (CO) terminal of the second counter circuit 57 outputs a power stop signal (vstop), and the power stop signal is input to the set (S) terminal of the third flip-flop circuit 56. And the NOR circuit 4 of the three-terminal input via the sixth inverter 58.
4 are input to the other one input terminal. The data (D) terminal and the clock (C) terminal of the third flip-flop circuit 56 are both connected to a 5V power source, and the output (negative logic output Q) terminal thereof is one of the remaining input terminals of the second AND 54. It is connected to the.

An energization signal (vout) is output from the output terminal of the second AND circuit 54, and the energization signal is passed through the second buffer circuit (collector open) 59 and further to the third buffer circuit 60 and the third buffer circuit 60. It is input to the remaining one input terminal of the second NOR circuit 55 through a series circuit with the No. 7 inverter circuit 61. The output terminal of the second NOR circuit 55 is connected to the input (LD) terminal of the second counter circuit 57. The second counter circuit is provided with a first data (D0) terminal, a second data (D1) terminal, a third data (D2) terminal, and a fourth data (D3) terminal, The first and fourth data terminals are connected to a 5V power source, and the second and third data terminals are connected to ground. The energization allowable time is set by setting the wiring of these data terminals.

The energization signal from the output terminal of the second AND circuit 54 is input to the cartridge D via the second buffer circuit 59, and is input to the base terminal of the NPN transistor 33 as described above. It has become so.

FIG. 2 shows the timing of various signals in this embodiment having such a configuration. First, the reset signal (re
set) becomes low level and one pulse of the power-on signal (von) is output, the power-supply control signal (vcont) becomes low level and the PNP transistor 32 is turned on to be in a conductive state. When one pulse of the power off signal (voff) is output, the power control signal is at a high level (not shown).
Then, the PNP transistor 32 is turned off and becomes non-conductive.

When the enable signal (enable) is output, a pulse signal of a predetermined time is output from the carry-out (CO) terminal of the first counter circuit 48 by the first counter circuit 48 and the second flip-flop circuit 47. The output pulse signal is output and input to the remaining one input terminal of the first AND circuit, and the first AND circuit 49
A pulse signal is input from one output terminal of the second AND circuit 54 to one input terminal of the second AND circuit 54, and an energization signal (vout) is output from the output terminal of the second AND circuit 54. Therefore, N
The PN transistor 33 is turned on / off, and the heating resistor 31 is energized for a predetermined energizing time.

If there is a malfunction in the time counting circuit G and the high level continues to be maintained even after the energization time for which the energization signal has been set, as at time point X shown in FIG. When the lapse of the energization allowable time is counted by the second counter 57 that starts counting at the rising edge, a low level is output to the power stop signal (vstop) from the carry-out terminal at the time point Y. Then, the sixth buffer circuit 58 and the three-terminal input N
OR circuit 44, first flip-flop circuit 43, first
Through the buffer circuit 45 of the PNP transistor 3
2 is turned off, the third flip-flop circuit 56, the second AND circuit 54, and the second buffer circuit 59 are turned on.
The NPN transistor 33 is turned off via
Energization of the heating resistor 31 is stopped.

As described above, according to this embodiment, when an abnormality occurs in the energization signal (vout) due to a malfunction in the time counting circuit G for controlling the energization time, the energization signal is input to measure the energization allowable time. By providing the time monitoring circuit F, a power stop signal (vstop) is output, and the transistors 32 and 33 for supplying power are both turned off.
The power supply to the heating resistor 31 of the print head is stopped. Therefore, the heating resistor does not generate excessive heat, and damage to the print head can be prevented.

In this embodiment, the energization control circuit for the print head of the ink jet printer has been described. However, the present invention is not limited to the ink jet printer and can be applied to circuits for energization control in general electronic equipment. Is.

[0032]

As described in detail above, according to the present invention,
It is possible to provide a malfunction prevention device for an electronic device that can prevent the load from being damaged by stopping energization of the load for a specified time or longer when an abnormality occurs in the energization signal due to a malfunction in the power distribution control unit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of essential parts showing an embodiment of the present invention.

FIG. 2 is a diagram showing timings of various signals in the embodiment.

FIG. 3 is a main part circuit diagram showing a conventional example.

FIG. 4 is a diagram showing timings of various signals in a conventional example.

[Explanation of symbols]

D ... Cartridge, E ... Energization control circuit, F ... Time monitoring circuit, G ... Time counting circuit, 44 ... 3-terminal input NOR circuit, 54 ... Second AND circuit.

Claims (1)

[Claims] 1. An energization signal output means for setting an energization time to a load and outputting an energization signal to the load only for the energization time, wherein when an abnormality occurs in the energization signal from the energization signal output means In a malfunction prevention circuit of an electronic device that stops energization of a load, the energization signal output from the energization signal output means to the load is input, and the energization time during which the energization signal is output by the energization signal output means The energization time monitoring means newly measures each time the energization signal is input, and the energization to the load is stopped when the energization time measured by the energization time monitoring means exceeds the preset allowable energization time. An apparatus for preventing malfunction of electronic equipment, comprising: