JPH05110634A - Multiple input specific pattern detection circuit - Google Patents

Abstract

PURPOSE:To decrease a circuit scale even when the number of data transmitters is large and to allow the circuit to easily cope with even the revision of the number of bits for an equipment diagnosis and of a bit pattern. CONSTITUTION:A ROM 3-11 is provided with various kinds of a simulating counter function, a comparison collation function between an equipment diagnostic bit and its expected value and a simulating backward/forward protection function. The multi-input specific pattern detection circuit using the ROM 3-11 as a major component is easily obtained by acting various data (part of data is outputted to the ROM 3-11 via a read data latch circuit 3-12) together with data (including equipment diagnostic bits) from data transmitters 11-1n onto the ROM 3-11 as a read address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention receives serial data in a bit phase synchronization state from each of data transmission devices as a large number of data transmission sources at a data transmission destination, and further, a predetermined bit is included in the data. Device diagnostic bits inserted at several intervals, the multi-input specific pattern detection circuit for intensively monitoring and detecting whether or not a predetermined bit pattern appears in a time corresponding to the frame period, In particular, the present invention relates to a multi-input specific pattern detection circuit in which a ROM has a function of comparing and collating a device diagnostic bit with an expected value.

[0002]

2. Description of the Related Art In some cases, serial digital data from each of a large number of data transmitters is centrally received at a data destination and then multiplexed or intensively processed. Based on the device diagnostic bits previously inserted with a predetermined bit pattern in the digital data from each data transmission device, whether each data transmission device is operating normally, or whether these digital data are data It is necessary to monitor and detect whether or not some trouble has occurred in the circuit operation including the transmission path until the signal is received by the transmission destination.

FIG. 6 shows an example of the configuration of a specific pattern detection circuit according to the prior art for monitoring and detecting whether or not any trouble has occurred in the circuit operation based on the device diagnostic bit. It is a thing. In this case, in each of the data transmission devices 11 to 1n, serial digital data is transmitted from the output interface circuits 11-2 to 1n-2 to the data transmission destination 3 at the same speed. Is the device diagnostic bit S _{1 in the} serial digital data.
On to S ₄ is inserted into a predetermined, yet adapted to be transmitted with a phase-locked state. Such a transmission mode of the data in the phase synchronization state is possible by the synchronization control by the synchronization control device 2. In the synchronization control device 2,
A reference bit clock signal having a bit cycle is created by the bit clock creation circuit 2-1 and the frame pulse signal is created by further dividing the reference bit clock signal by the frame pulse creation circuit 2-2 to an appropriate frame cycle T. However, by distributing the reference bit clock signal and the frame pulse signal to each of the data transmitters 11 to 1n, the serial digital data of the frame period T has a predetermined number of bit intervals (the period is T).
/ 4), the device diagnostic bits S _{1 to} S ₄ are sequentially inserted from the diagnostic bit insertion circuits 11-1 to 1n-1 so as to form a predetermined bit pattern.

On the other hand, at the data transmission destination 3, the device diagnostic bit is removed from the serial digital data from each of the data transmission devices 11 to 1n, and the multiplexing circuit 3-1 is used.
Bit multiplexing processing is carried out to obtain a multiplexed output OUT. In parallel with this multiplexing processing, the device diagnostic bits S _{1 to} S ₄ are specified in the serial digital data (received data). It is monitored whether or not the bit pattern appears. The reference bit clock signal and the frame pulse signal from the synchronization control device 2 are also distributed to the data transmission destination 3. From these signals, the detection clock generation circuit 3-10 inserts them into the serial digital data. Device diagnostic bit S
The positions of _{1 to} S ₄ are known. In this example, it is assumed that four device diagnostic bits appear within one frame period T, and the detection clock generation circuit 3-10 obtains the detection clock for each ¼ frame period T. It is supposed to be. At the timing of this detection clock, it is monitored and detected whether or not the device diagnostic bits S _{1 to} S ₄ appear with a predetermined bit pattern.

That is, the device diagnostic bit pattern of 4 bits is stored in the register 3-2 as an expected value, which is stored in the register 1 through the parallel / serial conversion circuit 3-3.
Every / 4 frame period T, one bit is obtained in a predetermined order in synchronization with the detection clock. Diagnostic bits S _{1 to} S ₄ as expected values, which are sequentially obtained from the parallel / serial conversion circuit 3-3 at every 1/4 frame period T.
Each of the serial digital data from each of the data transmitters 11 to 1n is compared with each of the exclusive OR gates 3-4-1 to 3-4-n to determine the state of the diagnostic bit and the serial digital data. The state is determined. In this example, the NOR gate 3-6 detects a full match between the state of the diagnostic bit and each state of the serial digital data, and the OR gate 3-5 detects a non-full match. In case of a complete match, counter 3-8,
In the case of non-full match, the counters 3-7 are set to the count enable (CE) state. By the way, the counters 3-7 and 3-8 are for detection only when they are in the count enable (CE) state after they are reset by the frame pulse signal (reset is performed by the rising differential pulse of the frame pulse signal). It is configured to count clocks. Therefore, when the counter 3-7 can once count a fixed number (the value is assumed to be 4 in this example) of the detection clock, the RS flip-flop 3-9
, While the alarm signal ALM is generated, the counter 3-8 can count a fixed number (the value is assumed to be 4 in this example) of the detection clock in a certain frame after that. It is supposed to be released for the first time in case of. Therefore, by monitoring the alarm signal ALM, it includes whether or not each of the data transmission devices 11 to 1n is normally operating, or the transmission path until the digital data is received by the data transmission destination. It is easily known whether or not some trouble has occurred in the circuit operation. FIG. 7 shows the timing for explaining the pattern detection circuit operation at the destination 3.
Since this is clear from the above description, further description is not particularly required. As a technique related to this type, for example, JP-A-1-293725 is known.

[0006]

However, in the above-mentioned prior art, no consideration is given to downsizing of the specific pattern detection circuit, and it cannot be denied that the circuit scale increases as the number of data transmission devices increases. It is not there. Further, it is not possible to easily deal with the change in the number of bits for device diagnosis and the change of the bit pattern. It is an object of the present invention to suppress the circuit scale to a small one even when the number of data transmitting devices is large, and to easily deal with a change in the number of bits for device diagnosis and its bit pattern. It provides a pattern detection circuit.

[0007]

SUMMARY OF THE INVENTION The above-mentioned object is to have at least a pseudo counter function according to an external read address, a function of comparing and collating a device diagnostic bit with an expected value, and a pseudo backward / forward protection function. ROM, a latch signal generating means for generating a latch signal in synchronization with the output time of each device diagnostic bit, and a read data holding means for holding read data from the ROM by the latch signal from the signal generating means. The device diagnosis bit group, various pseudo counter reset frame pulses, and held output data from the read data holding means are stored in the ROM.
This can be achieved by configuring the input address as a read address to.

[0008]

By storing necessary data in the ROM in advance, it is possible to provide at least various pseudo counter functions, a function for comparing and collating device diagnostic bits with expected values, and a pseudo rear / forward protection function. It was done. Therefore, by causing various data (some data is the ROM output of some data) to act as a read address from the outside for the ROM having such a function, the multi-input identification with the ROM as a main constituent element is performed. The pattern detection circuit can be easily obtained. When the number of bits for device diagnosis or the change of the bit pattern is changed, a ROM corresponding thereto can be used to easily cope with such a change.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to FIGS. Before specifically explaining the present invention, the operating principle of the ROM according to the present invention will be briefly described. FIG. 4 shows the basic operation principle as a counter. In this case, assuming that the ROM is operated as a quaternary counter, the address "00",
Data "01", "10", "11", and "00" must be stored in advance for "01", "10", and "11", respectively. The read data from the ROM acts on the ROM as a next read address via the read data holding means (temporary storage means). In the initial state, for example, “00” is output as read data from the read data holding unit.
If this acts as a read address for the ROM, then R
"01" is obtained as read data from the OM. This read data “01” is read as the read address for the next time through the read data holding means.
If it acts on M, it reads out "1" from the ROM.
0 "is read out. Therefore, the read data from the ROM is used as the address data for the next time in the ROM.
If you want to feed back to the
Can be made to function as a counter. By the way,
FIG. 5 shows the principle of the error detection operation, which will be described later.

Now, the present invention will be described in detail. FIG. 1 shows a configuration of an example of a specific pattern detection circuit according to the present invention together with its peripheral circuits or peripheral devices. In this case, a substantial difference from that shown in FIG. 6 is that the transmission destination 3 is provided with a multiplexing circuit 3-1 and a detection clock generation circuit 3-10 having the same functions as those shown in FIG. However, in addition to these, the ROM 3-11 and the read data holding circuit 3-12 are slightly newly provided. In this case, the ROM 3-11 is shown as a circuit function for simplification of the function description, but as will be understood from this, most of the functions as the multi-input specific pattern detection circuit (expected value position counter (expected value) (For update) 3-11-1, Expected value memory 3-11-2,
The comparison / collation circuit 3-11-3, the error counter 3-11-4, and the protection circuit 3-11-5) are collectively replaced by the ROM 3-11. As shown in FIG. 3, the read address (input address) for the ROM 3-11 is A ₀ (alarm ALM), A ₁ A ₂ (error count value), A ₃ A ₄ (expected value position count value), A ₅ (Frame pulse signal) and A _{6 to} A _{6 + n-1} (device diagnostic bits), the read data (output data) from the ROM 3-11 is D ₀ (alarm), D ₁ D ₂ (Error count value) and D ₃ D ₄ (expected value position count value) are temporarily held in the read data holding circuit 3-12 by the detection clock from the detection clock generation circuit 3-10, and The read address is fed back to the ROM 3-11 as much as possible.

As described above, the multi-input specific pattern detection circuit operates as a whole by inputting the read address to the ROM 3-11. FIG. 2 shows the operation flow in the ROM 3-11. Is. The operation will be described below. When the frame pulse signal A ₅ is input as a part of the read address,
The expected value position counter 3-11-1 and the error counter 3-11-4 are unconditionally reset and both count values are initialized to "0". The value and each of the input data (received data) are sequentially compared and collated, and the comparison and collation result is valid only at the timing of the detection clock signal. This is because the input data at the timing of the detection clock signal corresponds to the device diagnostic bit. When the comparison and collation result is an error (non-full match), the error counter 3-11-4 is incremented, while the expected value position counter 3-11-1 is incremented regardless of the comparison and collation result. It is supposed to be done. As long as the value of the expected value position counter 3-11-1 does not reach the number of device diagnostic bits in one frame, the above processing is repeated at the timing of the detection clock signal. Eventually, the value of the expected value position counter 3-11-1 reaches the number of device diagnostic bits in one frame, but at this point the number of error occurrences in that frame is fixed. The number of occurrences is first compared with a reference value for generating the alarm ALM. If the number of occurrences is equal to or greater than the reference value, the alarm ALM is generated for the first time and the next frame pulse signal is prepared for input. Is becoming If the number of error occurrences in the frame is less than the reference value and is not 0, no processing is performed to prepare for the input of the next frame pulse signal, but the error in the frame When the number of occurrences is 0, if the alarm ALM has been generated by then, the alarm ALM is canceled for the first time. Therefore, when the alarm ALM is once issued, the alarm ALM is canceled only when the number of error occurrences is 0 in a certain subsequent frame. The generation of such alarm ALM and its cancellation are managed by the protection circuit 3-11-5 based on the count value from the error counter 3-11-4.

Finally, referring to FIG. 5, the principle of the error detection operation will be described. Since the appearance pattern of the device diagnostic bits is known in advance, the expected value position counter 3-11
An error can be detected from the relationship between the count value A ₃ A _{4 of} -1 and each device diagnostic bit. In the example shown in FIG. 5, "0" is set as the first device diagnostic bit in the frame.
Is assumed to occur, the error counter 3-11-4 is incremented as if an error has occurred unless all the device diagnostic bits from the data transmission devices 11 to 1n are "0". It is supposed to be done. Since "1" is assumed as the state of the next device diagnostic bit, an error has occurred unless all the device diagnostic bits from the data transmission devices 11 to 1n are "1". As a matter of fact, the error counter 3-11-4 is incremented. Thereafter, similarly, it is detected whether or not an error has occurred in the device diagnostic bit in the frame, and the error counter 3 is detected each time the error is detected.
-11-4 is incremented, but when all the device diagnostic bits appear in the frame, the count value of the error counter 3-11-4 is determined as described in the flow shown in FIG. As a result, whether or not the alarm ALM is generated is controlled.

[0013]

As described above, according to the present invention, the circuit scale can be kept small even when the number of data transmission devices is large, and the number of bits for device diagnosis and its bit pattern can be changed. Therefore, a multi-input specific pattern detection circuit that can easily cope with the above situation can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an example of a specific pattern detection circuit according to the present invention together with its peripheral circuits or peripheral devices.

FIG. 2 is a diagram showing an operation flow in a ROM according to the present invention.

FIG. 3 is a diagram showing a relationship between a read address (input address) and read data (output data) from the ROM according to the present invention.

FIG. 4 is a diagram showing an operation principle as a counter of the ROM according to the present invention.

FIG. 5 is a diagram showing an error detection operation principle in a ROM according to the present invention.

FIG. 6 is a diagram showing a configuration of an example of a specific pattern detection circuit according to a conventional technique together with its peripheral circuits or peripheral devices.

FIG. 7 is a diagram showing an operation timing in an example of the pattern detection circuit.

[Explanation of symbols]

11 to 1n ... Data transmitting device, 2-1 ... Bit clock creating circuit, 2-2 ... Frame pulse creating circuit, 3 ... Data destination, 3-10 ... Detection clock creating circuit, 3-1
1 ... ROM, 3-12 ... Read data holding circuit

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Claims (1)

[Claims] 1. The serial data, which is in a bit phase synchronization state with each other, from each of the data transmission devices as a large number of data transmission sources is received at the data transmission destination, and is inserted into the data at a predetermined bit number interval. Is a multi-input specific pattern detection circuit for intensively monitoring and detecting whether or not the device diagnostic bit appears with a predetermined bit pattern within a time corresponding to the frame period, and an external read address Depending on various pseudo counter functions, comparison and collation function between device diagnostic bit and expected value, and pseudo backward / forward protection function, and ROM which has at least pseudo device backward and forward protection function And a read data holding means for holding the read data from the ROM by the latch signal from the signal generating means. Provided, device diagnostic bit group,
A multi-input specific pattern detection circuit configured to input various pseudo counter reset frame pulses and held output data from the read data holding means as read addresses to the ROM.