JPH05109971A - Lead frame - Google Patents

Lead frame

Info

Publication number
JPH05109971A
JPH05109971A JP3298044A JP29804491A JPH05109971A JP H05109971 A JPH05109971 A JP H05109971A JP 3298044 A JP3298044 A JP 3298044A JP 29804491 A JP29804491 A JP 29804491A JP H05109971 A JPH05109971 A JP H05109971A
Authority
JP
Japan
Prior art keywords
lead frame
dimple
tab
tab portion
working
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3298044A
Other languages
Japanese (ja)
Inventor
Hirohisa Endo
裕寿 遠藤
Takeshi Hosoki
剛 細木
Kosuke Sato
紘介 佐藤
Takashi Suzumura
隆志 鈴村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP3298044A priority Critical patent/JPH05109971A/en
Publication of JPH05109971A publication Critical patent/JPH05109971A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To suppress deformation due to working caused at the time of dimple working of a lead frame tab by press-working by providing a dimple having a trapezoidal cross section on an opposite side to an element fixing face of the tab. CONSTITUTION:A dimple 3 having a trapezoidal cross section is formed on a worked face 2 of a tab 1 of a lead frame having a thickness (t). The trapezoid is in a shape wherein a summit 4 of a pyramid or a cone has been cut by height (h) and has a plane parallel to the worked face 2, that is, a bottom 5. Formation of the bottom 5 produces components moving perpendicularly with respect to a material, these moving components expand horizontally on an element adhering surface, and they are balanced with horizontal components of the worked face 2. Thus, warping of the tab 1 can be suppressed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はリードフレームに関し、
特に、プレス加工によるリードフレームのタブ部のディ
ンプル加工時に生じる加工歪みを抑制したリードフレー
ムに関する。
FIELD OF THE INVENTION The present invention relates to a lead frame,
In particular, the present invention relates to a lead frame that suppresses processing distortion that occurs during dimple processing of the tab portion of the lead frame by press processing.

【0002】[0002]

【従来の技術】ディンプルの形成されたタブ部を有する
リードフレームを使用する従来の半導体装置は、図3に
示されるように、所定の形状,深さおよび大きさを有す
る複数のディンプル3をプレス機等により加工成型ある
いはエッチング等によってタブ部1(半導体素子の組み
付け部)に加工したリードフレームに、半導体素子6の
電極が形成されていない面を接着面として接合材7によ
って接着し、ワイヤ8によってインナーリード9に接続
し、ハッチングで示す部分を封止樹脂10によって封止
している。
2. Description of the Related Art A conventional semiconductor device using a lead frame having a dimple-formed tab portion presses a plurality of dimples 3 having a predetermined shape, depth and size, as shown in FIG. A lead frame processed into a tab portion 1 (assembly portion of a semiconductor element) by machining or etching by a machine or the like is bonded by a bonding material 7 with a surface of the semiconductor element 6 on which an electrode is not formed as an adhesive surface, and a wire 8 Is connected to the inner lead 9 and the portion indicated by hatching is sealed with the sealing resin 10.

【0003】リードフレームのタブ部1にディンプル3
を形成することによって、モールド成型時にディンプル
3へ封止樹脂10が入り込み、封止樹脂10のリードフ
レームに対する喰い付き性を良好にして密着性を向上さ
せるので、パッケージの信頼性が向上する。
The dimple 3 is formed on the tab portion 1 of the lead frame.
By forming the above, the sealing resin 10 enters the dimples 3 during molding, and the adhesiveness of the sealing resin 10 to the lead frame is improved and the adhesion is improved, so that the reliability of the package is improved.

【0004】[0004]

【発明が解決しようとする課題】しかし、従来のリード
フレームによると、タブ部1の加工面に対して形成され
るディンプル3の深さが深い程、封止樹脂10との喰い
付き特性が良好になる反面、ディンプル3をタブ部1の
加工面に対して深く形成すると加工歪みが生じてリード
フレームがディンプル加工面を外側にしてわん曲するこ
とがあり、このために図4に示すようにタブ部1に半導
体素子6を接合材7によって接着する際に接着面に隙間
11を生じることがある。この隙間11を防ぐために反
りを矯正する加工をタブ部1に与えることもあるが充分
ではない。また、タブ部1の素子接着面にも同じように
ディンプル3を形成すると反りの発生を抑えることがで
きるが、素子接着面にディンプル3を形成することは半
導体素子6とタブ部1との良好な接着性を確保させる点
から見て好ましくない。従って、本発明の目的はディン
プル形成によるリードフレームにおけるタブ部の反りを
抑制したリードフレームを提供することにある。
However, according to the conventional lead frame, the deeper the dimples 3 formed on the processed surface of the tab portion 1 is, the better the biting property with the sealing resin 10 is. On the other hand, when the dimples 3 are formed deeply with respect to the processed surface of the tab portion 1, processing distortion may occur and the lead frame may be bent with the dimple processed surface facing outward. Therefore, as shown in FIG. When the semiconductor element 6 is bonded to the tab portion 1 by the bonding material 7, a gap 11 may be formed on the bonding surface. The tab portion 1 may be processed to correct the warp in order to prevent the gap 11, but this is not sufficient. Further, when the dimples 3 are similarly formed on the element bonding surface of the tab portion 1, warpage can be suppressed. However, forming the dimples 3 on the element bonding surface is preferable for the semiconductor element 6 and the tab portion 1. It is not preferable from the viewpoint of ensuring good adhesiveness. Therefore, an object of the present invention is to provide a lead frame in which warp of the tab portion in the lead frame due to dimple formation is suppressed.

【0005】[0005]

【課題を解決するための手段】本発明はリードフレーム
におけるタブ部の反りを抑制するため、ディンプルが断
面台形の形状を有するリードフレームを提供する。ここ
で、ディンプルとはそれぞれ独立した凹みだけではな
く、所定のピッチで設けられる溝、スリット等をも含む
ものとする。
SUMMARY OF THE INVENTION The present invention provides a lead frame in which dimples have a trapezoidal cross section in order to suppress warpage of a tab portion in the lead frame. Here, the dimples include not only independent depressions but also grooves, slits, etc. provided at a predetermined pitch.

【0006】[0006]

【作用】断面が角錐形,円錐形であると、加工表面の材
料が水平方向に押し拡げられるので、加工表面を外側に
して反りが発生する。このため、本発明のリードフレー
ムは断面台形のディンプルをタブ部に形成している。台
形は角錐形,円錐形の頂部を切り落とした形状であり、
加工表面に平行な面を有する。この平行面の形成によっ
て材料の垂直方向への移動成分が生じる。この移動成分
は素子接着面で水平方向に拡がり、加工表面の水平方向
成分とバランスする。これによって反りが抑制される。
When the cross section is a pyramid or a cone, the material of the processed surface is expanded in the horizontal direction, so that a warp occurs with the processed surface facing outward. Therefore, in the lead frame of the present invention, dimples having a trapezoidal cross section are formed in the tab portion. The trapezoid is a pyramid or a cone with the top cut off.
It has a plane parallel to the processed surface. Due to the formation of the parallel planes, a moving component in the vertical direction of the material is generated. This moving component spreads horizontally in the element bonding surface and balances with the horizontal component of the processed surface. This suppresses warpage.

【0007】[0007]

【実施例1】以下、本発明のリードフレームを添付図面
を基に詳細に説明する。図1は本発明の一実施例を示
し、板厚tを有するリードフレームのタブ部1の一方の
面を加工面2にディンプル3が形成されている。その表
面よりディンプル3の底部5までの深さをδとし、高さ
をhとする。本実施例におけるリードフレームは13.4×
5.1mm ,厚み0.2mm の寸法を有する銅板で、タブ部1の
ディンプル3の仮想先端角度は90°で形成されてお
り、加工面に417個のディンプルが加工されている。
First Embodiment A lead frame of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 shows an embodiment of the present invention in which a dimple 3 is formed on one surface of a tab portion 1 of a lead frame having a plate thickness t and a processed surface 2. The depth from the surface to the bottom 5 of the dimple 3 is δ, and the height is h. The lead frame in this embodiment is 13.4 ×
A copper plate having a size of 5.1 mm and a thickness of 0.2 mm, the dimples 3 of the tab portion 1 are formed with a virtual tip angle of 90 °, and 417 dimples are machined on the machined surface.

【0008】図2はディンプル3の深さδと板厚tの比
δ/tが50%のリードフレームのタブ部1において、
前述の高さhと板厚tの比h/tを変化させたときのわ
ん曲(反り)の曲率の変化(1/ρ)を示す。わん曲の
方向は図2において加工面を外側とするものを正方向と
している。
FIG. 2 shows that in the tab portion 1 of the lead frame in which the ratio δ / t of the depth δ of the dimple 3 and the plate thickness t is 50%,
The change (1 / ρ) of the curvature of the bending (warping) when the ratio h / t between the height h and the plate thickness t is changed is shown. As for the direction of bending, the direction with the processed surface facing outward in FIG. 2 is the positive direction.

【0009】板厚tに対する先端部4の切り取り量hの
比が約10%ではタブ部1は正方向のわん曲を示してい
るが、その比が約17%でわん曲を生じない状態とな
る。さらにその比が増加するとタブ部1のわん曲方向が
反転して負方向のわん曲を生じ、先端部4の切り取り量
の増加に従ってタブ部1には負方向のわん曲が大きくな
る。
When the ratio of the cut amount h of the tip portion 4 to the plate thickness t is about 10%, the tab portion 1 shows a forward bending, but when the ratio is about 17%, no bending occurs. Become. When the ratio is further increased, the bending direction of the tab portion 1 is reversed to cause negative bending, and as the cut amount of the tip portion 4 increases, the negative bending of the tab portion 1 increases.

【0010】先端部4の切り取り量の増加に従い、ディ
ンプル3に形成される底部5の面積が増加することによ
って底部周辺のリードフレーム材料が主として深さ方向
へ押し退けられる。この深さ方向の移動成分が加工面と
の反対面(素子接着面)で水平方向成分に変わる。この
水平方向成分が加工面と水平方向成分とバランスするの
が前述したh/tが17%の時である。なお、リードフ
レームにおけるタブ部のわん曲に関する規格は一般的に
±0.2×10-2(1/mm)であるので安全性を考慮し、先
端部4の切り取り量を17±2%で形成したディンプルに
おいて、わん曲に対する良好な特性を示すことが確認さ
れている。
The area of the bottom portion 5 formed on the dimple 3 increases with an increase in the cutting amount of the tip portion 4, so that the lead frame material around the bottom portion is mainly pushed away in the depth direction. This moving component in the depth direction changes to a horizontal component on the surface opposite to the processed surface (element bonding surface). It is when the above-mentioned h / t is 17% that the horizontal component balances with the processed surface and the horizontal component. In addition, since the standard for the bending of the tab portion of the lead frame is generally ± 0.2 × 10 -2 (1 / mm), the cutting amount of the tip portion 4 was set to 17 ± 2% in consideration of safety. It has been confirmed that the dimple exhibits good characteristics with respect to bending.

【0011】[0011]

【発明の効果】以上説明した通り、本発明のリードフレ
ームによるとディンプルの断面形状を台形にしたので、
タブ部の反りを抑制することができる。
As described above, according to the lead frame of the present invention, the dimple has a trapezoidal cross-sectional shape.
The warp of the tab portion can be suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明の、ディンプル加工されたリード
フレームのタブ部の一実施例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a tab portion of a dimple-processed lead frame according to the present invention.

【図2】図2は本発明の、リードフレームのタブ部の角
錐の先端部の切り取り量とわん曲曲率の変化を示す説明
図である。
FIG. 2 is an explanatory diagram showing changes in the amount of cutting and the curvature of curvature of the tip portion of the pyramid of the tab portion of the lead frame of the present invention.

【図3】図3は従来の、ディンプル加工されたリードフ
レームのタブ部を有する半導体装置の断面図を示す。
FIG. 3 is a cross-sectional view of a conventional semiconductor device having a dimple-processed lead frame tab portion.

【図4】図4は従来の、ディンプル加工されたリードフ
レームのタブ部の断面図を示す断面図である。
FIG. 4 is a cross-sectional view showing a cross-sectional view of a tab portion of a conventional dimple-processed lead frame.

【符号の説明】[Explanation of symbols]

1 タブ部 2 加工面 3 ディンプル 4 先端部 5 底部 6 半導体素子 7 接合材 8 ワイヤ 9 インナーリード 10 封止材 11 隙間 1 Tab Part 2 Processed Surface 3 Dimple 4 Tip Part 5 Bottom Part 6 Semiconductor Element 7 Bonding Material 8 Wire 9 Inner Lead 10 Encapsulating Material 11 Gap

───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴村 隆志 茨城県土浦市木田余町3550番地 日立電線 株式会社システムマテリアル研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Takashi Suzumura 3550 Kidayomachi, Tsuchiura City, Ibaraki Prefecture Hitachi Cable Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を固定するために設けられる
タブ部の素子固定面の反対の面にディンプル(凹部)を
形成して封止樹脂との接着強度を大にするリードフレー
ムにおいて、 前記ディンプルは断面台形の形状を有することを特徴と
するリードフレーム。
1. A lead frame for increasing adhesive strength with a sealing resin by forming dimples (recesses) on a surface of a tab portion provided for fixing a semiconductor element, the surface being opposite to an element fixing surface. Is a lead frame having a trapezoidal cross section.
JP3298044A 1991-10-18 1991-10-18 Lead frame Pending JPH05109971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3298044A JPH05109971A (en) 1991-10-18 1991-10-18 Lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3298044A JPH05109971A (en) 1991-10-18 1991-10-18 Lead frame

Publications (1)

Publication Number Publication Date
JPH05109971A true JPH05109971A (en) 1993-04-30

Family

ID=17854403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3298044A Pending JPH05109971A (en) 1991-10-18 1991-10-18 Lead frame

Country Status (1)

Country Link
JP (1) JPH05109971A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI486597B (en) * 2013-07-23 2015-06-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI486597B (en) * 2013-07-23 2015-06-01

Similar Documents

Publication Publication Date Title
US7728412B2 (en) Semiconductor device having plurality of leads
US7183630B1 (en) Lead frame with plated end leads
JP2002064114A (en) Semiconductor device and its manufacturing method
JPH07297344A (en) Lead frame
JP2001015668A (en) Resin-sealed semiconductor package
JPH0621317A (en) Manufacture of semiconductor package
JPH05109971A (en) Lead frame
KR890004819B1 (en) Manufacture of resin seal type semiconductor device
JPH05218275A (en) Lead frame for semiconductor device
JP2004022725A (en) Semiconductor device
JPH088388A (en) Lead frame and semiconductor device
JPS60161646A (en) Lead frame for semiconductor device
JP3379246B2 (en) Lead frame with heat sink and method of manufacturing the same
JPS61269338A (en) Resin-sealed semiconductor device and molding die used for manufacture thereof
JPS59169161A (en) Semiconductor device
JP2010118712A (en) Method of manufacturing qfn package
JPS58186957A (en) Lead frame
JPH06302736A (en) Manufacture of lead frame for semiconductor device and semiconductor device
JPH09223767A (en) Lead frame
JPH1012802A (en) Lead frame and semiconductor device using the same
JPH11163010A (en) Metal mold for manufacturing semiconductor device
JP2001127184A (en) Hollow mold package
JPH1012797A (en) Lead frame, resin-sealed semiconductor device using the lead frame and manufacturing method therefor
JP2001352030A (en) Loc lead frame and its manufacturing method
JPH06132459A (en) Lead frame and manufacture thereof