JPH05109730A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce contact resistance between wirings, in a semiconductor device having a multilayer interconnection film. CONSTITUTION:Contact parts between wiring films which parts have been formed by a flat part in the conventional art are made uneven, and the surface area of the contact parts is increased, thereby reducing the contact resistance. Substratum wiring having uneveness is formed at 570-590 deg.C by a thermal CVD method using SiH4. Miniaturization of contact holes for high level integration can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. An object of the present invention is to reduce contact resistance between wirings in a semiconductor device having a multilayer wiring film.

[0002]

2. Description of the Related Art Conventionally, in a process of forming a contact portion in a manufacturing process of an LSI, a contact hole is formed in an interlayer insulating film formed on a base wiring film by dry etching, and then the surface is flattened by wet etching. An upper wiring film is formed thereon by the CVD method.

[0003]

However, in the above method, when the miniaturization of the LSI progresses and the contact hole becomes narrower, an increase in the contact resistance between the upper wiring and the lower wiring becomes a problem, and the inter-wiring film between However, there is a problem that the contact failure is likely to occur. Therefore, the present invention provides a semiconductor device that solves this problem and significantly reduces contact failures between wiring films, and a method of manufacturing the same.

[0004]

The semiconductor device according to the first aspect of the present invention is characterized in that the wiring and the contact surface of the wiring are made uneven. According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the base wiring having irregularities according to the first aspect is formed by using
It is characterized in that it is formed at 570 to 590 ° C. by the thermal CVD method using No. 4.

[0005]

EXAMPLE An example of a method of manufacturing a semiconductor device according to the present invention will be described. 1A to 1G are sectional views of manufacturing steps for explaining the method for manufacturing a semiconductor device of the present invention. First, a thermal oxide film 2 of 1000 Å was formed on a silicon substrate 1 by wet oxidation at 1000 ° C (Fig. 1 (a)), and then etched with a solution of hydrofluoric acid: water of 1: 200 for 3 minutes. Then, 1000 Å of the uneven amorphous silicon film 3 is formed by the thermal CVD method under a reduced pressure of 580 ° C. and 20 Pa (FIG. 1B), and the amorphous silicon film 3 having the unevenness is annealed at 800 to 900 ° C. , A polycrystalline silicon film 4 having irregularities is formed (FIG. 1C).

Phosphorus is implanted into this uneven polycrystalline silicon film 4 by ion implantation, and further etching is performed to form a base wiring layer 5 (FIG. 1D). Then CV
The interlayer insulating film 6 is formed in a thickness of 3000 Å by the D method (see FIG.
(E)) Then contact hole 7 by dry etching
Is formed (FIG. 1F), and finally an aluminum film 10000Å is formed by a sputtering method, and this is etched to form an upper wiring layer 8 (FIG. 1G). When the contact resistance of the underlying wiring layer 5 formed of the aluminum wiring and the polycrystalline silicon film was measured, it was 5 Ω per 0.5 μm ² contact hole. In the conventional manufacturing method in which a normal polycrystalline silicon having no unevenness is formed at a temperature (600 to 640 ° C.), a contact hole of 0.5 μm ² has a resistance of 15Ω.

From these results, it can be seen that the contact resistance between the underlying conductor film and the polycrystalline silicon film manufactured by the method of the present invention is drastically reduced as compared with the conventional method. In the above embodiment, the upper wiring layer is made of N + polycrystalline silicon, W, T
i, Mo, Pd, Ni, Ta, Cr, Pt, Au, Ag
In the case of using, Ti is formed on the polycrystalline silicon for the lower wiring.
Si2, MoSi2, WSi2, Pd2Si2, PtS
It was also confirmed that the contact resistance between the underlying wiring layer and the upper wiring layer was significantly reduced in the case of forming i and TaSi2 as compared with the case where the lower wiring layer was formed of a polycrystalline silicon film having no unevenness.

[0008]

As described above, according to the present invention, contact resistance can be reduced by making the contact portion between the wiring films, which is conventionally formed in a flat portion, uneven and increasing the surface area of the contact portion. As a result, it is possible to cope with the miniaturization of the contact hole due to the high integration.

[Brief description of drawings]

FIG. 1 is a manufacturing step sectional view showing a method of manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Thermal oxide film 3 ... Uneven amorphous silicon film 4 ... Uneven polycrystalline silicon film 5 ... Uneven N + polycrystalline silicon film 6 ... Base wiring film 7 ... Contact hole 8 ... Upper wiring layer

Claims (3)

[Claims] 1. A semiconductor device having multi-layered wiring, characterized in that the wiring and the contact surface of the wiring are made uneven. 2. A semiconductor device having multi-layer wiring, comprising:
A method of manufacturing a semiconductor device, comprising forming a base wiring having irregularities at 570 to 590 ° C. by a thermal CVD method using iH4. 3. A semiconductor device having a multi-layer wiring, comprising:
A method of manufacturing a semiconductor device, which comprises forming a film at 570 to 590 ° C. by a thermal CVD method using iH 4 and growing a metal silicide thereon.