JPH05108577A - Cache control system - Google Patents

Abstract

PURPOSE:To secure the coincidence of data fetched from a cache to a processor even when a clock skew is enlarged in the case of burst transfer concerning the cache control system for a computer system equipped with duplexed processors. CONSTITUTION:Cache storage devices 3 and 4 are connected independently for respective duplexed processors 1 and 2 by using system buses 5 and 6, and self-clocks CLK 1 and CLK 2 are individually supplied from the processors 1 and 2 to the corresponding cache storage devices 3 and 4. The processors 1 and 2 are equipped with a mode to simultaneously fetch plural words from the corresponding cache memory devices 3 and 4 synchronously with the clocks CLK 1 and CLK 2 and according to this mode, the address switching of the buffer storage devices 3 and 4 in the case of executing burst transfer from a gap between the cache memory devices 3 and 4 corresponding to the processors 1 and 2 and the output of the fetch data to the system buses 5 and 6 are executed according to the clocks CLK 1 and the CLK 2 from the microprocessors 1 and 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control system for a computer system having a duplicated processor. In recent years, a computer system aiming at a fault tolerant capable of continuing the operation without stopping the system even if one processor goes down due to a failure or the like has been put into practical use by duplicating the processors and performing the processes in parallel. ing.

When a cache storage device is provided in such a duplicated processor, cache control is performed in synchronization with a clock signal from one of the processors. This cache control includes a burst fetch / burst access mode in which the processor fetches a plurality of words at once. In the burst fetch / burst access mode of the duplicated processor, the fetch data is transferred from the cache storage device to the system bus in synchronization with the clock signal from one of the processors, and each processor transfers the system at the timing of its own clock signal. Fetch fetch data on the bus.

However, there is a clock skew due to the propagation characteristics of the circuit elements between the clock signals output from the duplicated processors, and timing fetching of fetched data by the processor not used for burst transfer may occur. There is a possibility that the system may be stopped due to detection of data inconsistency between processors due to deviation due to clock skew, and improvement of this point is desired.

[0004]

2. Description of the Related Art Conventionally, for example, a configuration shown in FIG. 4 has been used as a cache control system for a duplicated microprocessor. In FIG. 4, a processor module (P
In M) two synchronized microprocessors (MP
U) 1, 2 and one cache storage device 3 are connected by chip buses 5, 6 which function as a system bus.

The microprocessors 1 and 2 have a burst fetch / burst access mode in which a plurality of words are fetched at a time from a designated address of the cache memory device 3 in synchronization with a clock signal. For example, assuming that one word of the cache memory device 3 is 4 bytes, in the burst fetch / burst access mode, 4 words are sequentially designated from the designated address of the cache memory device 3, and 4
The 16-byte fetch data is fetched into the processors 1 and 2 by the burst transfer in which the fetch data is continuously transmitted four times in byte units.

More specifically, the two microprocessors 1 and 2 operating in synchronization supply the cache storage device 3 with, for example, the clock signal CLK1 of the microprocessor 1 to generate an address for burst transfer. The fetch data is output to the chip buses 5 and 6 by switching, and the microprocessors 1 and 2 individually fetch the fetch data in synchronization with their own clock signals CLK1 and CLK2.

At this time, the difference in propagation characteristics between the clock signals CLK1 and CLK2 of the microprocessors 1 and 2 due to the temperature of the elements provided in the circuit system from the clock oscillator to the microprocessors 1 and 2. Causes a clock skew (time shift). However, when the operation clocks of the conventional microprocessors 1 and 2 are low-speed, burst transfer with the cache storage device 3 is controlled in synchronization with the clock signal CLK1 from one microprocessor 1. However, even if the microprocessor 2 fetches the fetch data in synchronization with the clock signal CLK2 not used for burst transfer, the clock skew is small enough to be ignored with respect to the clock signal CLK2. Therefore, the burst occurs at the timing of the clock signal CLK1 without any problem. Even if the transferred fetch data is fetched by the microprocessor 2 at the timing of the clock signal CLK2, the fetch data of the microprocessors 1 and 2 can be matched.

[0008]

However, in the cache control system in which burst transfer is performed to two processors in synchronization with the clock signal of one microprocessor, the operating clock of the duplicated microprocessor becomes high in speed. If the microprocessor is composed of a CMOS integrated circuit whose propagation characteristics are easily affected by temperature, the clock skew between the clock signals for synchronizing the two processors becomes large.

When the clock skew becomes large in this way, as shown in FIG. 5, during burst transfer, the microprocessor 2 adds the clock skew to the clock CLK1 which gives the address switching timing t1 of the microprocessor 1. Since the fetch data is read at the address switching timing t2 of the signal CLK2, the data determination timings t3 and t4 of the microprocessors 1 and 2 after the setup time has elapsed are different, and a data mismatch between the microprocessors 1 and 2 is detected. There may be a problem that the processor module equipped with the microprocessors 1 and 2 stops.

The present invention has been made in view of the above-mentioned conventional problems, and the data taken in the processors are matched even if the clock skew becomes large at the time of burst transfer to the cache memory device of the duplicated processor. It is an object of the present invention to provide a cache control method that can secure the property and guarantee the reliability.

[0011]

FIG. 1 illustrates the principle of the present invention. First, the present invention is directed to a dual processor 1,
A computer system in which a cache storage device is connected to the system 2 using a system bus is targeted. According to the present invention as a cache control system for such a computer system, the cache processors 3 and 4 are independently connected to each of the duplicated processors 1 and 2 by using the system buses 5 and 6, and 2 to the corresponding cache storage devices 3 and 4 with their own clock signals CLK1 and C
KL2 is individually supplied, and the processors 1 and 2 have a mode (burst fetch / burst access mode) in which a plurality of words are simultaneously fetched from the corresponding cache memory devices 3 and 4 in synchronization with the clock signals CLK1 and CLK2. In this mode, the processors 1 and 2 output the fetch data to the system buses 5 and 6 and the address switching of the buffer memories 3 and 4 when the processors 1 and 2 perform burst transfer between the corresponding cache memories 3 and 4. It is characterized in that it is performed individually according to the clock signals CLK1 and CLK2.

Specifically, the cache storage control device 3,
Reference numeral 4 denotes an external circuit, which latches the addresses output from the processors 1 and 2 during burst transfer, and sequentially latches the latched addresses in synchronization with clock signals CLK1 and CLK2 from the microprocessors 1 and 2. Update. Further, the cache storage devices 3 and 4 receive the address designation from the external circuit at the time of burst transfer and continuously fetch the fetch data on the system buses 5 and 6 at the timing of the clock signals CLK1 and CLK2 from the processors 1 and 2. Output. Further, the processors 1 and 2 fetch fetch data continuously output from the cache storage devices 3 and 4 onto the system buses 5 and 6 at the timing of their own clock signals CLK1 and CLK2.

[0013]

According to the cache control system of the present invention having such a configuration, the duplicated microprocessor 1,
2 respectively connect dedicated cache memory devices 3 and 4 via system buses 5 and 6, and output address of fetch data to the system bus and address switching timing in burst transfer based on respective clock signals CLK1 and CLK2. To achieve this, two clock signals CL are added by increasing the speed of the clock signal and the CMOS configuration of the processor.
Even if the clock skew between K1 and CLK2 becomes large,
It is possible to ensure the consistency of fetch data between two processors by performing burst transfer in the burst fetch / burst access mode to the cache storage device without being affected by the clock skew, and to ensure high reliability.

[0014]

FIG. 2 is a block diagram of an embodiment showing one embodiment of the present invention. In FIG. 2, the processor module to which the cache control method of the present invention is applied is provided with duplicated microprocessors 1 and 2, and the microprocessors 1 and 2 are supplied from the same clock oscillator via different circuit systems. High-speed clock signals CLK1 and CL
It is operating in synchronization with K2. Under the control of the two microprocessors 1 and 2, two sets of cache storage devices 3 and 4 are provided.
An external circuit 10 for controlling a memory and the like is provided, and each of the microprocessors 1 and 2 is connected to each other by chip buses 5 and 6.

The microprocessors 1 and 2 are external circuits 1
0, clock signals CLK1 and CLK2 and burst access signals 11 and 12 are output. When the microprocessors 1 and 2 detect that the burst access request response signals 15 and 16 are asserted together with the transfer end signals 13 and 14 from the external circuit 10 during the assertion of the burst access signals 11 and 12, the burst transfer is started. To do.

The external circuit 10 is a cache storage device 3, 4
For the memory control unit (MCU), and executes store access or load access in response to access commands from the microprocessors 1 and 2. That is, the addresses output from the microprocessors 1 and 2 are latched at the same time when the burst access signals 11 and 12 are asserted, and the latched values are sequentially updated while the data of the target addresses in the cache storage devices 3 and 4 are clocked by the clock signal CLK1. , CLK2 at each timing and continuously output to the chip buses 5 and 6.

The microprocessor 1 fetches fetch data from the cache storage device 3 output on the chip bus 5 in synchronization with the clock signal CLK1 at the timing of the clock signal CLK1 output by itself. Further, like the microprocessor 1, the microprocessor 2 also outputs the clock signal CLK2 on the chip bus 6.
The fetch data from the cache storage device 4 output in synchronization with the clock signal C
It will be taken in at the timing of LK2.

FIG. 3 is a timing chart showing the operation during burst transfer, taking the microprocessor 1 side of FIG. 2 as an example. In FIG. 3, in synchronization with the clock signal CLK1 from the microprocessor 1, address switching for burst access is first performed on the address bus, and then the burst access signal to the external circuit 10 is made effective.

In response to this burst access, the cache memory device 3 receives the clock signal CLK in units of 4 bytes, for example.
The fetch data is output to the data bus four times in synchronization with 1 and the processor 1 synchronizes with the same clock signal CLK1.
Fetches fetched data on the data bus and performs burst transfer with 16 bytes as a unit. The operation during such burst transfer is the same on the processor 2 side as on the processor 1 side in FIG. 3 except that the clock signal CLK2 is used.

[0020]

As described above, according to the present invention, each duplicated processor switches the address and data to the cache memory device at the timing of its own clock signal, so that the clock pulse between the two clock signals is changed. Even if the queue size is increased by increasing the clock speed and CMOS circuit, the consistency of the fetched data can be secured by the burst transfer between the two processors, and the reliability of the duplicated cache control can be guaranteed. You can

[Brief description of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention.

FIG. 2 is a block diagram of an embodiment of the present invention.

FIG. 3 is a timing chart showing an operation during burst transfer, taking the processor 1 side of FIG. 2 as an example.

FIG. 4 is a block diagram of a conventional method

FIG. 5 is an explanatory diagram of address timing switching showing a problem of data mismatch due to clock skew.

[Explanation of symbols]

 1, 2: processor (microprocessor; MPU) 3, 4: cache storage device 5, 6: system bus (chip bus) 10: external circuit

Claims (2)

[Claims] 1. In a computer system in which a cache storage device is connected to redundant processors 1 and 2 by using a system bus, the cache storage devices 3 and 4 are independently provided for each of the redundant processors 1 and 2. The bus signals 5 and 6 are used for connection, and the clock signals CLK1 and CK of the processors 1 and 2 are sent to the corresponding cache storage devices 3 and 4 respectively.
L2 is individually supplied, and the processors 1 and 2 are configured to supply the clocks CLK1 and CL.
The cache memory device 3, which responds in synchronization with K2,
4 has a mode in which a plurality of words are fetched at a time, and in this mode, when the processors 1 and 2 perform burst transfer between the corresponding cache storage devices 3 and 4, the address switching of the buffer storage devices 3 and 4 and the system bus 5 ，
6. The cache control system is characterized in that the fetch data is output to 6 individually according to the clock signals CLK1 and CLK2 from the microprocessors 1 and 2. 2. The cache control system according to claim 1, wherein the cache storage control devices 3 and 4 include an external circuit,
The external circuit latches the address output from the processors 1 and 2 at the time of burst transfer, and uses the latched address as the clock signal CLK from the microprocessors 1 and 2.
1 and CLK2, the cache memory devices 3 and 4 receive addressing from the external circuit during burst transfer and receive clock signals CLK from the processors 1 and 2.
1 and CLK2, fetch data is continuously output to the system buses 5 and 6, and the processors 1 and 2 further output their own clock signals CLK.
1, cache memory device 3, 4 at the timing of CLK2
The cache control method is characterized in that fetch data continuously output to the system buses 5 and 6 are fetched.