JPH05108406A - Microprogram debugging device - Google Patents

Abstract

PURPOSE:To immediately see in which place a microcomputer operation desired to see is hourly generated while tracing whole movement and to immediately retrieve the operation of the microcomputer before and after, as well by providing event RAM fetching the address of trace RAM and generating the permission signal of event RAM from the status signal of the microcomputer. CONSTITUTION:When the whole history of the operation of a microcomputer part 6 is desired to see, trace RAM 7 is directly read from a host-side. When the specified operation is desired to see, a host reads the content of event RAM 8 at first, reads the address of trace RAM 7 and reads data on trace RAM 7 of the address. As necessary, the data on the microcomputer part 6 before and after can immediately be read. Since the address of trace RAM 7 is the output of a counter 10 by a basic clock, it directly corresponds to the elapse time of the operation of the microcomputer 6 and the generated time of an event can be converted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trace function of a microcomputer program debug device.

[0002]

2. Description of the Related Art A basic trace function is to sequentially send a signal from a microcomputer to RA according to the basic clock of the microcomputer.
This is done by writing to M. However, in recent years, when a specific operation condition can be set in the trace function and the developer wants to see only the operation of the CPU, there is also a method of aiming only the timing by creating a write signal of the trace RAM using the status signal. Taken.

The structure of the trace block in the conventional microcomputer program debug device will be described below.

FIG. 3 is a block diagram of a conventional trace. 1 is a portion having a circuit equivalent to a microcomputer for developing a program (hereinafter referred to as a microcomputer portion), 2 is a host portion for controlling a microcomputer program debugging device, 3 is a trace RAM for sequentially writing control signals and data of the microcomputer according to the movement of the microcomputer, 4 is a switch unit for controlling the trace, and 5 is a counter for generating an address of the trace RAM.

The trace operation of the microcomputer program debug device configured as described above will be described. First, when the movement of the microcomputer is sequentially traced, the basic clock generated by the microcomputer unit 1 every machine cycle is used as the write enable signal of the trace RAM 3 and the clock of the counter 5. When the host unit 2 sends an enable signal to the trace RAM 3 and the counter 5, the trace starts.
After the trace is completed from the host unit 2, it is difficult to read the data in the trace RAM 3 from the host unit 2, so that the developer knows how the microcomputer operates according to the program that he has set up. Further, when the developer wants to follow only a certain movement, the trace RAM 3 and the counter 5 are set to be enabled only when the status signal of the microcomputer 1 from the host unit 2 to the switch unit 4 satisfies a certain condition. However, the microcomputer signal only at that time can be written in the trace.

[0006]

However, in the above-mentioned conventional configuration, in the case of sequential tracing, the developer must look at all the addresses when searching the trace RAM for the desired operation. When a large-capacity memory becomes available at a low price, it becomes possible to write all the information on the operation of the microcomputer in the trace RAM for a long time, and it takes a very long time to search for the desired data.

Further, if the trace is performed only under a predetermined condition, there is a problem that only the signal at a desired portion cannot be seen and the movement before and after the signal cannot be understood.

The present invention solves the above-mentioned problems, and while tracing the entire movement, it is possible to immediately see at which point in time the desired microcomputer operation has occurred. Is also intended to be searchable immediately.

[0009]

In order to achieve the above object, the present invention provides a microcomputer program debugging device of the present invention, which has an event RAM for fetching an address of the trace RAM, in addition to the trace RAM, and a status of the microcomputer. It has a configuration for generating the permission signal of the event RAM from the signal.

[0010]

According to this structure, the address where the desired operation in the trace RAM is written can be immediately known by reading the event RAM, and the microcomputer operation which is infrequent in a large amount of trace data can be performed. This is useful when searching for a location. Further, in the flow of the entire software, the developer can immediately know at what point in time a specific operation occurs.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a block diagram showing the configuration of the embodiment. The movement of the microcomputer unit 6 is sequentially written in the trace RAM 7 by the counter 10 in synchronization with the basic clock. Counter 9 only when the status signal generated during the operation of a specific microcomputer becomes active
And the event RAM 8 operates to fetch the address of the trace RAM 7 at that time.

To view the entire history of the operation of the microcomputer section 6, the host side directly reads the trace RAM 7. When looking at a specific operation, the host first reads the contents of the Yvette RAM 8, reads the address of the trace RAM 7, and then reads the data of the trace RAM 7 at that address.

Further, if necessary, the data of the microcomputer section 6 before and after it can be immediately read. Also, the same operation as the conventional conditional trace can be read out by displaying only the data in the address of the trace RAM 7 of the event RAM 8 on the monitor.

Since the trace address is the output of the counter based on the basic clock, it directly corresponds to the elapsed time of the operation of the microcomputer 6 and the data in the event RAM 8 can be converted into the event occurrence time.

FIG. 3 is a block diagram showing the configuration of the second embodiment of the present invention. A selector is provided so that the host can select the event signal from the microcomputer signals.
This allows flexibility in trace conditions. The selector 14 selects one signal from the signal of the microcomputer unit 13 from the host 11.

Further, the outputs of the plurality of selectors 14 are logically ORed by the logical OR circuit 15, and the logical OR is performed to the event RA.
M12 is enabled, and the selector RAM output is also written in the event RAM 12 together with the address of the trace RAM.

As a result, after the operation of the microcomputer is completed, the host unit 11 reads the selector output data of the event RAM 12 and obtains the logical product or the logical sum of them to obtain the address of the trace RAM even for complicated conditions. It is possible to extract, and it is possible to see trace data under different conditions without having to restart the trace.

[0018]

As is apparent from the above embodiments, according to the present invention, with respect to the trace data desired by the software developer, by providing the event RAM, the time position at which the event immediately occurs and the time point Since it is possible to know the address of the trace RAM in which the information of is written, and the operation before and after that can be seen at the same time, when searching the position of the microcomputer operation that is infrequent in a large amount of trace data. To provide a microcomputer program debugging device that is effective and has good software development efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram of a condition setting circuit of an apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram of a conventional device.

[Explanation of symbols]

 6 Microcomputer part 7 Trace RAM 8 Event RAM 9 Counter 10 Counter 11 Host part 12 Trace RAM 13 Microcomputer part 14 Selector 15 Logical sum circuit

Claims (2)

[Claims] 1. From a basic clock required for microcomputer operation,
A first counter that generates a first address, a trace RAM that sequentially takes in the first address as address information using a microcomputer control signal and a microcomputer data bus as data, and a trace RAM that is generated according to a specific condition of the microcomputer operation. A microcomputer provided with a second counter for generating a second address by a status signal, and an event RAM for permitting fetching by a status signal, the second address as address information, and the first address as data information Program debug device. 2. A microcomputer program debug device comprising: a selector for selecting one of microcomputer signals; a means for producing a status signal of the specific condition from the selector output; and a status signal written in the event RAM. ..