JPH05108344A - Instruction fetch controller - Google Patents

Abstract

PURPOSE:To fetch an instruction at a high speed with use of a high speed access mode of a dynamic memory. CONSTITUTION:An instruction fetch control pert 10 decodes an instruction fetch control field in an instruction if this instruction is not equal to a branch instruction. Then the part 10 decides whether a high speed access mode is usable for the next instruction fetch or not and informs a memory access control part 4 of this deciding result. If a branch instruction is confirmed, an instruction decoding part 6 decodes a branch destination instruction fetch control field in an instruction and decides whether the high speed access mode is usable or not for the instruction fetch to the branch destination. Then the part 8 informs the part 4 of the deciding result. Therefore it is not required to perform the comparison of row addresses after the output of an instruction fetch address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer instruction fetch control device for decoding and executing instructions stored in a memory.

[0002]

2. Description of the Related Art In recent years, with the progress of memory technology, a dynamic memory having a high-speed access mode for giving only a column address has been widely used in addition to a normal access mode for sequentially accessing a row address and a column address. It was An instruction fetch control device for storing instructions in a dynamic memory and using this high speed access mode to speed up instruction fetching has been very important. An instruction fetch control device using the high speed access mode is described, for example, in the following document (“Transistor Technology”, Vol. 27, No. 3, 481 to 490).
page).

The conventional instruction fetch controller described above will be described below with reference to FIG. In FIG. 3, reference numeral 21 denotes a dynamic memory having a high-speed access mode for giving only a column address in addition to a normal access mode for giving a row address and a column address in order, and an instruction fetch address generator 22 for generating an address for fetching an instruction. , 23 is a multiplexer, 24 is a latch for temporarily storing the row address output from the instruction fetch address generation unit 22, 25 is a coincidence detector for comparing the contents of the latch 24 with the row address output from the instruction fetch address generation unit 22. , 26 is a memory access control unit for outputting a memory access control signal to the dynamic memory 21,
27 is an instruction register for storing instructions read from the dynamic memory 21, 28 is an instruction decoding section for decoding the contents of the instruction register 27, 29 is an operation executing section for performing data operations, 30 is an instruction fetch for controlling the instruction fetch operation. It is a decoding section.

The operation of the instruction fetch controller having the above structure will be described. First, in a normal case, the instruction fetch controller 30 controls the instruction fetch generator 22 to generate an address next to the immediately preceding instruction fetch address. At the same time, an instruction fetch request signal for requesting the start of instruction fetch is output to the memory access control unit 26. The address generated by the instruction fetch address generation unit 22 is input to the multiplexer 23 with the upper side as the row address and the lower side as the column address, and according to the output of the memory access control signal to the dynamic memory 21 by the memory access control unit 26. , Row address, column address are output in this order. The row address output from the instruction fetch address generation unit 22 is stored in the latch 24. When one access to the dynamic memory 21 is completed and the read instruction is stored in the instruction register 27, the memory access control unit 26 returns an instruction fetch end signal to the instruction fetch control unit 30 and one instruction fetch. Ends. The instruction decoding unit 28 decodes the contents of the instruction register 27 and controls the operation of the operation executing unit 29. When the result decoded by the instruction decoding unit 28 is not a branch instruction, the instruction fetch control unit 30 repeats the above operation.

On the other hand, when the result decoded by the instruction decoding unit 28 is a branch instruction, the instruction decoding unit 28 controls the instruction fetch generation unit 22 to generate a branch destination address and use it for the next instruction fetch. .. In either the normal case or the branch instruction, the instruction fetch address generation unit 2
The row address output by 2 is compared with the contents of the latch 24 by the coincidence detector 25. As a result, the row address generated by the immediately preceding instruction fetch is compared with the row address generated by the current instruction fetch. As a result, when it is determined that the addresses are the same row address, a high speed access control signal is output to the memory access control unit 26 to access the dynamic memory 21 in the high speed access mode.

[0006]

However, in the above-mentioned configuration, since the row address is compared and determined with the immediately preceding row address when the instruction fetch address is output, it takes time to make the determination and the basic cycle time of the memory access becomes long. .. That is, the time required only for the column address access in the high-speed access mode is longer than the time required for the column address access when performing the row address access and the column address access in the normal access, and the effect of using the high-speed access mode is reduced. There was a problem of doing.

In view of the above points, the present invention provides an instruction fetch control device in which the column address access time does not become long when the high speed access mode is used as compared to when the high speed access mode is not used. To aim.

[0008]

In order to solve the above-mentioned problems, the invention of claim 1 provides a dynamic memory having a high-speed access mode for giving only a column address in addition to a normal access mode for giving a row address and a column address in this order. An instruction fetch using a configuration having an instruction / operand field and a next instruction fetch control field that specifies whether or not the high-speed access mode can be used for the memory fetch to the next instruction, as the instruction to be used and stored in the dynamic memory A control device, which includes an instruction fetch address generation unit that generates an address for fetching an instruction stored in the dynamic memory, and a row address that outputs the output of the instruction fetch address generation unit to the dynamic memory. A multiplexer that switches and outputs the column address The memory access control signal for outputting the memory access control signal to the dynamic memory and the memory access control unit for controlling the analog multiplexer so as to output only the column address when the dynamic memory is accessed at high speed, and the instruction read from the dynamic memory are stored. An instruction register, an instruction decoding unit that decodes an instruction / operand field of the instructions stored in the instruction register, and an operation execution unit that performs a data operation by an execution control signal output by the decoding result of the instruction decoding unit. Whether the next instruction fetch control field of the instructions stored in the instruction register is decoded, the next instruction address generation control signal is output to the instruction fetch address generation unit, and the high-speed access mode is used for the memory access control unit. High-speed access to specify It is characterized by comprising an instruction fetch control unit for outputting a control signal.

According to a second aspect of the present invention, a branch instruction is used as an instruction that uses a dynamic memory having a high-speed access mode that gives only a column address in addition to a normal access mode that gives a row address and a column address in this order. Instructions other than those are configured to have an instruction / operand field and a next instruction fetch control field that specifies whether or not the high-speed access mode can be used for memory fetch to the next instruction, while a branch instruction has the instruction / operand field. And a next instruction fetch control field, the instruction fetch control device having a branch destination instruction fetch control field for designating whether or not the memory access to the branch destination instruction can use the high speed access mode. The instructions stored in memory are Instruction fetch address generator, a multiplexer for switching the address output from the instruction fetch address generator to a row address and a column address and outputting the row address and column address to the dynamic memory, and memory access to the dynamic memory. A memory access control unit that outputs a control signal and controls the multiplexer so as to output only a column address when the dynamic memory is accessed at high speed, an instruction register that stores an instruction read from the dynamic memory, and the instruction An instruction that decodes the instruction / operand field of the instructions stored in the register and outputs an execution control signal, and in the case of a branch instruction, an instruction that gives a signal instructing the instruction fetch address generation unit to generate a branch destination address. Decoding section and above Decodes an operation execution unit by the execution control signal output by the decoding result by the decree decoding unit performs data operations, the branch target instruction fetch control field of the instruction stored in the instruction register,
A branch instruction decoding unit that outputs a branch instruction control signal that specifies information on whether the instruction is a branch instruction and whether the high-speed access mode can be used for fetching a branch destination instruction; and a branch instruction from the branch instruction control signal. If it is determined that it is not a branch instruction, the next instruction fetch control field of the instruction stored in the instruction register is decoded, and the next instruction address generation control signal is output to the instruction fetch address generation unit. , Outputting a high-speed access control signal for designating whether or not to use the high-speed access mode to the memory access control unit, while using a high-speed access mode for the memory access control unit when it is determined to be a branch instruction. Equipped with an instruction fetch decoding unit that outputs a high-speed access control signal that specifies whether to perform It is characterized by a door.

[0010]

According to the present invention, the instruction decoding unit decodes the instruction / operand field in the instruction stored in the instruction register, the instruction fetch control field decodes the instruction fetch control field, and the next instruction is executed. It is determined whether or not the high speed access mode can be used for the dynamic memory access for fetching, and a high speed access control signal indicating the result of the judgment is output to the memory access control unit. From this signal, the memory access control unit controls the multiplexer to output only the column address when using the high speed access mode, and at the same time, gives the memory access control signal to the dynamic memory to access the dynamic memory in the high speed access mode. ..

By the above operation, the memory access mode of the next instruction fetch included in the instruction is decoded and notified to the memory access control unit, so that the memory access mode is fixed before the instruction fetch is started. The column address access time when using the high-speed access mode is not longer than that when the high-speed access mode is not used, and a high-speed instruction fetch operation is possible.

According to the invention of claim 2, basically, the same operation as that of the invention of claim 1 is performed, but when the instruction stored in the instruction register is a branch instruction, the branch instruction decoding unit Causes the instruction fetch address generation unit to generate a branch destination address and outputs a branch instruction control signal to the instruction fetch control unit. The instruction fetch controller determines whether or not the dynamic memory can be accessed in the high speed access mode based on the branch instruction control signal, and gives the signal of the determination result to the memory access controller. In this case, the memory access control unit performs access control of the dynamic memory by performing the same operation as in the high-speed access mode of a normal instruction that is not a branch instruction.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An instruction fetch control device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an instruction fetch control device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 is a dynamic memory having a high-speed access mode for giving only a column address in addition to a normal access mode for giving a row address and a column address in order, and 2 is an instruction fetch address generation unit for generating an address for fetching an instruction. 3 is a multiplexer, 4 is a memory access control unit for outputting a memory access control signal to the dynamic memory 1, 5 is an instruction register for storing an instruction read from the dynamic memory 1, and 6 is an instruction stored in the instruction register 5. Among these, an instruction / operand field storage unit that specifies the type of instruction operation and data used for instruction execution, and 7 is whether the memory fetch to the next instruction of the instructions stored in the instruction register 5 can use the high-speed access mode. Next instruction fetch control field storage section that specifies The instruction decoding unit for decoding the contents of the instruction register 5, 9 operation performing unit that performs data operations, 10 is an instruction fetch decode unit for controlling the instruction fetch operation.

FIG. 2 is an explanatory diagram showing the structure of an instruction used in this embodiment. As shown in FIG. 2, the instruction structure is roughly classified into two types depending on whether it is a branch instruction or not. If it is not a branch instruction, it is composed of an instruction / operand field and an instruction fetch control field. When it is a branch instruction,
A branch destination instruction fetch control field is further set as a part of the instruction / operand field.

Next, the operation when the instruction fetch control device configured as shown in FIG. 1 fetches and executes the instruction shown in FIG. 2 will be described. First, the instruction decoding unit 8 decodes the contents of the instruction / operand field storage unit 6 in the instruction register 5. As a result, when it is not a branch instruction, the instruction fetch control unit 10 causes the instruction fetch generation unit 2 to generate the next instruction fetch address, decodes the contents of the instruction fetch control field storage unit 7 in the instruction register 5, and It is determined whether or not the dynamic memory access for instruction fetch can use the high-speed access mode, and the high-speed access signal which is the determination result is output to the memory access control unit 4 together with the instruction fetch request signal.

The addresses generated by the instruction fetch address generator 2 are input to the multiplexer 3 with the upper side being the row address and the lower side being the column address. The multiplexer 3 alternately switches the row address and the column address when the dynamic memory 1 is not accessed at high speed by the switching control signal from the memory access control unit 4, and the column address when the dynamic memory 1 is accessed at high speed. Controlled to output only.

The dynamic memory 1 is switched between the normal access mode and the high speed access mode by a memory access control signal from the memory access control unit 4, and is designated by a row address and / or a column address signal output from the multiplexer 3. Read the instruction stored in the address. When the instruction read from the dynamic memory 1 is stored in the instruction register 5, the memory access control unit 4 outputs an instruction fetch end signal to the instruction fetch control unit 10 to end one instruction fetch.

On the other hand, when the instruction decoding unit 8 decodes the contents of the instruction / operand field storage unit 6 in the instruction register 5, and the instruction is a branch instruction, the instruction decoding unit 8 causes the instruction fetch address generating unit 2 to branch to the branch destination address. And a branch instruction control signal is output to the instruction fetch control unit 10. The branch instruction control signal indicates that the branch instruction is executed, and whether or not the memory fetch to the branch destination instruction given as a part of the instruction / operand field storage unit 6 can use the high speed access mode. Contains the instruction fetch control field. The instruction fetch control unit 10 outputs a high-speed access control signal indicating whether or not the high-speed access mode can be used to the memory access control unit 4 by the branch instruction control signal together with the instruction fetch request signal.

The branch destination address generated by the instruction fetch address generator 2 is input to the multiplexer 3,
The row address and the column address are alternately switched and output by the switching control signal from the memory access control unit 4, or only the column address is output. The dynamic memory reads an instruction in the normal mode or the high speed mode according to the memory access control signal from the memory access control unit 4 and the address signal output from the multiplexer 3. When the instruction read from the dynamic memory 1 is stored in the instruction register 5, the memory access control unit 4 outputs an instruction fetch end signal to the instruction fetch control unit 10 to end one instruction fetch.

As described above, according to the present embodiment, the memory access mode for the next instruction fetch included in the instruction is decoded by the instruction fetch decoding unit 2 and the instruction decoding unit 8 and is then transferred to the memory access control unit 4. By notifying, the memory access mode is fixed before the instruction fetch starts, so the column address access time when using the high-speed access mode does not become longer than when the high-speed access mode is not used. It becomes possible to operate.

The memory access mode included in the instruction is determined when the address storing the instruction is fixed. That is, it can be determined when the instruction is stored in the dynamic memory 1 before the instruction fetch is executed. In the embodiment, the instruction decoder 8 decodes the branch destination instruction fetch control field to determine that the instruction is a branch instruction. However, a branch instruction decoder is provided separately from the instruction decoder 8 to The branch destination instruction fetch control field may be decoded by the decoder.

In this case, it is not necessary to provide the branch destination instruction fetch control field in the instruction / operand field as shown in FIG. 2A. For example, the instruction / operand field and the next instruction fetch control field are further added. It can also be provided in the form of addition.

[0023]

As described above, according to the present invention, the instruction fetch includes the memory access mode for the next instruction fetch, and the instruction fetch is performed by decoding this instruction and notifying it to the memory access control unit. Since the memory access mode is determined before the start, the column address access time when using the high-speed access mode is not longer than that when the high-speed access mode is not used, and a high-speed instruction fetch operation is possible. As a result, by using the high-speed access mode of the dynamic memory, it is possible to realize a literally high-speed instruction fetch operation, and the format of the instruction is structurally different, and a specific field of the instruction is specified by the instruction fetch control unit. Since it only needs to be decrypted, it has the effect of being inexpensive to implement.

[Brief description of drawings]

FIG. 1 is a block diagram of an instruction fetch control device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of an instruction format in the embodiment.

FIG. 3 is a block diagram of a conventional instruction fetch control device.

[Description of Codes] 1 dynamic memory 2 instruction fetch address generation unit 3 multiplexer 4 memory access control unit 5 instruction register 8 instruction decoding unit 9 operation execution unit 10 instruction fetch decoding unit

Claims (3)

[Claims] 1. An instruction / operand field and an instruction field which are used as instructions to be stored in a dynamic memory having a high-speed access mode in which only a column address is added in addition to a normal access mode in which a row address and a column address are given in order. An instruction fetch controller using a configuration having a next instruction fetch control field for specifying whether or not a high speed access mode can be used for fetching an instruction, for fetching an instruction stored in the dynamic memory. Instruction fetch address generator, a multiplexer for switching output of the row address and column address to output the output of the instruction fetch address generator to the dynamic memory, and a memory access control signal for the dynamic memory. Output In addition, when accessing the dynamic memory at high speed, a memory access control unit that controls the analog multiplexer so as to output only the column address, an instruction register that stores an instruction read from the dynamic memory, and an instruction register that is stored in the instruction register. Of the instructions stored in the instruction register, an instruction decoding section that decodes the instruction / operand field of the instructions, an operation execution section that performs data operation based on the execution control signal output by the decoding result of the instruction decoding section, and an instruction stored in the instruction register. Decode the next instruction fetch control field, output the next instruction address generation control signal to the instruction fetch address generation unit, and
An instruction fetch control unit, comprising: an instruction fetch control unit that outputs a high-speed access control signal that specifies whether to use a high-speed access mode for the memory access control unit. 2. An instruction other than a branch instruction is used as an instruction to use a dynamic memory having a high-speed access mode for giving only a column address in addition to a normal access mode for giving a row address and a column address in order. A structure having an operand field and a next instruction fetch control field for designating whether or not the high speed access mode can be used for memory fetch to the next instruction, while the branch instruction has the instruction / operand field and the next instruction fetch control. An instruction fetch control device having a branch destination instruction fetch control field for specifying whether or not a memory fetch to a branch destination instruction can use a high-speed access mode in addition to the field, and is stored in the dynamic memory. An instruction fetcher Instruction fetch address generator, a multiplexer that switches the address output from the instruction fetch address generator to a row address and a column address and outputs the row address to the dynamic memory, and a memory access control signal to the dynamic memory In addition, when accessing the dynamic memory at high speed, the memory access control unit that controls the multiplexer so as to output only the column address, the instruction register that stores the instruction read from the dynamic memory, and the instruction register that is stored in the instruction register. An instruction decoding unit that decodes the instruction / operand field of the instruction to output an execution control signal and, in the case of a branch instruction, gives a signal instructing the instruction fetch address generation unit to generate a branch destination address; According to the instruction decoding unit The operation execution unit that performs data operation by the execution control signal output by the decoding result, and the branch destination instruction fetch control field of the instruction stored in the above instruction register is decoded, and information on whether the instruction is a branch instruction and the branch destination A branch instruction decoding unit that outputs a branch instruction control signal that specifies information on whether or not the high-speed access mode can be used for instruction fetch, and a branch instruction control signal that determines whether the instruction is a branch instruction and that the instruction is not a branch instruction. Then, the next instruction fetch control field of the instruction stored in the instruction register is decoded, the next instruction address generation control signal is output to the instruction fetch address generation unit, and the high speed access mode is set to the memory access control unit. Outputs a fast access control signal that specifies whether to use it, while
An instruction fetch control unit including an instruction fetch decoding unit that outputs a high-speed access control signal designating whether to use the high-speed access mode to the memory access control unit when it is determined to be a branch instruction. apparatus. 3. The branch destination instruction fetch control field is provided in an instruction / operand field,
3. The instruction fetch control device according to claim 2, wherein the instruction decoding unit also serves as a branch instruction decoding unit.