JPH05103489A - Motor speed controller - Google Patents

Abstract

PURPOSE:To obtain good speed control characteristics in any state by operating a signal to be generated by adding a frequency discriminator or an acceleration detector to a phase detector which discharges an output control amount, thereby largely removing an error signal and achieving proportional or proportional/ differential control. CONSTITUTION:The motor speed controller comprises, in addition to a phase detector 11 having a first counter 13 and a latch circuit 14, a limiter 21 for applying load data to the counter 13, a frequency discriminator 31 for generating a modulation signal to the detector 11, or an acceleration detector 33, signal processing means 30 having logical circuits 32, 35 or 34, a signal distributor 25 for generating signals to be applied to the elements, and a clock generator 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor speed controller for obtaining a smooth transient response and stable normal characteristics in a wide range of speed modes, and more particularly to a motor speed controller used for a carriage motor of a printer.

[0002]

2. Description of the Related Art FIG. 7 is a diagram showing an embodiment of a conventional technique disclosed in general publications, and FIG. 8 is a diagram showing its characteristics.

In FIG. 7, 1 represents velocity data or an input terminal. A clock generator 2 generates a reference clock φs corresponding to the speed data 1. Ms represents a signal proportional to the speed of the frequency generator 8 provided in the motor 7. Reference numeral 4 denotes a phase detector which counts the reference clock φs and has a capacity of a cycle To corresponding to the target speed and a counter 1 using a signal Ms.
Of the latch circuit 1 and a D / A converter 1 for D / A (digital / analog) conversion of the data of the latch circuit 1. The output characteristic of the phase detector 3 is shown in FIG.

Reference numeral 4 denotes a frequency discriminator, which emits an amount distant from the period To or frequency o corresponding to the target speed, and FIG. 8A shows a characteristic example. In FIG. 8A, the maximum output is obtained below a certain frequency, and the zero output is produced above a certain frequency. Before and after the target frequency fo, it changes from a maximum to zero by a negative count and emits an output.

The frequency discriminator 4 has a reference clock φ.
of the latch circuit 2 and the latch circuit 2 that counts s, is reset by the signal Ms, and has a capacity corresponding to the cycle To of the target speed, and the data of the counter 2 is latched by the Ms signal via a logic circuit (not shown). D / A converter 2 for D / A converting data
Consists of.

Reference numeral 5 is an adder / subtractor such as an operational amplifier. The phase output is a variable resistor VR ₁ and the frequency discrimination output is a variable resistor VR _2.
Weighted input via. The output of the adder / subtractor 5 is applied to the motor 7 via the power amplifier 6.

FIG. 8C shows an example of a startup characteristic at the time of starting the motor speed control shown in FIG. 3 examples of no control and target velocities A and B are shown. The example in which the motor speed control device according to the related art is described above shows an example in which the transient characteristic is worse at a lower speed B and the startup time of stable steady rotation is longer.

[0008]

However, in the above-mentioned prior art, when the power supply voltage is constant, there is a problem that the start-up characteristic is poor due to the occurrence of overshoot or undershoot at a constant speed. The speed of the motor is no serious problem in the case of one type, a printer, to adjust the variable resistor VR ₁ and VR ₂ if anything like a copier kinds speed mode is required is impractical. To solve this, the analog switch is used to switch the settings that are set according to the speed mode. This raises the problem of cost increase due to the increase in the number of components. In particular, when the basic components are integrated into an IC, there is a problem that the space efficiency is deteriorated due to the increase of external parts.

Therefore, the motor speed control device of the present invention solves these problems, and its purpose is to release only one control amount and to perform good control even if external parts for adjustment are eliminated. A motor speed control device having characteristics is provided.

Still another object is to add a large amount of error signal elimination, proportional control or proportional / derivative control in cooperation with a frequency discriminator or an acceleration detector to a phase detector that emits a controlled variable,
It is an object of the present invention to provide a motor speed control device that can obtain smooth start-up characteristics or transient response characteristics and stable steady-state characteristics even in various speed modes.

[0011]

[Means for Solving the Problems] A motor having a speed control amount obtained by D / A (digital-analog) conversion of a phase difference between a signal MS of a motor frequency generator and a reference period signal To corresponding to a target speed. In the speed control device, a clock generator 10 and a signal distributor 25 that generates a predetermined signal group with the signal MS.
, A phase detector 11 having a first counter 13 having a predetermined input / output means and a latch circuit 14 as main components, and D / A converting data of the latch circuit 14 into a motor control amount.
A converter 18, a limiter 21 for setting the upper and lower limits of the controlled variable,
It comprises a frequency discriminator 31 and a signal processing means for generating a signal for loading the data of the limiter 21 to the first counter 13 and a signal for giving to the input means of the first counter. It is a feature of the present invention that it has a smooth start-up (start-up) characteristic or a transient response characteristic and a stable steady-state characteristic even in various speed modes by preventing the quantity and having an appropriate proportional control or proportional / derivative control. ..

Further, the signal processing means 30 includes an acceleration detector 33.
In addition, it is a feature of the present invention that the control characteristic is further improved by acting on the control of the input means of the first counter 13 alone or in cooperation with the frequency discriminator 31.

Furthermore, the acceleration detector 33 is a frequency discriminator.
Another feature of the present invention is that the cost is reduced by reducing the number of components by configuring 31 components in common.

[0014]

FIG. 1 is a diagram showing a concrete block configuration of an embodiment of the present invention. In FIG. 1, the same reference numerals or numbers as in FIG. 7 have the same meaning.

In FIG. 1, reference numeral 10 designates a clock generator for speed data.
The reference clock φS and the clock φS modulated by 10 generate a clock φB having a different phase or a higher frequency. There may be a plurality of clocks φB.

Reference numeral 11 denotes a phase detector, which is mainly composed of a first counter 13 and a latch circuit 14 which always latches the data of the first counter 13 with a signal MS. CK, LD, R, and LP represent a clock input terminal, a load signal terminal, a reset terminal, and a latch pulse input terminal, respectively. 12 is an AND-DR gate that adds or deletes the clocks φS and φB, and normally clocks φS
Is passing. Reference numeral 15 is an OR gate, and 16 is a delay device, which is denoted by D. The delay device 16 is the first counter in a specific case
The timing is adjusted so that the data of 13 is accurately taken into the latch circuit 14. 17 is an OR gate.

Reference numeral 18 is a D / A converter which converts the data of the latch circuit 14 into D
/ A is converted and an analog control amount is emitted via the line 18a.

Reference numeral 21 is a limiter which takes in and holds the upper and lower limit values of the control amount in each speed mode from the upper and lower limit data input terminal 20. Data acquisition may be from the velocity data line. The data of the limiter 21 is taken into the first counter 13 when the speed is under or over, and the over-braking or over-energizing is prevented by limiting the upper and lower limits of the release control amount. As a result, there is a feature that a large overshoot or undershoot does not occur at the time of start-up or gear shifting, and the steady rotation is smoothly entered quickly.

The lower limit value of the limiter 21 includes zero. In this case, the first counter 13 is reset from the reset terminal R. This is shown in FIG.

Reference numeral 25 is a signal distributor, which is composed of a signal MS including a T-FF (trigger flip-flop) 26 and AND gates 27a and 27b. Reference symbols T, Q ₁ and Q ₁ F are clock input terminals of T-FF26,
Positive output and negative output are shown. MS1 and MS2 are signals
The MS is alternately distributed into two series pulse trains. An example of the Q ₁ signal and MS1 and MS2 of this signal distributor 25 is shown in FIG.

Reference numeral 30 is a signal processing means including at least a frequency discriminator 31, and in FIG. 1 an acceleration detector 33 is also shown.

Reference numeral 32 denotes a logic circuit, which is the output Q ₂ of the frequency discriminator 31.
By taking the logics of Q2 and Q2 and outputs Q1 and Q1 of the T-FF26, a time width signal appears at uV when the speed is faster than the target speed, and at LV when the speed is slower than the target speed.

Reference numeral 34 is a logic circuit which outputs Q3 and Q of the acceleration detector.
3. Take the logic of the outputs Q1 and Q1 of T-FF26, and PA when the time width before the arrival time width of the signal MS is large, NA when it is small
A signal with a difference time width appears at.

A NOR gate 36 is provided to the AND-OR gate 12 to delete the clock φS. In this case, since the first counter 13 does not advance, the data in the latch circuit 14 has a small value.
The output control amount becomes small.

Numeral 37 is an OR gate which allows the clock .phi.B of the AND-OR gate 12 to pass therethrough, so that the first counter advances in many cases. In this case, the output control amount becomes large.

Thus, the operation of the phase detector 11 of the present invention is
By modulating the clock passing through the AND-OR gate 12 with the velocity or acceleration information, the advance / retard of the first counter is controlled to quickly reach the predetermined control amount. From this, a smooth transient response characteristic can be obtained.

Although the reference is delayed, since the input clock of the counter which constitutes the conventional phase detector is constant, it takes a complicated process to reach the predetermined amount of phase, so that the overshoot or undershoot becomes large and becomes a steady state. It may take time.

The release logic of uV, LV for velocity and PA, NA for acceleration described above will be described later in a specific circuit of FIG. These relationships are shown in FIG.

Reference numeral 35 in FIG. 1 is a logic circuit, which is uL if t <3 / 4To from the period To of the target speed of the signal MS, for example, as shown in FIG.
Then, if t> 5 / 4To, a pulse signal is generated in the LL.

The signal uL loads the lower limit value of the limiter 21 into the first counter 13, and the signal LL loads the upper limit value. As a result, over-regulation and over-energization in each speed mode are prevented. In FIG. 1, since the lower limit value is set to zero, the first
An example of using the reset terminal of the counter 13 will be shown.

The above is the gist of the present invention, and further mention is made that PID (proportional / integral / derivative) control is preferable in speed control, but I control is necessary when position control is included, but simply PD in speed control. Control is sufficient. Therefore, the present invention makes full use of PD control.

That is, since there is a large error in the control amount when the motor is started or when the gear is shifted, the transient response is improved by limiting the over / undercoat by setting the upper and lower limits of the control amount.

Near the steady state, P control or PD control is executed. Although P control is also provided in the phase detector 11 itself, signals uV, LV, and D control by the frequency discriminator 31 are executed by signals PA and NA by the acceleration detector 33.

Although not shown in the figure, how to operate these signals may be such that a plurality of clocks φB are provided and weighted respectively.

The release relationship of the controlled amount is shown in FIG. In FIG. 4, the cycles To ₁ and To ₂ for the target speeds A and B are shown. The shaded area is the free control range where P or PD control is working.

FIG. 6 shows the start-up characteristics when the motor is started under this control, and the characteristics without the upper and lower limit values for the speeds A and B are also shown. According to the present invention, smooth startup characteristics can be obtained.

Next, referring to FIG. 3, an example in which the frequency discriminator 31 and the acceleration detector, which are the features of the present invention, are simply configured simultaneously will be described.

The capacity of the second counter 41 becomes the cycle To of the target speed when the clock CA is generated and the carrier CA is generated. It is reset via the R terminal with signal MS ₁ . Four
3 is D-FF (delayed flip-flop, D, CK, R, Q
₂ and Q ₂ respectively represent data input terminal, clock input terminal, reset terminal, positive output and negative output. 47 has the same configuration as D-
It is FF. ) And is reset by signal MS ₁
Inverted signal by inverter 42 for positive output Q ₂ = 1
To Therefore, the second counter 41 and the D-FF 43 are on the time scale of the cycle To.

The logic circuit 32 is composed of AND gates 48a and 48b, and takes the logic from Q ₁ and Q ₁ of the signal distributor 25 to obtain the above uV and LV.
Generate.

Since the data input terminals of D-FFs 43 and 47 are connected to + 5V, once Q ₂ = 1 and Q ₃ = 1 are held until they are reset. Logic circuit 35 for generating signals uL and LL
Is generated by taking the logic of the signals LV and uV, and the upper bit of the second counter 41, which is 2 bits in the figure. The NAND gate 61 indicates that the content of the second counter 41 is 3 / 4To or less, and the OR gate 60
Indicates To + 1 / 4TO = 5 / 4To or more.

Therefore, the AND gate 64 allows MS ₂ to pass, and the time interval between MS ₁ and MS ₂ is t <3 / 4To, and the signal uL is generated. Even if the output of AND gate 62 is generated t> 5 / 4To, signal MS ₂
Is generated, and the signal LL is generated by the differentiating circuit 63 which takes out the front at the clock φS.

Next, the acceleration detector 33 will be described. The third counter 44 has a capacity of 1 bit larger than that of the second counter 41 in the figure. The T-FF 45 counts when the carrier CA occurs in the second counter 41. LD is a load signal input terminal to which the signal MS ₂ is added. If the negative outputs of the second counter 41 and T-FF45 are used as load data, the time interval t _{1 of} the signal MS shown in FIG.
_{t 2, t 3, t 4} , ··· t 2 n-1, t 2 n of _{t 1, t 3, ··· t} 2 n-1
Will be loaded. Of course, the second counter 41 and the third counter 44 are binary counters. 3rd counter
When CA is generated in 44, D-FF47 is sent via inverter 46.
Q _{3 of} 1 is set. This delays the time scale of t ₁ , t ₃ , ... T ₂ n-1, and the calculation of t ₂ n-1 −t ₂ n becomes possible. Time lag
Although t ₂ n-1 −t ₂ n does not directly represent the acceleration, it is an amount related to the speed difference and thus related to the acceleration. At present, t ₂ n can be represented by Q ₁ or Q ₁ , so the logic circuit 34 uses the negative acceleration NA and the positive acceleration PA of the time width in the AND gates 49b and 49a.
Can be calculated with.

When the acceleration detector 33 is provided, the emission control amount is not increased so much even when the negative velocity is the positive acceleration. If the acceleration is a positive speed but a negative acceleration, the phase detector 11 is operated so as not to reduce the emission control amount so much, and the rush time to the steady state can be reduced.

FIG. 2 illustrates these relationships without forming a control loop, assuming that a signal is generated as shown in the figure.

In FIG. 2, Tos represents the reference clock corresponding to the period To of the target speed. The D / A converted waveform of the phase difference is the control amount for the motor.

Next, an example of a circuit in which the lower limit value from the limiter 21, which is not shown in FIG.

The upper limit data is signal LL and the lower limit data is signal
uL switches with a predetermined number of AND-OR gates 72. The reason for adding the delay 71 is to ensure that the load data is loaded with a delayed timing. In this case, the R end of the first counter 13 is unnecessary.

Finally, the motor speed control device of the present invention is integrated into an IC.
The case of conversion will be described.

Although only FIG. 1 may be integrated into an IC, in practice, since it is often a brushless motor, a position detector amplifier of the motor rotor, a phase changeover switch, a forward / reverse rotation control circuit, a motor start / stop circuit, etc. If it is added, it becomes convenient to use.

The clock generator 10 includes a PLL (Phase Locked Loop) including a VCO (Balltage Control Oscillator) to support the speed mode of the model.
The configuration is such that the output clock frequency fx = n / mfs (s: reference frequency of crystal oscillator or the like, n, m: integer) determines n and m by speed data. For small motors with low power consumption (~ 30 watts), a power amplifier may also be inserted.

Although the explanation has been delayed, the frequency discriminator 31 and the acceleration detector 33 of the signal processing means 30 described in FIG. 3 are used twice, and one of them reverses the connection of the signals MS ₁ and MS _2. Then, by changing the logic circuits 32 and 34 and adding the logical sum of the respective signals, the information amount of the speed and the acceleration is doubled, and a more effective speed control characteristic can be obtained. Furthermore, in order to change the target speed, the capacities of the first counter 13 and the second counter 41 may be made variable.

[0052]

According to the configuration of the present invention described above, a simple signal processing means having a frequency discriminator or an acceleration detector can be used to cope with signals related to speed, signals related to acceleration, and speed modes. The effect of obtaining stable steady-state characteristics and smooth transient response characteristics with only one control amount by exerting the upper and lower limit control amount settings on the phase detector is great.

[Brief description of drawings]

FIG. 1 is a diagram showing a specific block configuration according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between operation signals of respective parts of FIG. 1 and a generation condition.

FIG. 3 is a diagram showing a specific circuit configuration in which a frequency discriminator and an acceleration detector, which are features of the present invention, are configured in common.

FIG. 4 is a diagram showing how to generate a control amount for a motor according to the present invention.

FIG. 5 is a diagram showing a specific circuit configuration for loading upper and lower limit values of a control amount, which is a feature of the present invention.

FIG. 6 is a diagram showing a motor starting characteristic according to the present invention.

FIG. 7 is a diagram showing a block configuration of an example according to a conventional technique.

FIG. 8 is a diagram showing the characteristic example of FIG. 7, in which (a) is a frequency discrimination output characteristic, (b) is a phase output characteristic, and (c) is a starting characteristic.

[Explanation of symbols]

7 Motor 8 Frequency generator MS, MS ₁ , MS ₂ Frequency generator signal, 2 series of signal sequence that alternately separates these signals 3, 11 Phase detector 4, 31 Frequency discriminator 18 D / A converter 2 , 10 Clock generator 21 Limiter 25 Signal distributor 13, 41, 44 1st, 2nd, 3rd counter 32, 34, 35 Logic circuit 14 Latch circuit uV, LV Positive and negative speed signal PA, NA Positive and negative Acceleration signals uL, LL Signals to load lower and upper limits

Claims (3)

[Claims] 1. A motor speed control device in which a phase difference between a signal from a frequency generator of a motor and a reference period signal corresponding to a target speed is D / A (digital / analog) converted to be a speed control amount of the motor. , A, a clock generator that generates a clock containing a reference clock that is modulated by speed. b, a signal distributor that generates the signal into a predetermined signal group. c, a first counter having a load means for counting the clock of the clock generator through a predetermined input means,
A phase detector whose main component is a latch circuit that always latches the data of the first counter with the signal. d, a D / A converter that D / A converts the data in the latch circuit to release the control amount to the motor. e, a limiter for setting upper and lower limit values of the control amount depending on the speed of the motor. f, each signal of the signal distributor comprises at least a frequency discriminator, and signal processing means for generating a signal for loading the data of the limiter into the first counter and a signal for giving to the input means of the first counter. The characteristic motor speed control device. 2. The motor according to claim 1, wherein an acceleration detector is added to the signal processing means, and control of the input means of the first counter is executed independently or jointly with the frequency discriminator 31. Speed control device. 3. An acceleration detector 33, the frequency discriminator 31.
3. The configuration according to claim 2, wherein the configuration is shared with the components.
The described motor speed control device.