JPH05103467A - Dc-dc converter - Google Patents

Abstract

PURPOSE:To enable a DC-DC converter to behave well at a high frequency and with a high efficiency and in a noiseless manner, by making a soft switching operation, wherein the switching operations of the voltage and the current of a main switching element are not varied quickly, executable, and by making the time, wherein the voltage of the main switching element overlaps with its current, short, and further, by reducing its switching loss. CONSTITUTION:In the transition times for making main switching elements Q1, Q4 change from ON-states to OFF-states, and vice versa, and in the similar transition times for main switching elements Q2, Q3 provided are respectively quiescent times. In these quiescent times, resonance operations are made to occur by parasitic capacitors C1-C4 parallel to the main switching elements Q1-Q4, choke coils L1, L2 and the inductances of main conversion transformers T1, T2, which are observed from their primary sides. Thereby, soft switching operations, wherein the switching operations of the voltages and currents of the main switching elements Q1-Q4 are not varied quickly, are made executable, and the time, wherein the voltage of the main switching element overlaps with its current, is made short, and its switching loss is made small even when operating at a high frequency. Thereby, a DC-DC converter can be made to behave well at a high frequency and with a high efficiency and in a noiseless manner.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a two-stone double forwarder.
The present invention relates to reduction of switching loss of a de-type converter circuit.

[0002]

2. Description of the Related Art FIG. 1 exemplifies a typical operation waveform of a conventional two-stone double forward type converter circuit, and FIG. 2 shows a typical operation waveform of the two-stone double forward type converter circuit of FIG. .. In FIG. 1, Q1 to Q4 are main switching elements, which are FETs. C1 to C4 and D1 to D4 are the parasitic capacitances built in the main switching element FETs Q1 to Q4 and (2) the parasitic diode. T1 to T2 are conversion transformers, L1 to
L2 is a leakage inductance of the converting transformer T1T2, D5 to D8 are diodes for resetting the main transformer, D9 and D10 are rectifying diodes, L3 is an output choke, C5 is a smoothing capacitor, and D11. Is the output choke L
Vcc, a diode that returns the energy stored in 3
Indicates a DC power supply. In the operation waveforms of FIG. 2, 1 is a drive signal of the main switches Q1 and Q2, 2 is a drive signal of the main switch elements Q3 and Q4, 3 and 4 are current and voltage waveforms of the main switch elements Q1 and Q2, Reference numerals 5 and 6 denote current and voltage waveforms of the main switching elements Q3 and Q4. Reference numerals 7 and 8 represent losses in the periods in which the current and voltage waveforms 3 to 6 of the main switches Q1 to Q4 overlap during switching. Conventionally, in this type of circuit, the main switching elements Q1 to Q4 are conducting,
When shutting off, switching loss as shown by 7 and 8 in FIG. 2 occurs. Further, when operated at a high frequency, the loss becomes remarkable at the time of charging / discharging from the parasitic capacitances C1 to C4 of the main switch elements Q1 to Q4, which makes it difficult to operate at high efficiency. Further, the parasitic inductances due to the leakage inductances L1, L2 and wirings of the main conversion transformer T1 and the parasitic capacitances C1 to C4 cause the operation waveform to vibrate at the time of switching and it is difficult to reduce noise.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems in the conventional circuit and to realize high frequency, high efficiency and low noise. Further, it is possible to reduce the difficulty in controlling the voltage and current stress of the main switching element and the constant voltage or current at the time of a light load, and the constant power control which are seen in the conventional quasi-resonant type.

The present invention relates to a double-stone double forward type converter. The two-stone double forward type converter is generally used for a converter having a high input voltage and a large output capacity. Since the two-stone double-forward converter uses two sets of ordinary two-stone forward converters, the conduction periods are shifted from each other by 18 (3) 0 degrees. As a result, the choke used for smoothing the output has a merit in that it can be downsized because the frequency doubled is applied and the main transformer is less likely to be biased.

Further, pulse width control (PWM method) is used to stabilize the output, and the switching loss of the main switch tends to increase as the frequency becomes higher. Further, the switching power supply has been in the direction of smaller size and lighter weight in recent years, and there is a strong demand for higher frequency of the switching power supply. However, as mentioned above, the switching loss increases and the switching frequency is 50KHZ in the converter with large output capacity.
The limit was ~ 100KHZ. Further, when the frequency is high, the noise generated increases, and it is difficult to take measures against noise. However, in recent years, with the advent of resonant converters, high-frequency, low-noise, high-efficiency switching power supplies have been put to practical use, but only a few have been put to practical use due to the difficulty of control, increased costs, etc. It is used only for. The present invention has been made in view of the above points, and an object of the present invention is to provide a two-stone double forward converter circuit that has extremely low switching loss and low noise even at high frequency operation.

[0006]

The present invention will be described below with reference to the drawings. FIG. 3 is a basic circuit diagram of a two-stone double forward converter circuit according to an embodiment of the present invention, and FIG. 4 shows operation waveforms of the two-stone double forward converter of the present invention shown in FIG. Reference numeral 5 represents an equivalent circuit in each operation mode of the present invention. As is clear from the comparison between the two in FIGS. 1 and 3, according to the present invention, the main transformers T1 and T2 of the conventional two-stone double forward converter circuit are connected to the + and-of the DC power source. Two of the diodes D5, D6, D7, and D8 are abolished, and the anode of the diode D5 is used as the drain of the main switching device Q4 and the cathode of the diode D6 as shown in FIG. The main conversion transformers T1 and T2 and the main switching devices Q1 and Q3 are connected to the sources of the main switching devices Q3, respectively.
Connect the choke L1 and (4) L2 between the terminals. The operation timings of the conventional main switching elements Q1 to Q4 are as shown in FIG.
Since the phases of 3 and Q4 are 180 degrees out of phase, the conduction and interruption operations are repeated, and the output is controlled by PWM control.

In the present invention, the operation timings of the main switch elements Q1 to Q4 are, as shown in a to d of FIG. 4, the main switch elements Q1, Q4 and Q2, and Q3, which conduct and cut off by signals shifted by 180 degrees from each other. I do. Further, the control for stabilizing the output is performed by fixing the phases of the main switching elements Q1 and Q4 (or Q2, Q3), and then the main switching elements Q2, Q3 (or Q1,
It is possible by shifting the phase of Q4). Further, a pause period is provided during a period in which the main switching elements Q1 and Q4 and Q2 and Q3 are turned off (or turned on), and parasitic capacitances C1 to C4 and chokes parallel to the main switching elements Q1 to Q4 are provided during this period. L1 and L2 and the inductance of the main conversion transformer T1 as viewed from the primary side cause resonance operation to cause soft switch operation in which the voltage and current switch operations of the main switch elements Q1 to Q4 do not change abruptly, and Voltage,
This is a two-stone double forward converter circuit capable of extremely reducing switching loss even in high frequency operation by extremely shortening the time when currents overlap with each other and performing low noise operation.

A detailed description will be given below of FIG. 3 which is a double-forward converter circuit of the present invention, FIG. 4 which shows operation waveforms, and an equivalent circuit diagram 5 which shows an operation mode. As shown in FIG. 3, main switch elements Q1 to Q4 (FETs are shown in this example) are connected to both + and-sides of the DC power supply VCC, and series connection is made from the source side of the main switch elements Q1 and Q3. One ends of choke coils L1 and L2 are connected to.
The main transformers T1 and T2 are connected in series from the other side of the choke coils L1 and L2, and the nodes of the main switching elements Q2 and Q4 described above are connected to the other side of the main transformer T1T2. The output diodes (5) D7, D8 and the output choke L3, the output smoothing capacitor C5, and the energy stored in the output choke L3 are fed back to the secondary side of the main transformers T1, T2. A load RL is connected to the output OUT. Parasitic capacitances C1 to C4 between the main switch elements Q1 to Q4 drain sources
And parasitic diodes D1 to D4 exist in parallel, and a diode D5D6 is connected between the drains of the main switching devices Q4 and Q2 and the source of Q1Q3. Although not shown in the figure, the main switching elements Q1 to Q4 are connected to the gates of the main switching elements Q1 to Q4.
A drive circuit for turning on and off 1 to Q4 is connected.

It is assumed that the symbols a to d shown in FIG. 4 are input to the gates of the main switching elements Q1 to Q4. Figure 4
Shows an operation waveform of each part of the operation circuit of the present invention, and a, b, c, d are main switching elements Q1, Q2,
Gate input voltage waveforms of Q3 and Q4, e and f are voltage waveforms of main switching elements Q4 and Q1, g and g'are main switching elements Q
1 and Q4 current waveform, h and i are switch element Q2 and Q3 voltage waveforms, j and j'are switch element Q2 and Q3 current waveforms,
k and l are the parasitic capacitances of the main switching elements Q1 and Q4, and C1 and C4.
Charge / discharge current waveform, m, n are parasitic capacitances of the main switching elements Q2, Q3, charge / discharge current waveforms of C2, C3, o, p are parasitic diode D1 built in the main switching elements Q1, Q4, Current waveforms flowing in D4, Q and R are current waveforms flowing in parasitic diodes D2 and D3 built in the main switch elements Q2 and Q3, and X and Y.
Represents the waveform of the current flowing in the diodes D5 and D6, Z represents the voltage waveform of the main conversion transformer T1, t1, t2, t3, t3 ',
t4, t5, and t6 represent representative times that are important in explaining the operation of the present invention.

Next, FIG. 5 will be described. MODE1 in FIG.
3 to 5 are equivalent circuits of FIG. 3, which is an embodiment of the present invention, for each period. In FIG. 5, L1 + LR1 represents the sum of the inductance of the choke coil L1 of FIG. 3 and the leakage inductance LR1 of the main transformer T1.
LO 'and LM1 represent the inductance value seen from the primary side of the main transformer T1 in FIG. 3 and the excitation (6) inductance value of the main conversion transformer. VO 'indicates the voltage generated on the primary side of the main transformer T1 in FIG. 3, and the diodes D5 and D6 are the same as the diodes D5 and D6 shown in FIG. Further, circled arrows 1 to 3 indicate constant current sources generated in the above-mentioned inductances, and IM1 and IO 'are exciting currents flowing in the exciting inductance LM1 of the main transformer T1.
The current obtained by converting the output current flowing on the secondary side of the main transformer T1 into the primary side is shown. IP represents the sum of the exciting current IM1 and the output current IO 'converted to the primary side. Reference numeral 4 shows an equivalent circuit of the two-stone forward converter on the other side of FIG. 3, but it is omitted because it has no relation to the operation of this description.
C4, C3 and VCC of 5 and 6 represent capacitors C3 and C4 connected in parallel to the main switches Q3 and Q4, respectively, and indicate that the DC power source VCC is charged.

Next, the main switching elements Q1 to Q4 of the two-stone forward converter circuit of the present invention shown in FIG.
A description will be given of the case of driving with the waveforms a to d shown in FIG. For convenience of explanation, it is assumed that the time is from t1 to t6, and the subsequent loopback operation is performed after that. Time t1 in FIG.
The operation mode from t2 to t2 is shown in MODE1 of FIG. 5, which is an equivalent circuit of the circuit diagram of this embodiment shown in FIG. As an initial condition, since the main switching elements Q3 and Q4 are in the cutoff state during this period, the parasitic capacitances C3 and C4 of the main switching elements Q3 and Q4 are the DC power source V.
It shall be charged to CC. The main switching element Q
It is assumed that 1 and Q2 are in a conductive state, and the applied voltages of the parasitic capacitances C1 and C2 connected in parallel to the main switch elements Q1 and Q2 are almost zero volt. Therefore, g and j shown in FIG. 4 flow through the main switch elements Q1 and Q2. After time T2 in FIG. 4, g and j are picked up by the choke L3 in FIG.
Reaches the black level IP1. This MODE1 is a period during which energy is transferred to the load RL, and changes depending on the size of the load RL.

Next, the period from t2 to t3 in FIG. 4, that is, M in FIG.
The ODE2 will be described. When the main switching element Q1 in FIG. 3 (7) is turned off, the current g immediately before the interruption occurs because the current g of the main switching element Q1 in FIG. 4 continues to flow with IP1 as the initial condition, so the capacitor C1 in parallel with the main switching element Q1 in FIG. The capacitor C4 in parallel with the main switch element Q4 was charged up to the power supply voltage Vcc at the same time as the charge was charged, but is discharged through L1 + LR, L0, LM1. Therefore, the voltage between the drain and the source of the main switching elements Q1 and Q4 starts to rise and fall slowly as shown in f and e of FIG. 4, and at time t3 of FIG. It is charged to the voltage Vcc and the switch element Q4 is discharged to zero volts. Therefore, the main switching element Q1
Enables so-called zero volt switching in which voltage and current do not cross, and switching loss is extremely reduced.

The relational expression at this time can be expressed by the following expression. VCC (tX) = VCC (1-cosω1t) -V0 '(1-cosω1t) + IP / W1 (C1 + C4) ∴W = 1 / √ ・ {(L1' + LR) + LM / L0 '} (C1 + C4) VC4 (tx) = VCC-VC1 (t) IP1 = IM1 + I0 'VC1 (tx) = IP / (C1 + C4) .t ∴t = t2-t1 = VCC. (C1 + C4) / IP1 However, tx is any value between t1 and t2. And the period.

Therefore, the time when the parasitic capacitances C1 and C4 in parallel with the main switching devices Q1 and Q4 of FIG. 3 are charged to the DC power supply VCC and the time when the parasitic capacitance C4 is discharged from the DC power supply VCC to almost zero volt. It can be seen that t changes depending on the magnitude of the current IP1 flowing through the main switch element Q1 and the parasitic capacitances C1 and C4. The current IP1 flows through the power source side and the feedback diode D5 after the time t3, and finally becomes IP2, which is expressed by the following equation.

IP2 = IP1 − {(V0′−VCC−D5VF) (t3−t2) / (L1 + LR1 + LM1 / L0) (8) + (V0′−VCC−Q2V05 (ON)) (t3−t2) / (L1 + LR1 + LM1 / L0 ')} where D5VF is the forward voltage of diode D5, Q2V05
(ON) is the ON voltage between the drain and source of switch Q2.

Next, the period from t3 to t4 in FIG. 4 will be described. During this period, as shown in FIG. 4, the main switch elements Q1 and Q3 are cut off, Q2 is in the conductive state, and Q4 is in the conductive state at time t3 '. Therefore, when this period is represented by an equivalent circuit, MODE 3 in FIG. 5 is obtained. During this period, the energy stored in L1 + LR1 which is the sum of the leakage inductance LR1 of the choke coil L1 of FIG. 3 and the main transformer T1 is the diode D4 and the diode which are in parallel with the main switch element Q4 with IP2 as the initial condition. It is a mode in which the ring goes through the mode D5. At time t4, the current ID flowing through the main switch Q2 is obtained by the following equation.

IP3 = IP2 − {(t4−t3) · (D5VF + D4VF) / (L1 + LR1)} where IP3: current of the main switch Q2 at time t4 ID D4VF: forward direction of diode parallel to the main switching element Q4 Voltage

At t3 'during this period, the main switching element Q4
Is turned on, but it is turned on while the current ID is flowing in the parallel diode D4, but at time t3 in FIG. 4, the voltage of the parasitic capacitance C4 in parallel with the main switch element Q4 has almost reached 0 volt. It can be seen that the voltage and current switching loss of the main switch element Q4 does not occur because the discharge occurs.

Next, the period from time t4 to t5 will be described. This period is a period in which the main switching devices Q1 and Q3 are in the cutoff state, Q2 is in the cutoff state at time t4, and Q4 is in the conduction state from FIG. 4, and the equivalent circuit example of this embodiment circuit in FIG. Equivalent to. During this period, since the main switching element Q2 is cut off at time t4, the sum of the leakage inductance (9) LR1 of the choke coil L1 and the main transformer T1, L1
The energy stored in + LR1 is the parasitic capacitance C2 in parallel with the main switch element Q2 from 0 volt to the DC power supply Vcc due to the current IP3. L1 + R1 and diode D
Parasitic capacitance C of 6 in FIG. 5 is charged through 4, D5 and is charged in parallel to the main switch element Q3 up to the DC power supply Vcc.
3 to almost zero volt L1 + LR1 and diode D6
To discharge through. The relational expression at this time can be expressed by the following expression.

VC2 (t) = (IP3 / 2) ・ √ ・ (L1 + LR1) / C2 ・ Sinω2t W2 = 1 / √ ・ (L1 + LR1) (C3 + C4) VC3 (t) = VCC-VC2 (t) where D4VOF: Daio -Forward voltage of D4 VC2 (t): voltage of capacitor C2 at any time between t4 and t5 VC3 (t): voltage of capacitor C3 at any time between t4 and t5

Therefore, the voltage of the main switch element Q2 is at time t4.
As it rises more slowly and Q3 falls gradually,
It can be seen that the switching loss of the main switch element Q2 does not occur. At this time, the current IP4 after the completion of charging / discharging of C2 and C3
Is expressed by the following equation.

IP4 = IP3- (D4VF + D5VF) / (L1 + LR
1)

Next, the times t5 to t6 will be described. This period is a period in which the main switches Q1 and Q2 are cut off, Q3 is turned on at time tb from the cutoff, and Q4 is turned on according to FIG. 4, and the equivalent circuit example of this embodiment shown in FIG.
It becomes DE5. During this period, the current I P4 of 1 in FIG. 5 is the diode D due to the energy stored in the leakage inductance of the choke coil L1 and the main transformer T1 in the MODE4.
6, D3 and the DC power supply Vcc and the diodes D4 and D5 are discharged. By eliminating the switching loss of the main switching element Q3 by conducting the main switching element (10) Q3 during the period in which the current r flowing through the diode D3 in parallel with the main switching element Q3 continues to flow at time t6 in FIG. Understand. The current r flowing through the diode D3 and the magnitude IP5 at the time t6 can be obtained by the following equation.

IP5 = IP4− (VCC + D6VF + D3VF + D4VF + D5VF) (t6−t5) / (L1 + LR1)

In FIG. 4, after the time t6, it can be easily inferred that no loss occurs at the time of switching by carrying out the flyback as described above. As described above, in the present description, the main switch element has been described as an FET, but it is obvious that other elements can be applied. Therefore, in the embodiment circuit example of FIG. 3, the explanation has been made by using the parasitic capacitances C1 to C4 and the parasitic diodes D1 to D4 in parallel with the main switch elements Q1 to Q4. It is sufficiently possible to connect in parallel to Q4 to perform the above operation.

[0026]

According to the present invention, in a two-stone type double forward converter in which the main transformer is less likely to be biasedly excited, the energy of switching is returned to the power source so that the converter having a relatively large capacity can be used. It is possible to realize low noise, high efficiency, and miniaturization, which is a great industrial effect.

[Brief description of drawings]

FIG. 1 Conventional two-stone double forward converter

[Fig. 2] Operation waveform of a conventional circuit

FIG. 3 is a two-stone double forward converter of the present invention.

FIG. 4 is an operation waveform (11) of the circuit of the present invention.

FIG. 5: Equivalent circuit of each operation mode of the circuit of the present invention

[Explanation of symbols]

Q1 to Q4 Main switch element D1 to D4 Parasitic diode or external diode T1, T2 Main conversion transformer D5 to D11 Diode L1, L2 Leakage inductance or external inductance C1 to C4 Parasitic capacitor or Externally installed capacitor C5 Smoothing capacitor V CC DC power supply RL load LR1 Leakage inductance of main transformer T1 L0 'Primary transformer equivalent inductance of main transformer T1 LM1 Main transformer T1 excitation inductance V0' Primary voltage equivalent of output voltage 1 L1 + LR1 Constant current source, IP
= IM + IO IM Excitation current stored in excitation inductance LM1 3 Current I0'4 obtained by converting the output current to the primary side 4 Equivalent circuit of the other two-stone converter 5 Charge state of DC power supply VCC of capacitor C4 6 Capacitor C3 Charge state of DC power supply VCC VCC DC power supply

Claims (1)

[Claims] 1. A combination of two sets of two-stone forward type converters in which a main transformer is connected between two switching elements each having one end connected to the + side and the-side of a power supply line. In a DC-DC converter for supplying a set of direct current output, a leakage inductance or an external inductance is provided in series with each of the main transformers, and parasitic parallel to each of the switch elements. Capacitor or external capacitor is connected to a set of two stone forward type converters.
Drain or collector of the switching element connected to the side power supply line and another pair of two-stone forward type converter
A diode is connected to the source or the emitter of the switching element connected to the positive side power supply line of the switch so as to be in the forward direction, and the other one pair of forward type forward converters. A drain or collector of the switching element connected to the negative (-) side power supply line, and a source or emitter of the switching element connected to the positive (+) side power supply line of the pair of two-stone forward type converters. A DC-DC converter characterized in that a diode is connected in a forward direction between the two.